CN116259534A - Silicon carbide epitaxy method - Google Patents
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Abstract
The invention relates to the technical field of silicon carbide epitaxy, in particular to a silicon carbide epitaxy method. The silicon carbide epitaxy method comprises the following steps: performing in-situ etching on the silicon carbide substrate; depositing a first epitaxial layer on one side surface of a silicon carbide substrate, wherein the deposition rate of the first epitaxial layer is 60-80 mu m/h; depositing a first buffer layer on one side of the first epitaxial layer; a second epitaxial layer is deposited on a surface of the first buffer layer on a side facing away from the silicon carbide substrate. In the rapid deposition process of the first epitaxial layer, C atoms and Si atoms are accumulated and deposited at pit defects, so that part of pit defects can be filled up, the number of pit defects on the surface of silicon carbide is reduced, the surface of the second epitaxial layer has fewer pit defects, the preparation requirements of a semiconductor device are easily met, and the overall performance of the silicon carbide semiconductor device is improved.
Description
Technical Field
The invention relates to the technical field of silicon carbide epitaxy, in particular to a silicon carbide epitaxy method.
Background
With the increasing demands of semiconductor devices in the fields of aerospace, military, radar, electric vehicles and the like, silicon-based semiconductor devices cannot meet the increasing use demands. Silicon carbide has the excellent characteristics of large forbidden bandwidth, excellent stability, high thermal conductivity, high critical breakdown field strength, high saturated electron drift velocity and the like, and is an ideal semiconductor material for manufacturing high-temperature, high-frequency, high-power and strong-radiation power electronic devices. Compared with the traditional silicon-based semiconductor device, the silicon carbide device can normally work under the electric field intensity which is 10 times that of the silicon-based semiconductor device, and has excellent performance.
However, the performance of the semiconductor device directly fabricated on the surface of the silicon carbide substrate is not good because the silicon carbide substrate has various defects such as pit defects and the like. In order to improve the performance of semiconductor devices, it is generally necessary to perform high-quality silicon carbide homoepitaxy on a silicon carbide substrate to obtain an epitaxial wafer, and to perform the preparation of semiconductor devices on the epitaxial wafer.
The typical silicon carbide epitaxy process includes the steps of: firstly, a chemical vapor deposition process is adopted to deposit a buffer layer on the surface of a silicon carbide substrate, and then a chemical vapor deposition process is adopted to deposit an epitaxial layer on the surface of one side of the buffer layer, which is away from the silicon carbide substrate, and the buffer layer can improve the quality of the epitaxial layer. However, the buffer layer cannot transition pit defects on the surface of the silicon carbide substrate, so that the pit defects on the surface of the silicon carbide substrate extend to the epitaxial layer, and the epitaxial layer still has a certain number of pit defects, so that the total number of defects on the surface of the silicon carbide epitaxial wafer cannot be effectively controlled, and the silicon carbide epitaxial wafer cannot be guaranteed to meet the preparation requirements of semiconductor devices.
Disclosure of Invention
The invention aims to effectively reduce the total amount of defects on the surface of the silicon carbide epitaxial wafer.
To this end, the invention proposes a silicon carbide epitaxy method comprising: providing a silicon carbide substrate; performing in-situ etching on the silicon carbide substrate; after in-situ etching is carried out on the silicon carbide substrate, a first epitaxial layer is deposited on one side surface of the silicon carbide substrate, and the deposition rate of the first epitaxial layer is 60-80 mu m/h; depositing a first buffer layer on one side of the first epitaxial layer away from the silicon carbide substrate; and depositing a second epitaxial layer on the surface of one side of the first buffer layer, which is away from the silicon carbide substrate. In the rapid deposition process of the first epitaxial layer, C atoms and Si atoms are accumulated and deposited at pit defects, so that part of pit defects can be filled up, the number of pit defects on the surface of silicon carbide is reduced, and the surface of the second epitaxial layer has fewer pit defects; meanwhile, the first buffer layer can be used for transiting other defects such as at least partial basal plane dislocation and the like on the surface of the first epitaxial layer to a certain extent, so that the number of other defects on the surface of the second epitaxial layer is controlled. Therefore, the silicon carbide epitaxial method can effectively reduce the total amount of defects on the surface of the silicon carbide epitaxial wafer, and the prepared silicon carbide epitaxial wafer easily meets the preparation requirements of the semiconductor device, so that the overall performance of the silicon carbide semiconductor device is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the description of the embodiments will be briefly described below:
FIG. 1 is a process flow diagram of a silicon carbide epitaxy method provided by an embodiment of the present invention;
fig. 2 to 8 are schematic structural diagrams during silicon carbide epitaxy according to an embodiment of the present invention;
reference numerals:
a 1-silicon carbide substrate; 2-a first epitaxial layer; 3-a first buffer layer; 4-a second epitaxial layer; 5-a second buffer layer.
Detailed Description
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. In the description of the present invention, it should be noted that the terms "first," "second," and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Referring to fig. 1, the present embodiment provides a silicon carbide epitaxy method, including:
step S1, providing a silicon carbide substrate;
s2, performing in-situ etching on the silicon carbide substrate;
s3, after in-situ etching is carried out on the silicon carbide substrate, depositing a first epitaxial layer on one side surface of the silicon carbide substrate, wherein the deposition rate of the first epitaxial layer is 60-80 mu m/h;
step S4, depositing a first buffer layer on one side of the first epitaxial layer away from the silicon carbide substrate;
and S5, depositing a second epitaxial layer on the surface of one side of the first buffer layer, which is away from the silicon carbide substrate.
According to the silicon carbide epitaxial method provided by the embodiment, in the rapid deposition process of the first epitaxial layer, C atoms and Si atoms are accumulated and deposited at pit defects, so that part of pit defects can be filled up, the number of pit defects on the surface of silicon carbide is reduced, and the surface of the second epitaxial layer has fewer pit defects; meanwhile, the first buffer layer can be used for transiting other defects such as at least partial basal plane dislocation and the like on the surface of the first epitaxial layer to a certain extent, so that the number of other defects on the surface of the second epitaxial layer is controlled. Therefore, the silicon carbide epitaxial method can effectively reduce the total amount of defects on the surface of the silicon carbide epitaxial wafer, and the prepared silicon carbide epitaxial wafer easily meets the preparation requirements of the semiconductor device, so that the overall performance of the silicon carbide semiconductor device is improved. Specifically, the pit defects on the surface of the silicon carbide epitaxial wafer with the diameter of 150 mm prepared by the preparation method of the embodiment are less than 1000.
Specifically, in this embodiment, the first epitaxial layer, the first buffer layer, and the second epitaxial layer are all deposited by using a chemical vapor deposition process, where the chemical vapor deposition process (CVD) in this embodiment may be one of horizontal hot-wall CVD and vertical hot-wall CVD, and the chemical vapor deposition process is used to prepare a silicon carbide epitaxial wafer, so that the flow of the reaction gas can be precisely controlled, and thus the composition, thickness, and doping concentration of the epitaxial material can be precisely controlled, and the grown epitaxial material has good uniformity and a large doping range.
The silicon carbide epitaxy method provided in this embodiment is described in detail and fully below with reference to fig. 2-8.
Referring to fig. 2, a silicon carbide substrate 1 is provided.
Specifically, the silicon carbide substrate 1 may be an off-axis silicon carbide substrate or a zero-offset silicon carbide substrate. The off-axis silicon carbide substrate includes, but is not limited to, a 4 off-axis 4H-SiC substrate or an 8 off-axis 4H-SiC substrate. Compared with a zero-bias silicon carbide substrate, the 4-H-SiC substrate with the 4-degree off-axis can grow a 4H-SiC film with better quality.
Further, before epitaxial growth is performed on the surface of the silicon carbide substrate 1, the silicon carbide substrate 1 needs to be sequentially subjected to ultrasonic cleaning and in-situ etching.
The step of ultrasonically cleaning the silicon carbide substrate 1 includes: ultrasonic cleaning is carried out on the silicon carbide substrate 1 by using acetone for 10-15 min so as to remove impurities such as metal impurities and greasy dirt on the surface of the silicon carbide substrate 1; ultrasonically cleaning the silicon carbide substrate 1 by using absolute ethyl alcohol for 10-15 min to remove residual acetone on the surface of the silicon carbide substrate 1; ultrasonic cleaning is carried out on the silicon carbide substrate 1 by using deionized water to remove absolute ethyl alcohol remained on the surface of the silicon carbide substrate 1, wherein the cleaning time is 10-15 min; after the ultrasonic cleaning of the deionized water is finished, the silicon carbide substrate 1 is dried by using high-purity argon gas, so that water marks are prevented from being left on the surface of the silicon carbide substrate 1. For example, the ultrasonic cleaning time of each solution may be 10min, 11min, 12min, 13min, 14min or 15min, and the ultrasonic cleaning time of each solution may be the same or different.
The step of in-situ etching the silicon carbide substrate 1 includes: placing the silicon carbide substrate 1 subjected to ultrasonic cleaning into a deposition chamber of a chemical vapor deposition device; vacuumizing the deposition chamber until the vacuum degree of the deposition chamber is 40 mbar-150 mbar; introducing high-purity hydrogen into the deposition chamber, wherein the flow rate of the high-purity hydrogen is 100L/min-120L/min, for example, the flow rate of the high-purity hydrogen is 100L/min, 110L/min or 120L/min, so that the vacuum degree of the deposition chamber is maintained at 40 mbar-150 mbar; raising the temperature of the deposition chamber to stabilize the temperature of the deposition chamber to 1580-1630 ℃, and carrying out in-situ etching on the silicon carbide substrate 1 for 2-5 min to remove surface damage and scratches on the surface of the silicon carbide substrate 1.
Referring to fig. 3, a chemical vapor deposition process is adopted to deposit a first epitaxial layer 2 on one side surface of the silicon carbide substrate 1, the deposition rate of the first epitaxial layer 2 is 60 μm/h to 80 μm/h, and the thickness of the first epitaxial layer 2 can be 2 μm to 8 μm. By way of example, the deposition rate of the first epitaxial layer 2 may be 60 μm/h, 65 μm/h, 70 μm/h, 75 μm/h or 80 μm/h, and the thickness of the first epitaxial layer 2 may be 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm or 8 μm. Preferably, the thickness of the first epitaxial layer 2 is 2 μm-4 μm, and the first epitaxial layer with the above thickness range is advantageous for obtaining a silicon carbide epitaxial wafer with fewer pit defects.
Specifically, after the in-situ etching is finished, a small flow of reaction gas is introduced into the deposition chamber, and at this time, the hydrogen with a relatively large flow plays a role of carrier gas, and the deposition rate of the first epitaxial layer 2 is mainly determined by the flow of the reaction gas. In the deposition process of the first epitaxial layer 2, the reaction gas comprises a carbon source and a silicon source, the flow rate of the silicon source is 300 sccm-426 sccm, and the carbon-silicon ratio C/Si of the deposition chamber is 0.8-0.9. The silicon source comprises at least one of silane, trichlorosilane, dichlorosilane, silicon tetrachloride and methyl silicon trichloride, the carbon source is at least one of propane, ethylene, chloromethane and methane, and the flow rate of the carbon source is determined by the material of the carbon source, the flow rate of the silicon source and the carbon-silicon ratio of the deposition chamber. Illustratively, the silicon source flow rate may be 300 sccm, 316 sccm, 320 sccm, 350 sccm, 380 sccm, 400 sccm, or 426 sccm, and the deposition chamber carbon to silicon ratio C/Si may be 0.8, 0.83, 0.85, 0.87, or 0.9. The carbon-silicon ratio in the present application refers to the ratio of the amount of the substance of the carbon element to the silicon element in the deposition chamber.
Further, in the deposition process of the first epitaxial layer 2, the temperature of the deposition chamber is 1570 ℃ to 1610 ℃, the vacuum degree of the deposition chamber is 40 mbar to 150 mbar, the Si/H ratio in the deposition chamber is 0.0027 to 0.0038, and the vacuum degree and the Si/H ratio of the deposition chamber are regulated and controlled by regulating and controlling the flow of the reaction gas and the carrier gas. Illustratively, the Si/H ratio within the deposition chamber may be 0.0027, 0.003, 0.00316, 0.0032, or 0.0038. The silicon-hydrogen ratio in the present application refers to the ratio of the amounts of silicon element and hydrogen element substances in the deposition chamber.
Referring to fig. 4, a chemical vapor deposition process is adopted to deposit a first buffer layer 3 on the side, away from the silicon carbide substrate 1, of the first epitaxial layer 2, the deposition rate of the first buffer layer 3 is 7-11 μm/h, and the thickness of the first buffer layer 3 is 0.6-1 μm. By way of example, the deposition rate of the first buffer layer 3 may be 7 μm/h, 7.5 μm/h, 8 μm/h, 8.5 μm/h, 9 μm/h, 9.5 μm/h, 10 μm/h, 10.5 μm/h or 11 μm/h, and the thickness of the first buffer layer 3 may be 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm or 1 μm.
Specifically, in the deposition process of the first buffer layer 3, the carbon-silicon ratio of the deposition chamber is 0.5-0.6, the flow rate of the silicon source is 61 sccm-96 sccm, and the flow rate of the carbon source is determined by the specific material of the carbon source, the flow rate of the silicon source and the carbon-silicon ratio of the deposition chamber; that is, after the first epitaxial layer 2 is deposited to a desired thickness, the flow of the reaction gas is regulated to perform the deposition of the first buffer layer 3, the reaction gas in the deposition process of the first buffer layer 3 is the same as the reaction gas in the deposition process of the first epitaxial layer 2, and the deposition rate of the first buffer layer 3 is the normal deposition rate of the buffer layer. Illustratively, the silicon source flow rate may be 61 sccm, 66 sccm, 70 sccm, 79 sccm, 85sccm, 90sccm, 93sccm, or 96 sccm, and the deposition chamber may have a carbon to silicon ratio C/Si of 0.5, 0.53, 0.55, 0.57, or 0.6.
Further, in the deposition process of the first buffer layer 3, the temperature of the deposition chamber is 1570 ℃ to 1610 ℃, the vacuum degree of the deposition chamber is 40 mbar to 150 mbar, the Si/H ratio in the deposition chamber is 0.00061 to 0.00079, and the vacuum degree and the Si/H ratio of the deposition chamber are regulated and controlled by regulating and controlling the flow of the reaction gas and the carrier gas. Illustratively, the Si/H ratio within the deposition chamber may be 0.00061, 0.00069, 0.00070, or 0.00079.
Referring to fig. 5, a second epitaxial layer 4 is deposited on the surface of one side, facing away from the silicon carbide substrate 1, of the first buffer layer 3 by a chemical vapor deposition process, the deposition rate of the second epitaxial layer 4 is 20-40 μm/h, and the thickness of the second epitaxial layer 4 is 8-12 μm. The deposition rate of the second epitaxial layer 4 may be, for example, 20 μm/h, 25 μm/h, 30 μm/h, 35 μm/h or 40 μm/h, and the thickness of the second epitaxial layer 4 may be 8 μm, 9 μm, 10 μm, 11 μm or 12 μm.
Specifically, in the deposition process of the second epitaxial layer 4, the carbon-silicon ratio of the deposition chamber is 0.5-1, the flow rate of the silicon source is 110 sccm-216 sccm, and the flow rate of the carbon source is determined by the specific material of the carbon source, the flow rate of the silicon source and the carbon-silicon ratio of the deposition chamber; that is, after the first buffer layer 3 is deposited to a desired thickness, the flow rate of the reaction gas is regulated to perform deposition of the second epitaxial layer 4, the reaction gas in the deposition process of the second epitaxial layer 4 is the same as the reaction gas in the deposition process of the first epitaxial layer 2, and the deposition rate of the second epitaxial layer 4 is the normal deposition rate of the epitaxial layer. Illustratively, the silicon source flow rate may be 110 sccm, 135 sccm, 162 sccm, or 216 sccm and the deposition chamber carbon to silicon ratio C/Si may be 0.5, 0.6, 0.7, 0.8, 0.9, or 1.
Further, in the process of depositing the second epitaxial layer 4, the temperature of the deposition chamber is 1570-1610 ℃, the vacuum degree of the deposition chamber is 40-150 mbar, the Si/H ratio in the deposition chamber is 0.0011-0.00216, and the vacuum degree and the Si/H ratio of the deposition chamber are regulated by regulating and controlling the flow of the reaction gas and the carrier gas. Illustratively, the Si/H ratio within the deposition chamber may be 0.0011, 0.00135, 0.00162, or 0.00216.
It should be noted that the rapid deposition of the first epitaxial layer causes the surface thereof to have many other defects, which are defects that do not belong to the pit defect, such as basal plane dislocation, etc. On the one hand, the first buffer layer 3 is able to transition at least part of the other defects of the surface of the first epitaxial layer 2 to such an extent that at least part of the other defects of the surface of the first epitaxial layer 2 do not extend to the surface of the second epitaxial layer 4; on the other hand, the second epitaxial layer 4 surface deposited at the normal deposition rate also has fewer other defects, eventually leading to fewer other defects on the second epitaxial layer 4 surface. Therefore, the silicon carbide epitaxial method provided by the embodiment can control the number of concave defects and the number of other defects at the same time, so that the total number of defects on the surface of the silicon carbide epitaxial wafer is controlled, and the preparation requirement of a semiconductor device is more easily met.
In addition, the reaction gas in the embodiment further includes a doping source, the silicon source and the carbon source are introduced into the deposition chamber together, the flow rate of the doping source is determined according to the doping concentration, and the silicon carbide substrate 1, the first epitaxial layer 2, the first buffer layer 3 and the second epitaxial layer 4 all have the same doping type; when the doping type is n-type, the doping source may be nitrogen; when the doping type is p-type, the doping source may be trimethylaluminum.
As a preferred embodiment, the doping concentration of the first epitaxial layer 2 is smaller than the doping concentration of the silicon carbide substrate and greater than the doping concentration of the second epitaxial layer 4. The doping concentration of the first epitaxial layer 2 is located between the doping concentration of the silicon carbide substrate and the doping concentration of the second epitaxial layer 4, so that the number of basal plane dislocations can be reduced, the total number of defects on the surface of the silicon carbide epitaxial wafer is further reduced, the quality of the silicon carbide epitaxial wafer is improved, and the overall performance of the silicon carbide semiconductor device can be further improved.
Specifically, the doping concentration of the silicon carbide substrate is 1×10 18 atom/cm 2 ～3×10 18 atom/cm 2 The doping concentration of the first epitaxial layer 2 is 1×10 15 atom/cm 2 ~1×10 17 atom/cm 2 The doping concentration of the second epitaxial layer 4 is 5×10 15 atom/cm 2 ~1×10 16 atom/cm 2 The doping concentration of the first buffer layer 3 is 5×10 17 atom/cm 2 ~1×10 18 atom/cm 2 . The silicon carbide substrate may have a doping concentration of 1×10 18 atom/cm 2 、2×10 18 atom/cm 2 、3×10 18 atom/cm 2 The doping concentration of the first epitaxial layer 2 may be 1×10 15 atom/cm 2 、5×10 15 atom/cm 2 、7.5×10 15 atom/cm 2 、1×10 16 atom/cm 2 、5×10 16 atom/cm 2 Or 1X 10 17 atom/cm 2 The doping concentration of the second epitaxial layer 4 may be 5×10 15 atom/cm 2 、6×10 15 atom/cm 2 、7×10 15 atom/cm 2 、8×10 15 atom/cm 2 、9×10 15 atom/cm 2 Or 1X 10 16 atom/cm 2 The doping concentration of the first buffer layer 3 may be 5×10 17 atom/cm 2 、6×10 17 atom/cm 2 、7×10 17 atom/cm 2 、8×10 17 atom/cm 2 、9×10 17 atom/cm 2 Or 1X 10 18 atom/cm 2 。
As a preferred embodiment, referring to fig. 6-8, a chemical vapor deposition process is used to grow a second buffer layer 5 on the surface of the side of the first epitaxial layer 2 facing away from the silicon carbide substrate 1, before depositing the first buffer layer 3 on the side of the first epitaxial layer 2 facing away from the silicon carbide substrate 1; after the first buffer layer 3 is deposited on the side, away from the silicon carbide substrate 1, of the first epitaxial layer 2, the second buffer layer 5 is located between the first buffer layer 3 and the first epitaxial layer 2, the deposition rate of the second buffer layer 5 is 1-3 μm/h, and the thickness of the second buffer layer 5 is 0.1-0.3 μm. The second buffer layer 5 and the first buffer layer 3 can transition at least part of other defects such as basal plane dislocation and triangle on the surface of the first epitaxial layer 2 to a certain extent, so that at least part of other defects on the surface of the first epitaxial layer 2 cannot extend to the surface of the second epitaxial layer 4, and the number of other defects on the surface of the second epitaxial layer 4 is further reduced; meanwhile, the deposition rate of the second buffer layer 5 is smaller than the normal deposition rate of the buffer layer, and the slowly grown second buffer layer 5 has higher crystallization performance, so that the crystallization of the subsequently deposited first buffer layer 3 and second epitaxial layer 4 can be improved, the quality of the silicon carbide epitaxial wafer is further improved, and the overall performance of the silicon carbide semiconductor device can be further improved. The deposition rate of the second buffer layer 5 may be 1 μm/h, 1.5 μm/h, 2 μm/h, 2.5 μm/h, or 3 μm/h, and the thickness of the second buffer layer 5 may be 0.1 μm, 0.2 μm, or 0.3 μm, for example.
Specifically, in the deposition process of the second buffer layer 5, the carbon-silicon ratio of the deposition chamber is 0.6-0.65, the flow rate of the silicon source is 8 sccm-27 sccm, and the flow rate of the carbon source is determined by the specific material of the carbon source, the flow rate of the silicon source and the carbon-silicon ratio of the deposition chamber; that is, after the first epitaxial layer 2 is deposited to a desired thickness, the flow rate of the reaction gas is regulated to deposit the second buffer layer 5, the reaction gas in the deposition process of the second buffer layer 5 is the same as the reaction gas in the deposition process of the first buffer layer 3, the reaction gas comprises a silicon source, a carbon source and a doping source, the flow rate of the doping source is determined according to the doping concentration, and the doping concentration of the second buffer layer 5 is 5×10 17 atom/cm2~1×10 18 The doping concentration of the second buffer layer 5 may be the same as the doping concentration of the first buffer layer 3 or may be different from the doping concentration of the first buffer layer 3. Illustratively, the silicon source flow rate may be 8 sccm, 8.7 sccm, 10 sccm, 15 sccm, 18 sccm, 21 sccm, 24 sccm, 26 sccm, or 27 sccm, and the deposition chamber carbon to silicon ratio C/Si may be 0.6, 0.61, 0.62, 0.63, 0.64, or 0.65.
Further, in the deposition process of the second buffer layer 5, the temperature of the deposition chamber is 1570 ℃ to 1610 ℃, the vacuum degree of the deposition chamber is 40 mbar to 150 mbar, the Si/H ratio in the deposition chamber is 0.00055 to 0.0006, and the vacuum degree and the Si/H ratio of the deposition chamber are regulated and controlled by regulating and controlling the flow of the reaction gas and the carrier gas. Illustratively, the Si/H ratio within the deposition chamber may be 0.00055, 0.00058, 0.00059, or 0.0006.
During the deposition of the first epitaxial layer 2, the second buffer layer 5, the first buffer layer 3 and the second epitaxial layer 4, the temperature of the deposition chamber may be kept constant or slightly fluctuating.
After the second epitaxial layer 4 is deposited, stopping introducing reaction gas, wherein the reaction gas comprises a silicon source, a carbon source and a doping source, and stopping heating to gradually reduce the temperature in the deposition chamber to room temperature; discharging hydrogen, then introducing argon into the deposition chamber, and opening the bin to take out the sheet after the pressure in the deposition chamber reaches the atmospheric pressure.
In order to make the technical problems, technical schemes and beneficial effects solved by the embodiments of the present application more clear, the following will be described in further detail with reference to the embodiments and the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the application, or its uses. All other embodiments, based on the embodiments herein, which are within the scope of the protection of the present application, will be within the skill of one of ordinary skill in the art without undue burden.
Example 1
The embodiment provides a silicon carbide epitaxy method, which comprises the following steps:
providing a 4 DEG off-axis 4H-SiC substrate with a diameter of 150 mm, wherein the silicon carbide substrate has a doping type of n type and a doping concentration of 3×10 18 atom/cm 2 ；
Ultrasonic cleaning is carried out on the silicon carbide substrate: ultrasonically cleaning the silicon carbide substrate by using acetone for 15min; ultrasonically cleaning the silicon carbide substrate for 15min by using absolute ethyl alcohol; ultrasonically cleaning the silicon carbide substrate by using deionized water for 15min; after the ultrasonic cleaning of the deionized water is finished, drying the silicon carbide substrate by using high-purity argon;
etching the silicon carbide substrate in situ: placing the silicon carbide substrate subjected to ultrasonic cleaning into a deposition chamber of chemical vapor deposition equipment; vacuumizing the deposition chamber until the vacuum degree of the deposition chamber is 100 mbar; then, high-purity hydrogen is introduced into the deposition chamber, the flow rate of the high-purity hydrogen is 120L/min, and the vacuum degree of the deposition chamber is maintained at 100 mbar; raising the temperature of the deposition chamber to ensure that the temperature of the deposition chamber is stabilized at 1630 ℃ so as to carry out in-situ etching on the silicon carbide substrate, wherein the time of in-situ etching is 5min;
deposit firstEpitaxial layer: after the in-situ etching is finished, adjusting the hydrogen flow to 120L/min, reducing the temperature of the deposition chamber, and stabilizing the temperature of the deposition chamber to about 1590 ℃; introducing silane (silicon source), ethylene (carbon source) and high-purity nitrogen (n-type doping source) into a deposition chamber, wherein the flow rate of the silane is 320 sccm, the flow rate of the ethylene is 144 sccm, the flow rate of the high-purity nitrogen is 45 sccm, at the moment, the carbon-silicon ratio C/Si in the deposition chamber is 0.9, the silicon-hydrogen ratio Si/H is 0.0027, the vacuum degree is 100 mbar, the deposition rate of the first epitaxial layer is 60 mu m/H, until a first epitaxial layer with the thickness of 2 mu m is formed on the surface of the silicon carbide substrate, and the doping concentration of the first epitaxial layer is 1 multiplied by 10 17 atom/cm 2 ；
Depositing a first buffer layer: adjusting the flow rate of silane, ethylene and high-purity nitrogen gas, wherein the flow rate of silane is 70 sccm, the flow rate of ethylene is 21 sccm, the flow rate of high-purity nitrogen gas is 25 sccm, the carbon-silicon ratio C/Si in the deposition chamber is 0.6, the silicon-hydrogen ratio Si/H is 0.00058, the vacuum degree is 100 mbar, the deposition rate of the first buffer layer is 8 μm/H, until the surface of one side of the first epitaxial layer, which is far away from the silicon carbide substrate, forms a first buffer layer with the thickness of 0.8 μm, the doping concentration of the first buffer layer is 1×10 18 atom/cm 2 ；
Depositing a second epitaxial layer: the flow rates of silane, ethylene and high-purity nitrogen are adjusted, the flow rate of silane is 160, the flow rate of ethylene is 72 sccm, the flow rate of high-purity nitrogen is 38 sccm, at the moment, the carbon-silicon ratio C/Si in the deposition chamber is 0.9, the silicon-hydrogen ratio Si/H is 0.0013, the vacuum degree is 100 mbar, the deposition rate of the second epitaxial layer is 30 mu m/H, until a second epitaxial layer with the thickness of 10 mu m is formed on the surface of one side of the first epitaxial layer, which is far away from the silicon carbide substrate, and the doping concentration of the second epitaxial layer is 9 multiplied by 10 15 atom/cm 2 Obtaining the silicon carbide epitaxial wafer.
Example 2
The present embodiment provides a silicon carbide epitaxy method, which differs from the silicon carbide epitaxy method provided in embodiment 1 in that: the deposition rate of the first epitaxial layer in this example was 80 μm/h. Specifically, in the deposition process of the first epitaxial layer, the flow rate of silane is 426 sccm, the flow rate of ethylene is 192 sccm, and the deposition rate of the first epitaxial layer is controlled by regulating the flow rates of silane and ethylene.
Example 3
The present embodiment provides a silicon carbide epitaxy method, which differs from the silicon carbide epitaxy method provided in embodiment 1 in that: the deposition rate of the first epitaxial layer in this example was 70 μm/h. Specifically, in the deposition process of the first epitaxial layer, the flow rate of silane is 373 sccm, the flow rate of ethylene is 168 sccm, and the deposition rate of the first epitaxial layer is controlled by regulating and controlling the flow rates of silane and ethylene.
Example 4
The present embodiment provides a silicon carbide epitaxy method, which differs from the silicon carbide epitaxy method provided in embodiment 1 in that: the present embodiment extends the deposition time of the first epitaxial layer until the thickness of the first epitaxial layer is 4 μm.
Example 5
The present embodiment provides a silicon carbide epitaxy method, which differs from the silicon carbide epitaxy method provided in embodiment 1 in that: the present embodiment extends the deposition time of the first epitaxial layer until the thickness of the first epitaxial layer is 8 μm.
Example 6
The present embodiment provides a silicon carbide epitaxy method, which differs from the silicon carbide epitaxy method provided in embodiment 1 in that: in this embodiment, after the first epitaxial layer is deposited, a second buffer layer is first deposited on a surface of the first epitaxial layer on a side facing away from the silicon carbide substrate, and then the first buffer layer is formed on a surface of the second buffer layer on a side facing away from the silicon carbide substrate.
Specifically, the second buffer layer is deposited by the following steps: after the first epitaxial layer is deposited, the flow rates of silane, ethylene and high-purity nitrogen are regulated, the flow rate of silane is 18 sccm, the flow rate of ethylene is 5.4 sccm, the flow rate of high-purity nitrogen is 18 sccm, at the moment, the carbon-silicon ratio C/Si in the deposition chamber is 0.6, the silicon-hydrogen ratio Si/H is 0.00015, the vacuum degree is 100 mbar, the deposition rate of the second buffer layer is 2 mu m/H, until the surface of one side of the first epitaxial layer, which is far away from the silicon carbide substrate, forms a second buffer layer with the thickness of 0.2 mu m, and the doping concentration of the second buffer layer is 6 multiplied by 10 17 atom/cm 2 。
Example 7
The present embodiment provides a silicon carbide epitaxy method, which differs from the silicon carbide epitaxy method provided in embodiment 6 in that: the deposition rate of the second buffer layer was 1 μm/h. Specifically, in the deposition process of the second buffer layer, the flow rate of silane is 9 sccm, the flow rate of ethylene is 2.7 sccm, and the deposition rate of the second buffer layer is controlled by regulating the flow rates of silane and ethylene.
Example 8
The present embodiment provides a silicon carbide epitaxy method, which differs from the silicon carbide epitaxy method provided in embodiment 6 in that: the deposition rate of the second buffer layer was 3 μm/h. Specifically, in the deposition process of the second buffer layer, the flow rate of silane is 26 sccm, the flow rate of ethylene is 7.8 sccm, and the deposition rate of the second buffer layer is controlled by regulating the flow rates of silane and ethylene.
Example 9
The present embodiment provides a silicon carbide epitaxy method, which differs from the silicon carbide epitaxy method provided in embodiment 6 in that: the deposition rate of the first epitaxial layer in this example was 70 μm/h. Specifically, in the deposition process of the first epitaxial layer, the flow rate of silane is 373 sccm, the flow rate of ethylene is 168 sccm, and the deposition rate of the first epitaxial layer is controlled by regulating and controlling the flow rates of silane and ethylene.
Example 10
The present embodiment provides a silicon carbide epitaxy method, which differs from the silicon carbide epitaxy method provided in embodiment 6 in that: the deposition rate of the first epitaxial layer in this example was 80 μm/h. Specifically, in the deposition process of the first epitaxial layer, the flow rate of silane is 426 sccm, the flow rate of ethylene is 192 sccm, and the deposition rate of the first epitaxial layer is controlled by regulating the flow rates of silane and ethylene.
Example 11
The present embodiment provides a silicon carbide epitaxy method, which differs from the silicon carbide epitaxy method provided in embodiment 1 in that: the doping concentration of the first epitaxial layer in this embodiment is 9×10 15 atom/cm 2 。
Comparative example 1
This comparative example provides a silicon carbide epitaxy method which differs from the silicon carbide epitaxy method provided in example 1 in that: after the in-situ etching is finished, the first buffer layer is directly deposited, and then the second epitaxial layer is deposited, namely, the preparation of the first epitaxial layer is not carried out.
Comparative example 2
This comparative example provides a silicon carbide epitaxy method which differs from the silicon carbide epitaxy method provided in comparative example 1 in that: the deposition rate of the first epitaxial layer in this comparative example was 50 μm/h. Specifically, in the deposition process of the first epitaxial layer, the flow rate of silane is 267sccm, the flow rate of ethylene is 120 sccm, and the deposition rate of the first epitaxial layer is controlled by regulating the flow rates of silane and ethylene.
Comparative example 3
This comparative example provides a silicon carbide epitaxy method which differs from the silicon carbide epitaxy method provided in comparative example 1 in that: the deposition rate of the first epitaxial layer in this comparative example was 100 μm/h. Specifically, in the deposition process of the first epitaxial layer, the flow rate of silane is 533 sccm, the flow rate of ethylene is 240 sccm, and the deposition rate of the first epitaxial layer is controlled by regulating the flow rates of silane and ethylene.
Test examples
The silicon carbide epitaxial wafers prepared in examples 1 to 11 and comparative examples 1 to 3 were subjected to pit number detection by using a laser tec sica 81 defect inspection apparatus, and the test results are shown in table 1:
TABLE 1
As can be seen from the comparison of examples 1-3 and comparative examples 1-3, the first epitaxial layer deposited at the specific deposition rate according to the present application can effectively reduce pit defects on the surface of the silicon carbide epitaxial wafer, and control the number of other defects on the surface of the silicon carbide epitaxial wafer, thereby reducing the total number of defects on the surface of the silicon carbide epitaxial wafer;
as can be seen from the comparison between the embodiment 1 and the embodiment 11, the doping concentration of the first epitaxial layer is located between the doping concentration of the silicon carbide substrate and the doping concentration of the second epitaxial layer, so that the number of other defects on the surface of the second epitaxial layer can be further reduced, and the quality of the silicon carbide epitaxial wafer is further improved.
From the comparison of examples 1 to 3 with comparative examples 2 to 3, and the comparison of examples 6, 9, and 10, it is understood that as the deposition rate of the first epitaxial layer increases, pit defects gradually decrease and the number of other defects gradually increases.
From the comparison of examples 1, 6-8, the comparison of example 2 and example 10, and the comparison of example 9 and example 3, it is evident that the deposition of the second buffer layer can further reduce the number of other defects on the surface of the second epitaxial layer, thereby further improving the quality of the silicon carbide epitaxial wafer.
As can be seen from a comparison of examples 6 to 8, as the deposition rate of the second buffer layer decreases, pit defects gradually increase and the number of other defects gradually decrease.
In the description of the present specification, a description referring to the terms "one embodiment," "some embodiments," "examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
Claims (10)
1. A method of silicon carbide epitaxy, comprising:
providing a silicon carbide substrate;
performing in-situ etching on the silicon carbide substrate;
after in-situ etching is carried out on the silicon carbide substrate, a first epitaxial layer is deposited on one side surface of the silicon carbide substrate, and the deposition rate of the first epitaxial layer is 60-80 mu m/h;
depositing a first buffer layer on one side of the first epitaxial layer away from the silicon carbide substrate;
and depositing a second epitaxial layer on the surface of one side of the first buffer layer, which is away from the silicon carbide substrate.
2. The method of claim 1, wherein during the deposition of the first epitaxial layer, the reaction gas to the deposition chamber comprises a carbon source and a silicon source, the carbon to silicon ratio of the deposition chamber is 0.8-0.9, and the flow rate of the silicon source is 300 sccm-426 sccm.
3. The silicon carbide epitaxy method according to claim 1 or 2, characterized in that the thickness of the first epitaxial layer is 2 μm to 8 μm.
4. The silicon carbide epitaxial method of claim 1, wherein the doping concentration of the first epitaxial layer is less than the doping concentration of the silicon carbide substrate and greater than the doping concentration of the second epitaxial layer, the doping types of the first epitaxial layer, the silicon carbide substrate, and the second epitaxial layer being the same.
5. The method of claim 4, wherein the first epitaxial layer has a doping concentration of 1 x 10 15 atom/cm 2 ~1×10 17 atom/cm 2 The doping concentration of the silicon carbide substrate is 1 multiplied by 10 18 atom/cm 2 ～3×10 18 atom/cm 2 The doping concentration of the second epitaxial layer is 5×10 15 atom/cm 2 ~1×10 16 atom/cm 2 。
6. The silicon carbide epitaxy method of claim 1, further comprising:
before depositing the first buffer layer on the side, away from the silicon carbide substrate, of the first epitaxial layer, growing a second buffer layer on the surface of the side, away from the silicon carbide substrate, of the first epitaxial layer by adopting a chemical vapor deposition process; after the first buffer layer is deposited on one side, away from the silicon carbide substrate, of the first epitaxial layer, the second buffer layer is positioned between the first buffer layer and the first epitaxial layer, and the deposition rate of the second buffer layer is 1-3 mu m/h.
7. The method of claim 6, wherein during the deposition of the second buffer layer, the reaction gas to the deposition chamber comprises a carbon source and a silicon source, the carbon-silicon ratio of the deposition chamber is 0.6-0.65, and the flow rate of the silicon source is 8 sccm-27 sccm.
8. The silicon carbide epitaxy method of claim 6, wherein a thickness of the second buffer layer is 0.1 μm to 0.3 μm.
9. The silicon carbide epitaxial method of claim 1, wherein the deposition rate of the first buffer layer is 7-11 μm/h and the deposition rate of the second epitaxial layer is 20-40 μm/h.
10. A silicon carbide epitaxy method according to claim 1, characterised in that the silicon carbide substrate is an off-axis silicon carbide substrate.
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