CN114775046A - Silicon carbide epitaxial layer growth method - Google Patents

Silicon carbide epitaxial layer growth method Download PDF

Info

Publication number
CN114775046A
CN114775046A CN202210710329.1A CN202210710329A CN114775046A CN 114775046 A CN114775046 A CN 114775046A CN 202210710329 A CN202210710329 A CN 202210710329A CN 114775046 A CN114775046 A CN 114775046A
Authority
CN
China
Prior art keywords
buffer layer
silicon carbide
silicon
carbon source
epitaxial layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202210710329.1A
Other languages
Chinese (zh)
Other versions
CN114775046B (en
Inventor
王蓉
李佳君
皮孝东
李东珂
刘小平
杨德仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hangzhou Jingchi Electromechanical Technology Co ltd
Original Assignee
ZJU Hangzhou Global Scientific and Technological Innovation Center
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ZJU Hangzhou Global Scientific and Technological Innovation Center filed Critical ZJU Hangzhou Global Scientific and Technological Innovation Center
Priority to CN202210710329.1A priority Critical patent/CN114775046B/en
Publication of CN114775046A publication Critical patent/CN114775046A/en
Application granted granted Critical
Publication of CN114775046B publication Critical patent/CN114775046B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
    • C30B25/18Epitaxial-layer growth characterised by the substrate
    • C30B25/183Epitaxial-layer growth characterised by the substrate being provided with a buffer layer, e.g. a lattice matching layer
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10Inorganic compounds or compositions
    • C30B29/36Carbides

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

The invention relates to the technical field of silicon carbide crystal growth, and discloses a silicon carbide epitaxial layer growth method.

Description

Silicon carbide epitaxial layer growth method
Technical Field
The invention relates to the technical field of growth of a silicon carbide epitaxial layer, in particular to a method for growing the silicon carbide epitaxial layer.
Background
The silicon carbide has excellent performance and has great application value in high-voltage and high-power application scenes. However, both device performance and yield are affected by the presence of dislocations.
In the state of the art, the majority of basal plane dislocations of the silicon carbide substrate are converted to threading dislocations during the epitaxial formation of the silicon carbide epitaxial layer on the surface of the silicon carbide substrate, but the threading dislocations extend substantially entirely into the epitaxial layer. Therefore, the dislocation density of the epitaxial layer obtained by the conventional epitaxial process cannot be reduced, and the method becomes one of the key technical problems for limiting the performance optimization and the cost control of the silicon carbide device.
Disclosure of Invention
The invention aims to solve the problem of high dislocation density of an epitaxial layer obtained by a conventional epitaxial process, and provides a silicon carbide epitaxial layer growth method.
In order to achieve the above object, the present invention provides a method for growing a silicon carbide epitaxial layer, comprising the steps of:
providing a silicon carbide substrate, placing the silicon carbide substrate in an epitaxial furnace, introducing carrier gas, heating, setting pressure, introducing a carbon source with a first preset carbon source flow and a silicon source with a first preset silicon source flow, introducing doping gas, and growing a first buffer layer on the surface of the silicon carbide wafer; wherein the ratio of carbon to silicon in the first predetermined carbon source flow and the first predetermined silicon source flow ranges from 1: 1-3: 2, the flow range of the first predetermined carbon source is 10 sccm-20 sccm; the carbon source with the first preset carbon source flow and the silicon source with the first preset silicon source flow enable the growth speed of the first buffer layer to be slow, and the threading dislocation continued from the silicon carbide substrate slice is converted into the layer dislocation and the basal plane dislocation in the process of growing the first buffer layer, so that the dislocation is promoted to move transversely and move out of the surface of the first buffer layer;
stopping introducing the carbon source, the silicon source and the doping gas, introducing etching gas, etching the surface of the first buffer layer, removing carbon impurities on the surface of the first buffer layer, and preventing the carbon impurities from becoming dislocation sources;
and continuously introducing the carbon source and the silicon source with corresponding flow rates, introducing doping gas, and growing on the surface of the first buffer layer after impurities are removed to obtain the epitaxial layer with corresponding concentration parameters.
As an implementable manner, the step of continuously introducing the carbon source and the silicon source with corresponding flow rates, introducing the doping gas, and growing on the surface of the first buffer layer after the impurities are removed to obtain the epitaxial layer with the corresponding concentration parameters specifically comprises;
continuously introducing a carbon source with a second preset carbon source flow rate and a silicon source with a second preset silicon source flow rate, introducing doping gas, and forming a second buffer layer on the surface of the first buffer layer, wherein the carbon source with the second preset carbon source flow rate and the silicon source with the second preset silicon source flow rate enable the growth speed of the second buffer layer to be fast, and in the process of growing the second buffer layer, residual basal plane dislocations which are continued from the first buffer layer are converted into threading dislocations, so that the dislocations are promoted to move longitudinally, and the dislocations which extend from the second buffer layer to a subsequently formed epitaxial layer are threading dislocations;
and then continuously introducing the carbon source and the silicon source with corresponding flow rates, introducing doping gas, and growing on the surface of the second buffer layer after the impurities are removed to obtain the epitaxial layer with corresponding concentration parameters.
As an embodiment, the second predetermined carbon source flow rate ranges from: 60-100 sccm, and the ratio of the second predetermined carbon source flow to the carbon-silicon in the second predetermined silicon source flow is in a range of 4: 5-1: 1.
in one embodiment, the pressure is set to be 30 to 80 Torr when the first buffer layer is grown on the surface of the silicon carbide substrate slice; setting the pressure range to be 80-120 Torr when growing a second buffer layer on the surface of the first buffer layer; and setting the pressure range to be 80-120 Torr when the epitaxial layer grows on the surface of the second buffer layer.
As an implementation manner, the doping gas introduced during the growth of the first buffer layer has a first predetermined flow rate, and the doping gas with the first predetermined flow rate enables the first buffer layer to be formed to have a corresponding first predetermined doping concentration, and the first predetermined doping concentration is consistent with the doping concentration of the silicon carbide substrate sheet and is used for preventing interface dislocation between the silicon carbide substrate sheet and the first buffer layer caused by a large difference of the doping concentrations;
the doping gas introduced during the growth of the second buffer layer has a second preset flow rate, and the doping gas with the second preset flow rate enables the formed second buffer layer to have a corresponding second preset doping concentration, wherein the second preset doping concentration is smaller than the first preset doping concentration but larger than the doping concentration of the subsequently formed epitaxial layer, and is used for performing intermediate transition on the doping concentration of the first buffer layer and the doping concentration of the subsequently formed epitaxial layer, so that new defects caused by lattice distortion due to large difference of the doping concentrations are prevented.
In one embodiment, the first buffer layer has a thickness ranging from 0.5 to 2.0 micrometers, and the second buffer layer has a thickness ranging from 0.5 to 2.0 micrometers.
As an embodiment, the threading dislocations include threading dislocations TSD and edge dislocations TED.
As one possible implementation mode, the silicon carbide substrate sheet is an N-type silicon carbide wafer, and the doping concentration range of the silicon carbide substrate sheet is 1018~1019 cm-3The total dislocation density of the silicon carbide substrate piece is 103~104 cm-3
As one possible embodiment, the doping gas includes a nitrogen-containing gas including nitrogen; the carrier gas is hydrogen; the etching gas is hydrogen.
As an embodiment, the silicon source is one or both of silane and trichlorosilane; the carbon source is one or more of methane, ethylene and propylene.
The invention has the beneficial effects that: the invention provides a silicon carbide epitaxial layer growth method, which comprises the steps of generating a first buffer layer on the surface of a silicon carbide substrate sheet by introducing a carbon source with a first preset carbon source flow rate and a silicon source with a first preset silicon source flow rate, so that through adjustment of the carbon-silicon flow rate ratio and the specific introduced carbon source flow rate, threading dislocations extending from the silicon carbide substrate sheet are promoted to be converted into faults and basal plane dislocations in the growth process of the first buffer layer, and the transverse movement is carried out to remove the first buffer layer of a crystal, thereby reducing the number of the dislocations entering an epitaxial layer from the first buffer layer; and a second buffer layer is generated on the surface of the first buffer layer by introducing a carbon source with a first preset carbon source flow and a silicon source with a first preset silicon source flow, so that the basal plane dislocation extending from the silicon carbide substrate is converted into the threading dislocation in the growth process of the first buffer layer by adjusting the carbon-silicon flow ratio and the specific introduced carbon source flow, the dislocation density of the basal plane dislocation is reduced, the influence of the basal plane dislocation on the epitaxial layer is further reduced, the purpose of reducing the dislocation density in the silicon carbide epitaxial layer is finally realized, and the device performance is improved.
Drawings
FIG. 1 is a flow chart of steps of a method for growing a silicon carbide epitaxial layer according to an embodiment of the present invention;
FIG. 2 is a schematic illustration of dislocations in different layers in a silicon carbide epitaxial layer growth process according to an embodiment of the present invention;
fig. 3 is a schematic view showing the process of eliminating dislocation convergence in the method for growing a silicon carbide epitaxial layer according to the embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
Referring to fig. 1, the present embodiment provides a technical solution: a method of growing a silicon carbide epitaxial layer, comprising the steps of:
step S100, providing a silicon carbide substrate slice, placing the silicon carbide substrate slice into an epitaxial furnace, introducing carrier gas, heating, setting pressure, introducing a carbon source with a first preset carbon source flow and a silicon source with a first preset silicon source flow, introducing doping gas, and growing a first buffer layer on the surface of the silicon carbide wafer; wherein the ratio of the first predetermined carbon source flow to the carbon-silicon in the first predetermined silicon source flow is in a range of 1: 1-3: 2, the flow range of the first predetermined carbon source is 10 sccm-20 sccm; the carbon source with the first preset carbon source flow and the silicon source with the first preset silicon source flow enable the growth speed of the first buffer layer to be slow, and the threading dislocation continued from the silicon carbide substrate slice is converted into the layer dislocation and the basal plane dislocation in the process of growing the first buffer layer, so that the dislocation is promoted to move transversely and move out of the surface of the first buffer layer;
step S200, stopping introducing the carbon source, the silicon source and the doping gas, introducing etching gas, etching the surface of the first buffer layer, removing carbon impurities on the surface of the first buffer layer, and preventing the carbon impurities from becoming dislocation sources;
and step S300, continuing to introduce carbon sources and silicon sources with corresponding flow rates, introducing doping gas, and growing on the surface of the first buffer layer after impurities are removed to obtain the epitaxial layer with corresponding concentration parameters.
Step S100 and step S200 are executed, in this embodiment, the silicon carbide substrate slice is an N-type silicon carbide wafer, and the doping concentration range of the silicon carbide substrate slice is 1018~1019 cm-3The total dislocation density of the silicon carbide substrate piece is 103~104 cm-3In other embodiments, however, a different silicon carbide substrate piece may actually be selected.
The dopant gas includes nitrogen-containing gas and the like, and the nitrogen-containing gas includes nitrogen and the like; the carrier gas is high-purity hydrogen; the etching gas is hydrogen; the silicon source can be one or two of silane and trichlorosilane, or other specific materials which can be used as the silicon source; the carbon source is one or more of methane, ethylene, propylene and propylene, or other specific materials which can be used as the carbon source.
In this embodiment, the range of the first predetermined carbon source flow rate is: 10 sccm-20 sccm, and the ratio of the carbon to the silicon in the first predetermined carbon source flow and the first predetermined silicon source flow ranges from 3: 1-1: 2; the first preset silicon source flow of the introduced silicon source is adjusted through the fused first preset carbon source flow and the carbon-silicon ratio; specifically, in the present embodiment, the speed of growing the first buffer layer is slowed by introducing a lower carbon source flow; in the embodiment, the high carbon-silicon flow ratio is set, that is, the carbon-silicon ratio of the first predetermined carbon source flow to the first predetermined silicon source flow is increased, that is, the carbon ratio is greater than the silicon ratio, so that the carbon occupancy of the generated first buffer layer is increased, that is, the threading dislocations continuing from the silicon carbide substrate sheet can be converted into the faults and the basal plane dislocations during the growth of the first buffer layer, and the lateral movement of the faults and dislocations is promoted under the slow growth of the first buffer layer, so that the faults and dislocations can move out of the crystal under the lateral movement, and cannot rise into the epitaxial layer on the surface of the first buffer layer again without rising to the surface of the first buffer layer, thereby reducing the dislocation density in the epitaxial layer. Wherein, the stacking fault and the basal plane dislocation are grown transversely according to the growth direction of the step flow, and the threading dislocation is the dislocation which can grow longitudinally; the threading dislocations include threading dislocations TSD and edge dislocations TED.
Specifically, the speed of growing the first buffer layer is slowed, that is, the process of growing the first buffer layer is a low-speed step flow growth mode, in the growth mode, the size of the grown step is increased, so that the threading dislocation continued from the silicon carbide substrate sheet is promoted to move transversely in the process of growing the first buffer layer, and is converted into a transversely moving lamination fault and a basal plane dislocation, the transverse movement of the dislocation on the surface of the step is strengthened, so that part of the initial threading dislocation is promoted to move to the side surface of the crystal, and the other part of the initial threading dislocation is decomposed to form the lamination fault, so that the threading dislocation directly moves at an increased speed in the transverse growth direction of the lamination fault, and the threading dislocation can be promoted to escape from the crystal; and basal plane dislocations continued from the silicon carbide substrate slice can further move transversely along with the slow growth, so that the basal plane dislocations are moved out of the surface of the first buffer layer and do not extend to the surface of the first buffer layer.
Meanwhile, partial dislocations with opposite Bernoulli vectors can be converged and disappear, for example: the threading dislocation TSD is a screw dislocation, a left-handed threading dislocation TSD and a right-handed threading dislocation TSD are collided together and offset so as to be converged and disappear, the edge dislocation TED is a half-layer atom, and an edge dislocation TED of a left half-layer and an edge dislocation TED of a right half-layer are collided together and converged and disappear; as shown in fig. 3, in the figure, a solid black line represents the movement of dislocation lines on the surface of the first buffer layer, arrows represent the direction of the bernoulli vectors, black dots represent vertical surfaces, hollow dots represent convergence positions, as the epitaxial thickness of the first buffer layer increases, a part of the threading dislocations extend to the side surfaces of the crystal and escape, a part of the threading dislocations opposite to the bernoulli vectors approach each other and finally converge to disappear, a part of the threading dislocations do not escape or converge, and the dislocation lines as residuals may also move laterally in the first buffer layer along the step flow direction without moving out of the first buffer layer.
In the embodiment, the heating temperature in the process is 1500-1700 ℃; the pressure in the whole process can be set to be constant, but if the growth speed of the first buffer layer is further reduced; the pressure when the first buffer layer grows on the surface of the silicon carbide substrate piece can be set to be low pressure in the range of 30-80 Torr.
It should be noted that, because the ratio of the carbon source flow is high during the growth of the first buffer layer, carbon impurities may be generated on the surface of the first buffer layer, and if an epitaxial layer is grown on the surface of the first buffer layer without being removed, the carbon impurities may become dislocation sources of the epitaxial layer, and a new dislocation line is formed in the epitaxial layer, so that in order to reduce the influence of the impurities, the embodiment of the present invention further reduces the influence of dislocations on the epitaxial layer by etching the surface of the first buffer layer. Meanwhile, because the thickness of the first buffer layer is smaller, carbon impurities are mainly formed on the surface of the first buffer layer and are not formed inside the first buffer layer, so that the carbon impurities on the surface of the first buffer layer are removed through an etching process, and dislocation sources of the epitaxial layer can be effectively reduced.
Step 300 is executed, the carbon source with the corresponding flow rate and the silicon source with the corresponding flow rate are introduced to perform epitaxial layer growth, the epitaxial layer with the target concentration parameter required to be obtained according to actual needs is determined, the growth thickness of the epitaxial layer is also directly determined according to the target thickness of the epitaxial layer required in actual needs, the embodiment is not limited, for example, the carbon source flow rate can be 40 sccm to 80sccm, the carbon-silicon ratio in the carbon source flow rate and the silicon source flow rate can be set to be 0.8 to 1, and the silicon source flow rate is adjusted through the carbon source flow rate and the carbon-silicon ratio.
In this embodiment, in order to further reduce the influence of the dislocation remaining on the surface of the first buffer layer on the epitaxial layer, in this embodiment, the carbon source and the silicon source with corresponding flow rates are continuously introduced, the doping gas is introduced, and the step of growing the epitaxial layer with the corresponding concentration parameter on the surface of the first buffer layer after the impurity removal specifically includes;
continuously introducing a carbon source with a second preset carbon source flow rate and a silicon source with a second preset silicon source flow rate, introducing doping gas, and forming a second buffer layer on the surface of the first buffer layer, wherein the carbon source with the second preset carbon source flow rate and the silicon source with the second preset silicon source flow rate enable the growth speed of the second buffer layer to be fast, and in the process of growing the second buffer layer, residual basal plane dislocations which are continued from the first buffer layer are converted into threading dislocations, so that the dislocations are promoted to move longitudinally, and the dislocations which extend from the second buffer layer to a subsequently formed epitaxial layer are threading dislocations;
and continuously introducing the carbon source and the silicon source with corresponding flow rates, introducing doping gas, and growing on the surface of the second buffer layer after impurities are removed to obtain the epitaxial layer with corresponding concentration parameters.
It should be noted that, in this embodiment, after the second buffer layer is generated, the surface of the second buffer layer is not etched, because the ratio of the first predetermined carbon source flow introduced into the second buffer layer to the carbon-silicon ratio in the first predetermined silicon source flow is not higher than that of the medium carbon source, carbon impurities are not formed on the surface of the second buffer layer, and an epitaxial layer may be directly grown without performing additional etching.
In this embodiment, the range of the second predetermined carbon source flow rate is: 60-100 sccm, and the ratio of the second predetermined carbon source flow to the carbon-silicon in the second predetermined silicon source flow is in a range of 4: 5-1: 1; the flow rate of the introduced second predetermined silicon source is adjusted through the flow rate of the second predetermined carbon source of the introduced carbon source and the carbon-silicon ratio; specifically, in this embodiment, a higher carbon source flow is introduced, so that the growth speed of the second buffer layer is increased, and in addition, a low carbon source flow ratio is set, that is, the carbon content ratio of the second buffer layer is reduced compared to the carbon content ratio of the first buffer layer, so that residual basal plane dislocations continuing from the surface of the first buffer layer are converted into threading dislocations in the second buffer layer during the growth of the first buffer layer, so that the threading dislocations are accelerated to move longitudinally on the premise that the growth speed of the second buffer layer is increased, and finally the dislocations moving into the epitaxial layer are made to be threading dislocations, thereby reducing the influence of the basal plane dislocations on the epitaxial layer.
The purpose of converting residual basal plane dislocations extending from the first buffer layer into threading dislocations in the process of growing the second buffer layer, so that the dislocations extending from the second buffer layer into the epitaxial layer formed subsequently are threading dislocations, is that in the process of growing the first buffer layer, because some dislocations may exist or cannot move out, and the threading dislocations have smaller influence on the quality of the epitaxial layer than the basal plane dislocations, the influence of the dislocations on the epitaxial layer is further reduced, and the influence of the dislocations is reduced as a whole, so that the basal plane dislocations extending from the first buffer layer are converted into the threading dislocations again by arranging the second buffer layer; in other embodiments, however, the second buffer layer may be further configured to promote lateral movement of the basal plane dislocations, thereby promoting movement of the dislocations away from the surface of the second buffer layer, further reducing the number and density of dislocations in the epitaxial layer.
As shown in fig. 2, a first buffer layer 20 is grown on the surface of the silicon carbide substrate piece 10, a second buffer layer 30 is grown on the surface of the first buffer layer 20, an epitaxial layer 40 is grown on the surface of the second buffer layer, wherein the solid lines shown in the figure can be regarded as dislocation lines, and the direction shown by the arrow is the step flow direction, it can be seen that a plurality of dislocation lines exist in the silicon carbide substrate piece 10, and the dislocation lines directly extend into the generated first buffer layer 20, and since the embodiment makes the growth speed of the first buffer layer 20 slow by adjusting the proportion of the carbon-silicon flow introduced and the specific carbon source flow introduced during the growth of the first buffer layer 20, the threading dislocation type in the silicon carbide substrate piece 10 is converted into the basal plane dislocation moving transversely in the first buffer layer 20, and the part of the dislocation lines extends out of the right side of the first buffer layer 20 along with the growth of the first buffer layer 20, finally, the number of dislocation lines extending to the surface of the first buffer layer 20 is reduced, and the second buffer layer 30 on the surface of the first buffer layer 20, it can be seen that, in the present embodiment, the basal plane dislocations extending from the surface of the first buffer layer are converted into threading dislocations in the second buffer layer 30 by adjusting the ratio of the flow rate of carbon to silicon introduced and the flow rate of the carbon source specifically introduced during the growth of the second buffer layer 30.
Furthermore, the pressure range when the second buffer layer grows on the surface of the first buffer layer can be set to be 80-120 Torr, so that the speed of growing the second buffer layer is further improved; the pressure range when the epitaxial layer grows on the surface of the second buffer layer can be set to be 80-120 Torr, and the pressure range is used for improving the speed of growing the epitaxial layer.
Further, the doping gas introduced during the growth of the first buffer layer has a first predetermined flow rate, and the doping gas with the first predetermined flow rate enables the first buffer layer to be formed to have a corresponding first predetermined doping concentration, and the first predetermined doping concentration is consistent with the doping concentration of the silicon carbide substrate slice, so that interface dislocation caused by a large difference of the doping concentrations between the silicon carbide substrate slice and the first buffer layer is prevented;
the doping gas with the second preset flow rate is introduced when the second buffer layer grows, so that the formed second buffer layer has corresponding second preset doping concentration, wherein the second preset doping concentration is smaller than the first preset doping concentration but larger than the doping concentration of the subsequently formed epitaxial layer, and the doping concentration of the first buffer layer and the doping concentration of the subsequently formed epitaxial layer are subjected to intermediate transition, so that the generation of new defects caused by lattice distortion due to large difference of the doping concentrations is prevented.
For example: when the doping concentration range of the silicon carbide substrate slice is 1018~1019 cm-3And the doping concentration of the epitaxial layer to be grown is 1015cm-3In this case, the doping concentration of the first buffer layer may be adjusted to 10 by adjusting the flow rate of the doping gas18 cm-3So that the doping concentration of the second buffer layer is reduced to 1016 cm-3So that the first buffer layer and the second buffer layer can play corresponding roles.
Specifically, as an example, first, a silicon carbide substrate sheet is provided, and the silicon carbide substrate sheet is cleaned, wherein, as the silicon carbide substrate sheet, a 4 ° obliquely cut N-type silicon carbide wafer with a doping concentration of 10 may be selected18~1019 cm-3 Total dislocation density 103~104 cm-3Cleaning based on standard RCA; after cleaning, sending the silicon carbide substrate into an epitaxial furnace, introducing high-purity hydrogen, and raising the temperature to 1600 ℃; adjusting the pressure of the reaction chamber to 40 Torr, adding trichlorosilane as a silicon source and propylene as a carbon source, wherein the flow of the propylene is 20 sccm, and adjusting the flow of the trichlorosilane to ensure that the flow ratio of the carbon to the silicon is 1: 2, obtaining a low-speed step flow growth mode, adjusting the flow of high-purity nitrogen to ensure that the doping concentration is 1018cm-3(ii) a Obtaining a first buffer layer with the thickness of 1.0 micrometer; in this mode, the epitaxial step size is increased, the lateral movement of the threading dislocation on the step surface is strengthened, and a part of the threading dislocation is promoted to move to the side surface of the crystal, and another part of the threading dislocation is decomposed into a layer dislocation, so that the lateral growth speed is increased, and the threading dislocation can be promoted to escape from the crystal. Meanwhile, the dislocations with opposite Bernoulli vectors are close to each other, and finally converge and disappear. The high doping concentration can reduce lattice mismatch between the epitaxial layer and the substrate and avoid new crystal defectsGeneration of interfacial dislocations.
Adjusting the pressure of the reaction chamber to be 100 Torr, the flow of the propylene to be 60sccm, and adjusting the flow of the trichlorosilane to ensure that the carbon-silicon ratio is 1: 2, adjusting the flow rate of high-purity nitrogen gas to make the doping concentration of the second buffer layer 105-106 cm-3And growing to a thickness of 1.0 micrometer to obtain the buffer layer B, wherein the growth environment promotes the transition from basal plane dislocation to threading dislocation.
The pressure was maintained at 100 Torr, the flow rate of propylene was maintained at 60sccm, the flow rate of trichlorosilane was adjusted to reduce the carbon-silicon ratio to 0.9, and an epitaxial layer having a target thickness was grown to obtain an epitaxial thin film having a low dislocation density.
The invention provides a silicon carbide epitaxial layer growth method, which comprises the steps of generating a first buffer layer on the surface of a silicon carbide substrate by introducing a carbon source with a first preset carbon source flow rate and a silicon source with a first preset silicon source flow rate, so that through adjustment of the carbon-silicon flow rate ratio and the specific introduced carbon source flow rate, threading dislocations extending out of the silicon carbide substrate are promoted to be converted into basal plane dislocations in the growth process of the first buffer layer, and the first buffer layer of a crystal is moved transversely and removed, so that the number of dislocations entering an epitaxial layer from the first buffer layer is reduced; and a second buffer layer is generated on the surface of the first buffer layer by introducing a carbon source with a first preset carbon source flow and a silicon source with a first preset silicon source flow, so that the basal plane dislocation extending from the silicon carbide substrate is converted into the threading dislocation in the growth process of the first buffer layer by adjusting the carbon-silicon flow ratio and the specific introduced carbon source flow, the dislocation density of the basal plane dislocation is reduced, the influence of the basal plane dislocation on the epitaxial layer is further reduced, the purpose of reducing the dislocation density in the silicon carbide epitaxial layer is finally realized, and the device performance is improved.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.

Claims (10)

1. A method for growing a silicon carbide epitaxial layer is characterized by comprising the following steps:
providing a silicon carbide substrate slice, placing the silicon carbide substrate slice into an epitaxial furnace, introducing carrier gas, heating, setting pressure, introducing a carbon source with a first preset carbon source flow and a silicon source with a first preset silicon source flow, introducing doping gas, and growing a first buffer layer on the surface of the silicon carbide wafer; wherein the ratio of the first predetermined carbon source flow to the carbon-silicon in the first predetermined silicon source flow is in a range of 1: 1-3: 2, the flow range of the first predetermined carbon source is 10 sccm-20 sccm; the carbon source with the first preset carbon source flow and the silicon source with the first preset silicon source flow enable the growth speed of the first buffer layer to be slow, and the threading dislocation continued from the silicon carbide substrate slice is converted into the layer dislocation and the basal plane dislocation in the process of growing the first buffer layer, so that the dislocation is promoted to move transversely and move out of the surface of the first buffer layer;
stopping introducing the carbon source, the silicon source and the doping gas, introducing etching gas, etching the surface of the first buffer layer, removing carbon impurities on the surface of the first buffer layer, and preventing the carbon impurities from becoming dislocation sources;
and then continuously introducing the carbon source and the silicon source with corresponding flow rates, introducing doping gas, and growing on the surface of the first buffer layer after the impurities are removed to obtain the epitaxial layer with corresponding concentration parameters.
2. The method for growing the silicon carbide epitaxial layer according to claim 1, wherein the step of continuing to introduce the carbon source and the silicon source at corresponding flow rates and introducing the doping gas to grow the epitaxial layer with the corresponding concentration parameter on the surface of the first buffer layer after the impurities are removed specifically comprises;
continuously introducing a carbon source with a second preset carbon source flow rate and a silicon source with a second preset silicon source flow rate, introducing doping gas, and forming a second buffer layer on the surface of the first buffer layer, wherein the carbon source with the second preset carbon source flow rate and the silicon source with the second preset silicon source flow rate enable the growth speed of the second buffer layer to be fast, and in the process of growing the second buffer layer, residual basal plane dislocations which are continued from the first buffer layer are converted into threading dislocations, so that the dislocations are promoted to move longitudinally, and the dislocations which extend from the second buffer layer to a subsequently formed epitaxial layer are threading dislocations;
and then continuously introducing the carbon source and the silicon source with corresponding flow rates, introducing doping gas, and growing on the surface of the second buffer layer after the impurities are removed to obtain the epitaxial layer with corresponding concentration parameters.
3. The method for growing a silicon carbide epitaxial layer according to claim 2, wherein the second predetermined carbon source flow rate ranges from 60sccm to 100sccm, and the ratio of the second predetermined carbon source flow rate to the carbon to silicon in the second predetermined silicon source flow rate ranges from 4: 5-1: 1.
4. the method for growing the silicon carbide epitaxial layer according to claim 2, wherein the pressure is set to be in a range of 30 to 80 Torr when the first buffer layer is grown on the surface of the silicon carbide substrate wafer; setting the pressure range to be 80-120 Torr when growing a second buffer layer on the surface of the first buffer layer; and setting the pressure range to be 80-120 Torr when the epitaxial layer grows on the surface of the second buffer layer.
5. The method for growing the silicon carbide epitaxial layer according to claim 2, wherein the doping gas is introduced during the growth of the first buffer layer at a first predetermined flow rate, and the doping gas at the first predetermined flow rate causes the first buffer layer to be formed with a corresponding first predetermined doping concentration, which is consistent with the doping concentration of the silicon carbide substrate sheet, so as to prevent interface dislocation between the silicon carbide substrate sheet and the first buffer layer due to a large difference in doping concentration;
the doping gas with the second preset flow rate is introduced when the second buffer layer grows, so that the formed second buffer layer has corresponding second preset doping concentration, wherein the second preset doping concentration is smaller than the first preset doping concentration but larger than the doping concentration of the subsequently formed epitaxial layer, and the doping concentration of the first buffer layer and the doping concentration of the subsequently formed epitaxial layer are subjected to intermediate transition, so that the generation of new defects caused by lattice distortion due to large difference of the doping concentrations is prevented.
6. The method for growing the silicon carbide epitaxial layer according to claim 2, wherein the first buffer layer has a thickness in a range of 0.5 to 2.0 μm, and the second buffer layer has a thickness in a range of 0.5 to 2.0 μm.
7. The silicon carbide epitaxial layer growth method of claim 1, wherein the threading dislocations comprise threading dislocations TSD and edge dislocations TED.
8. The method of claim 1, wherein the silicon carbide substrate wafer is an N-type silicon carbide wafer and the silicon carbide substrate wafer has a doping concentration in the range of 1018~1019 cm-3The total dislocation density of the silicon carbide substrate piece is 103~104 cm-3
9. The method of growing a silicon carbide epitaxial layer according to claim 1, wherein the dopant gas comprises a nitrogen-containing gas comprising nitrogen; the carrier gas is hydrogen; the etching gas is hydrogen.
10. The method for growing a silicon carbide epitaxial layer according to claim 1, wherein the silicon source is one or both of silane and trichlorosilane; the carbon source is one or more of methane, ethylene and propylene.
CN202210710329.1A 2022-06-22 2022-06-22 Silicon carbide epitaxial layer growth method Active CN114775046B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210710329.1A CN114775046B (en) 2022-06-22 2022-06-22 Silicon carbide epitaxial layer growth method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210710329.1A CN114775046B (en) 2022-06-22 2022-06-22 Silicon carbide epitaxial layer growth method

Publications (2)

Publication Number Publication Date
CN114775046A true CN114775046A (en) 2022-07-22
CN114775046B CN114775046B (en) 2022-11-29

Family

ID=82422437

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210710329.1A Active CN114775046B (en) 2022-06-22 2022-06-22 Silicon carbide epitaxial layer growth method

Country Status (1)

Country Link
CN (1) CN114775046B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116259534A (en) * 2023-05-12 2023-06-13 比亚迪股份有限公司 Silicon carbide epitaxy method

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007269627A (en) * 2002-03-19 2007-10-18 Central Res Inst Of Electric Power Ind METHOD FOR MANUFACTURING SIC CRYSTAL TO REDUCE MICROPIPE PROPAGATING FROM SUBSTRATE AND SiC CRYSTAL, SiC SINGLE CRYSTAL FILM, SiC SEMICONDUCTOR ELEMENT, SiC SINGLE CRYSTAL SUBSTRATE AND ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING SiC BULK CRYSTAL
US20100119849A1 (en) * 2007-07-26 2010-05-13 Nobuhiko Nakamura Sic epitaxial substrate and method for producing the same
US20110045281A1 (en) * 2009-08-20 2011-02-24 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Reduction of basal plane dislocations in epitaxial sic
JP2015002207A (en) * 2013-06-13 2015-01-05 昭和電工株式会社 SiC EPITAXIAL WAFER AND MANUFACTURING METHOD THEREOF
US20150128850A1 (en) * 2011-11-23 2015-05-14 University Of South Carolina Pretreatment Method for Reduction and/or Elimination of Basal Plane Dislocations Close to Epilayer/Substrate Interface in Growth of SiC Epitaxial Films
CN107068539A (en) * 2016-12-15 2017-08-18 中国电子科技集团公司第五十五研究所 The method for reducing silicon carbide epitaxy base plane dislocation density
CN108166056A (en) * 2018-01-16 2018-06-15 李哲洋 A kind of growing method that can effectively reduce silicon carbide epitaxy surface defect
CN111681947A (en) * 2020-05-22 2020-09-18 东莞市天域半导体科技有限公司 Epitaxial method for reducing stacking fault defects of epitaxial wafer and application thereof
CN112670165A (en) * 2020-12-24 2021-04-16 南京百识电子科技有限公司 Growth method of silicon carbide epitaxial bottom layer

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007269627A (en) * 2002-03-19 2007-10-18 Central Res Inst Of Electric Power Ind METHOD FOR MANUFACTURING SIC CRYSTAL TO REDUCE MICROPIPE PROPAGATING FROM SUBSTRATE AND SiC CRYSTAL, SiC SINGLE CRYSTAL FILM, SiC SEMICONDUCTOR ELEMENT, SiC SINGLE CRYSTAL SUBSTRATE AND ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING SiC BULK CRYSTAL
US20100119849A1 (en) * 2007-07-26 2010-05-13 Nobuhiko Nakamura Sic epitaxial substrate and method for producing the same
US20110045281A1 (en) * 2009-08-20 2011-02-24 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Reduction of basal plane dislocations in epitaxial sic
US20150128850A1 (en) * 2011-11-23 2015-05-14 University Of South Carolina Pretreatment Method for Reduction and/or Elimination of Basal Plane Dislocations Close to Epilayer/Substrate Interface in Growth of SiC Epitaxial Films
JP2015002207A (en) * 2013-06-13 2015-01-05 昭和電工株式会社 SiC EPITAXIAL WAFER AND MANUFACTURING METHOD THEREOF
CN107068539A (en) * 2016-12-15 2017-08-18 中国电子科技集团公司第五十五研究所 The method for reducing silicon carbide epitaxy base plane dislocation density
CN108166056A (en) * 2018-01-16 2018-06-15 李哲洋 A kind of growing method that can effectively reduce silicon carbide epitaxy surface defect
CN111681947A (en) * 2020-05-22 2020-09-18 东莞市天域半导体科技有限公司 Epitaxial method for reducing stacking fault defects of epitaxial wafer and application thereof
CN112670165A (en) * 2020-12-24 2021-04-16 南京百识电子科技有限公司 Growth method of silicon carbide epitaxial bottom layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116259534A (en) * 2023-05-12 2023-06-13 比亚迪股份有限公司 Silicon carbide epitaxy method

Also Published As

Publication number Publication date
CN114775046B (en) 2022-11-29

Similar Documents

Publication Publication Date Title
CN107709635B (en) Method for producing epitaxial silicon carbide single crystal wafer
US8927396B2 (en) Production process of epitaxial silicon carbide single crystal substrate
US6906400B2 (en) SiGe strain relaxed buffer for high mobility devices and a method of fabricating it
KR102285498B1 (en) How to reduce the effect of basal plane potential on the epitaxial layer of a silicon carbide substrate
JP4842094B2 (en) Epitaxial silicon carbide single crystal substrate manufacturing method
WO2011126145A1 (en) Process for producing epitaxial single-crystal silicon carbide substrate and epitaxial single-crystal silicon carbide substrate obtained by the process
CN108400159B (en) HEMT epitaxial structure with multi-quantum well high-resistance buffer layer and preparation method
JP6304699B2 (en) Method for manufacturing epitaxial silicon carbide wafer
JP6542347B2 (en) Method of manufacturing epitaxial silicon carbide single crystal wafer and epitaxial silicon carbide single crystal wafer
CN108899365B (en) High-resistance GaN-based buffer layer epitaxial structure and preparation method thereof
CN113192820A (en) Preparation method of silicon substrate aluminum nitride film
CN114775046B (en) Silicon carbide epitaxial layer growth method
CN111681947B (en) Epitaxial method for reducing stacking fault defects of epitaxial wafer and application thereof
JP2006080278A (en) Strained silicon wafer and manufacturing method thereof
CN112366130A (en) Method for reducing defect density of silicon carbide epitaxial material
JP5045955B2 (en) Group III nitride semiconductor free-standing substrate
US8563442B2 (en) Method for manufacturing nitrogen compound semiconductor substrate and nitrogen compound semiconductor substrate, and method for manufacturing single crystal SiC substrate and single crystal SiC substrate
TW202340551A (en) Nitride semiconductor substrate and method for manufacturing the same
CN113078205B (en) SiC epitaxial structure based on Al-N codoping and preparation method thereof
CN111312585B (en) Epitaxial layer growth method of low dislocation density nitride
CN114005728A (en) Low-stress high-quality nitride material epitaxy method
CN111081834A (en) Novel method for growing GaN epitaxial layer on sapphire and GaN epitaxial layer
Rana et al. Interfacial Dislocation Reduction by Optimizing Process Condition in SiC Epitaxy
CN112342524B (en) Epitaxial growth method of gallium nitride high-aluminum component
US20220077287A1 (en) Nitride semiconductor substrate

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20230825

Address after: Building 205-14, Phase 5, Building 1, Information Port, No. 733 Jianshe Third Road, Economic and Technological Development Zone, Xiaoshan District, Hangzhou City, Zhejiang Province, 311200

Patentee after: Hangzhou Jingchi Electromechanical Technology Co.,Ltd.

Address before: 310000 5th floor, No. 99, Shixin North Road, Hangzhou, Zhejiang

Patentee before: ZJU-Hangzhou Global Scientific and Technological Innovation Center