TWI760144B - Epitaxy method for super-heavy red phosphorus-doped substrate - Google Patents
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- 239000010703 silicon Substances 0.000 claims abstract description 41
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- 239000001257 hydrogen Substances 0.000 claims description 3
- 229910052739 hydrogen Inorganic materials 0.000 claims description 3
- ZDHXKXAHOVTTAH-UHFFFAOYSA-N trichlorosilane Chemical compound Cl[SiH](Cl)Cl ZDHXKXAHOVTTAH-UHFFFAOYSA-N 0.000 claims description 3
- 239000005052 trichlorosilane Substances 0.000 claims description 3
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Abstract
本發明涉及超重摻紅磷襯底外延方法，包括以下步驟：在超重摻紅磷襯底上成長超過需要厚度的本征矽層以吸收氣相中的雜質，刻蝕本征矽層至需要的厚度，在本征矽層上進行外延。本發明於現有技術中隔離的思路截然不同，通過生成過厚的本征矽層來吸收氣相中的雜質，再刻蝕至需要的厚度，有效的去除的氣相中的摻雜，解決超重摻紅磷襯底外延工藝中，氣相摻雜對於電阻率影響較大的問題，通過本發明的外延方法制得的外延片，邊緣與中心的SRP高度一致，提高了產品的良率。The invention relates to an epitaxy method for a super-heavy red phosphorus-doped substrate, comprising the following steps: growing an intrinsic silicon layer exceeding the required thickness on the super-heavy red phosphorus-doped substrate to absorb impurities in the gas phase, and etching the intrinsic silicon layer to the required thickness , epitaxy on the intrinsic silicon layer. The idea of isolation in the present invention is completely different from that in the prior art. By generating an excessively thick intrinsic silicon layer to absorb impurities in the gas phase, and then etching to the required thickness, the doping in the gas phase can be effectively removed to solve the problem of overweight. In the epitaxial process of the red phosphorus-doped substrate, the vapor-phase doping has a great influence on the resistivity. The epitaxial wafer prepared by the epitaxial method of the present invention has the same SRP height at the edge and the center, which improves the yield of the product.
Description
本發明涉及外延片的生產方法，具體涉及超重摻紅磷襯底外延方法。The invention relates to a production method of an epitaxial wafer, in particular to an epitaxial method of a super-heavy red phosphorus-doped substrate.
現有技術中的外延片生產過程中，普遍存在著自摻雜現象。自摻雜，是由於熱蒸發或者化學反應的副產物對襯底的擴散，襯底中的矽及雜質進入氣相，改變了氣相中的摻雜成分和濃度，從而導致了外延層中的雜質實際分佈偏離理想情況的現象。超重摻紅磷襯底（襯底電阻率≤1.0mohm-cm）外延中自摻雜現象嚴重，氣象中摻雜成分和濃度對於電阻率的影響較大，導致外延片邊緣與中心的SRP（spreading resistance profile，擴展電阻曲線形貌）差異明顯。In the production process of epitaxial wafers in the prior art, the phenomenon of self-doping generally exists. Self-doping is due to thermal evaporation or the diffusion of by-products of chemical reactions to the substrate, and the silicon and impurities in the substrate enter the gas phase, which changes the doping composition and concentration in the gas phase, resulting in the formation of the epitaxial layer. The phenomenon that the actual distribution of impurities deviates from the ideal situation. The self-doping phenomenon is serious in the epitaxy of the super-heavy red phosphorus-doped substrate (substrate resistivity ≤ 1.0mohm-cm), and the doping composition and concentration in the weather have a great influence on the resistivity, resulting in SRP (spreading) at the edge and center of the epitaxial wafer. resistance profile, the extended resistance curve morphology) is significantly different.
中國專利申請文獻CN106505093A公開了一種外延片的生產方法，該方法中在襯底上鋪設本征矽層（cap），從而將外延層的電阻率均勻性做到小於1.5%（計算公式，(MAX電阻率 -MIN電阻率 ) ×100％/(MAX電阻率 +MIN電阻率 )，通過此計算公式計算得出的均勻性數值越小，則其均勻性越高，外延片質量越高），從而增加了外延片的良率。其作用原理是通過本征矽層將襯底和外延層隔開，從而避免襯底本體與外延層之間產生自摻雜的問題，其本征矽層的厚度與襯底本體的厚度呈正相關。然而，這種隔離的方式只能解決襯底與外延層之間的自摻雜，無法解決氣相摻雜成分和濃度對於電阻率的影響，尤其是對於超重摻紅磷襯底的外延工藝而言，摻雜成分對於電阻率的影響較大，氣相中的摻雜成分會造成外延片邊緣與中心的SRP差異明顯，導致成品率下降。Chinese patent application document CN106505093A discloses a method for producing epitaxial wafers. In the method, an intrinsic silicon layer (cap) is laid on a substrate, so that the resistivity uniformity of the epitaxial layer is less than 1.5% (calculation formula, (MAX) Resistivity - MIN resistivity ) × 100%/(MAX resistivity + MIN resistivity ), the smaller the uniformity value calculated by this formula, the higher the uniformity and the higher the quality of the epitaxial wafer), thus Increased yield of epitaxial wafers. Its working principle is to separate the substrate and the epitaxial layer through the intrinsic silicon layer, so as to avoid the problem of self-doping between the substrate body and the epitaxial layer. The thickness of the intrinsic silicon layer is positively related to the thickness of the substrate body. . However, this isolation method can only solve the self-doping between the substrate and the epitaxial layer, and cannot solve the influence of the gas-phase doping composition and concentration on the resistivity, especially for the epitaxial process of the super-heavy red phosphorus-doped substrate. In other words, the doping composition has a great influence on the resistivity, and the doping composition in the gas phase will cause a significant difference in the SRP between the edge and the center of the epitaxial wafer, resulting in a decrease in the yield.
有鑑於此，吾等發明人乃潛心進一步研究，並著手進行研發及改良，期以一較佳發明以解決上述問題，且在經過不斷試驗及修改後而有本發明之問世。In view of this, our inventors have devoted themselves to further research, and started to carry out research and development and improvement, hoping to find a better invention to solve the above problems, and the present invention has come out after continuous experiments and modifications.
本發明的主要目的之一提供一種外延方法，克服超重摻紅磷襯底在外延邊緣自摻雜嚴重的現象，使得超重摻紅磷襯底外延片邊緣與中心的SRP高度一致。One of the main purposes of the present invention is to provide an epitaxy method, which overcomes the phenomenon of serious self-doping at the epitaxial edge of the super-heavy red phosphorus-doped substrate, so that the edge and the center of the epitaxial wafer of the super-heavy red phosphorus-doped substrate are highly consistent with SRP.
為了實現上述目的，本發明提供一種超重摻紅磷襯底外延方法，包括以下步驟：In order to achieve the above object, the present invention provides a super-heavy red phosphorus-doped substrate epitaxy method, comprising the following steps:
在超重摻紅磷襯底上成長超過需要厚度的本征矽層以吸收氣相中的雜質，Growth of an intrinsic silicon layer exceeding the required thickness on a super-heavy red phosphorus-doped substrate to absorb impurities in the gas phase,
刻蝕本征矽層至需要的厚度，Etch the intrinsic silicon layer to the desired thickness,
在本征矽層上進行外延。Epitaxy is performed on the intrinsic silicon layer.
優選地，所述的超重摻紅磷襯底的電阻率≤1.0 mohm-cm。Preferably, the resistivity of the super-heavy red phosphorus-doped substrate is less than or equal to 1.0 mohm-cm.
優選地，本征矽層需要的厚度與襯底的厚度呈正相關。Preferably, the required thickness of the intrinsic silicon layer is positively related to the thickness of the substrate.
優選地，本征矽層超過的厚度與襯底的厚度呈正相關。Preferably, the excess thickness of the intrinsic silicon layer is positively related to the thickness of the substrate.
優選地，本征矽層超過的厚度不高於襯底的厚度的20%。Preferably, the excess thickness of the intrinsic silicon layer is no more than 20% of the thickness of the substrate.
優選地，本征矽層超過的厚度不高於襯底的厚度的10%。Preferably, the excess thickness of the intrinsic silicon layer is no more than 10% of the thickness of the substrate.
優選地，本征矽層的成長速率為2.0±0.1μm/min。Preferably, the growth rate of the intrinsic silicon layer is 2.0±0.1 μm/min.
優選地，在成長所述的本征矽層之前還對襯底進行烘烤。Preferably, the substrate is also baked before growing the intrinsic silicon layer.
優選地，進行所述的刻蝕後先進行清洗再進行所述的外延。Preferably, after the etching, cleaning is performed first, and then the epitaxy is performed.
優選地，所述本征矽層由三氯矽烷與氫氣反應生成。Preferably, the intrinsic silicon layer is formed by reacting trichlorosilane with hydrogen.
本發明與現有技術中隔離的思路截然不同，通過生成過厚的本征矽層來吸收氣相中的雜質，再刻蝕至需要的厚度，有效的去除的氣相中的摻雜，解決超重摻紅磷襯底外延工藝中，氣相摻雜對於電阻率影響較大的問題，通過本發明的外延方法制得的外延片，邊緣與中心的SRP高度一致，提高了產品的良率。The invention is completely different from the idea of isolation in the prior art. By generating an excessively thick intrinsic silicon layer to absorb impurities in the gas phase, and then etching to the required thickness, the doping in the gas phase can be effectively removed to solve the problem of overweight. In the epitaxial process of the red phosphorus-doped substrate, the vapor-phase doping has a great influence on the resistivity. The epitaxial wafer prepared by the epitaxial method of the present invention has the same SRP height at the edge and the center, which improves the yield of the product.
關於吾等發明人之技術手段，茲舉數種較佳實施例配合圖式於下文進行詳細說明，俾供 鈞上深入瞭解並認同本發明。Regarding the technical means of our inventors, several preferred embodiments are hereby described in detail below with the accompanying drawings, so as to provide for an in-depth understanding and approval of the present invention.
本發明通過生成過厚的本征矽層來吸收氣相中的雜質，再刻蝕至需要的厚度。以下結合實施例和附圖對於本發明作進一步說明。The present invention absorbs impurities in the gas phase by generating an excessively thick intrinsic silicon layer, and then etches to a desired thickness. The present invention will be further described below with reference to the embodiments and the accompanying drawings.
實施例1Example 1
步驟一、烘烤（BAKE）襯底。襯底也稱為基板。襯底本體與外延層的主體構成的元素相同，均為矽。本實施例的襯底為重摻磷襯底，襯底的電阻率≤1.0 mohm-cm。
步驟二、在超重摻紅磷襯底上成長超過需要厚度的本征矽層（CAP）以吸收氣相中的雜質，所述本征矽層由三氯矽烷與氫氣反應生成。即，反應生成的單晶矽沉積在襯底本體的上表面形成所述本征矽層。本實施例中，本征矽層超過的厚度不高於襯底的厚度的20%，優選在不高於襯底的厚度10%的範圍內。本征矽層所需要的厚度一般不高於襯底厚度的10%，本征矽層的成長速率控制在2.0±0.1μm/min，成長的溫度可以控制在1110~1150℃。The second step is to grow an intrinsic silicon layer (CAP) with a thickness exceeding the required thickness on the super-heavy red phosphorus-doped substrate to absorb impurities in the gas phase, and the intrinsic silicon layer is formed by the reaction of trichlorosilane and hydrogen. That is, the single crystal silicon produced by the reaction is deposited on the upper surface of the substrate body to form the intrinsic silicon layer. In this embodiment, the excess thickness of the intrinsic silicon layer is not higher than 20% of the thickness of the substrate, preferably within a range not higher than 10% of the thickness of the substrate. The required thickness of the intrinsic silicon layer is generally not higher than 10% of the substrate thickness, the growth rate of the intrinsic silicon layer is controlled at 2.0±0.1 μm/min, and the growth temperature can be controlled at 1110~1150℃.
步驟三、用鹽酸刻蝕（ETCH）本征矽層至需要的厚度。Step 3: Etch the intrinsic silicon layer with hydrochloric acid (ETCH) to the required thickness.
步驟四：進行清洗（PURGE）。Step 4: Carry out cleaning (PURGE).
步驟五：在本征矽層上進行外延（DEPOSIT）。外延的製備溫度在1110~1150℃，生長速率可以控制在0.5-1μm/min。Step 5: Epitaxy (DEPOSIT) on the intrinsic silicon layer. The preparation temperature of epitaxy is 1110~1150℃, and the growth rate can be controlled at 0.5-1μm/min.
本實施例中採用的外延設備採用ASM 2000機台。在所述機台中採用的外延工藝的參數如下：The epitaxy equipment used in this embodiment adopts an ASM 2000 machine. The parameters of the epitaxy process used in the machine are as follows:
對得到的外延片用兩個機台進行SRP檢測，檢測的線性圖表和LOG圖表如圖1~4所示，可以看到外延片中心與邊緣3mm出的SRP曲線高度重合。The obtained epitaxial wafer was tested by two machines for SRP. The linear chart and LOG chart of the detection are shown in Figures 1 to 4. It can be seen that the SRP curve at 3 mm from the center of the epitaxial wafer and the edge is highly coincident.
比較例1Comparative Example 1
其製備方法是在襯底上製備需要厚度的本征矽層，用於隔開襯底與外延層。The preparation method is to prepare an intrinsic silicon layer with required thickness on the substrate, which is used to separate the substrate and the epitaxial layer.
該方法採用的機台與實施例1相同，在所述機台中採用的外延工藝的參數：The machine used in this method is the same as that of
對得到的外延片進行SRP檢測，檢測的線性圖表和LOG圖表如圖5~6所示，可以看到起中心與邊緣3mm處的SRP曲線有較大差異。The obtained epitaxial wafer is tested by SRP, and the linear chart and LOG chart of the test are shown in Figures 5-6. It can be seen that there is a big difference between the SRP curves at 3mm from the center and the edge.
比較例2Comparative Example 2
採用低溫工藝進行外延生長，該方法採用的機台與實施例1相同，在所述機台中採用的外延工藝的參數：A low-temperature process is used for epitaxial growth, and the machine used in this method is the same as that in Example 1, and the parameters of the epitaxial process used in the machine are:
對得到的外延片進行SRP檢測，檢測的線性圖表和LOG圖表如圖5~6所示，可以看到起中心與邊緣3mm處的SRP曲線有較大差異。The obtained epitaxial wafer is tested by SRP, and the linear chart and LOG chart of the test are shown in Figures 5-6. It can be seen that there is a big difference between the SRP curves at 3mm from the center and the edge.
經過上述比較可知，本發明過厚的本征矽層吸收了氣相中的雜質，有效的去除的氣相中的摻雜，解決超重摻紅磷襯底外延工藝中，氣相摻雜對於電阻率影響較大的問題，外延片邊緣與中心的SRP高度一致，提高了產品的良率。Through the above comparison, it can be seen that the excessively thick intrinsic silicon layer of the present invention absorbs impurities in the gas phase, effectively removes the impurities in the gas phase, and solves the problem of the effect of gas phase doping on resistance in the epitaxial process of the super-heavy red phosphorus-doped substrate. The SRP at the edge and center of the epitaxial wafer is highly consistent, which improves the yield of the product.
以上僅為本發明較佳的實施例，並不用於局限本發明的保護範圍，任何在本發明精神內的修改、等同替換或改進等，都涵蓋在本發明的權利要求範圍內。The above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements or improvements within the spirit of the present invention are all included within the scope of the claims of the present invention.
綜上所述，本發明所揭露之技術手段確能有效解決習知等問題，並達致預期之目的與功效，且申請前未見諸於刊物、未曾公開使用且具長遠進步性，誠屬專利法所稱之發明無誤，爰依法提出申請，懇祈 鈞上惠予詳審並賜准發明專利，至感德馨。To sum up, the technical means disclosed in the present invention can indeed effectively solve the problems of conventional knowledge and achieve the expected purpose and effect, and it has not been published in publications before the application, has not been used publicly, and has long-term progress. The invention referred to in the Patent Law is correct, and the application is filed in accordance with the law. I sincerely pray that Jun Shang will give me a detailed examination and grant the invention patent. I am very grateful.
惟以上所述者，僅為本發明之數種較佳實施例，當不能以此限定本發明實施之範圍，即大凡依本發明申請專利範圍及發明說明書內容所作之等效變化與修飾，皆應仍屬本發明專利涵蓋之範圍內。However, the above are only several preferred embodiments of the present invention, and should not limit the scope of implementation of the present invention, that is, any equivalent changes and modifications made according to the scope of the patent application of the present invention and the contents of the description of the invention are all equivalents. It should still fall within the scope of the patent of the present invention.
〔本發明〕 1、3、5、7、9、11、13和15:為各個圖中的外延片中心的SRP曲線 2、4、6、8、10、12、14、16:為各個圖中的外延片邊緣3mm處的SRP曲線〔this invention〕 1, 3, 5, 7, 9, 11, 13 and 15: SRP curves for the epitaxial wafer center in each figure 2, 4, 6, 8, 10, 12, 14, 16: SRP curves at 3mm from the edge of the epitaxial wafer in each figure
[圖1]為實施例1的SRP線性比對圖; [圖2]為實施例1的SRP LOG比對圖; [圖3]為實施例1的另一SRP線性比對圖; [圖4]為實施例1的另一SRP LOG比對圖; [圖5]為比較例1的SRP線性比對圖; [圖6]為比較例1的SRP LOG比對圖; [圖7]為比較例2的SRP線性比對圖; [圖8]為比較例2的SRP LOG比對圖。[Figure 1] is the SRP linear comparison diagram of Example 1; [Fig. 2] is the SRP LOG comparison diagram of Example 1; [Figure 3] is another SRP linear comparison diagram of Example 1; [Figure 4] is another SRP LOG comparison diagram of Example 1; [Figure 5] is the SRP linear comparison diagram of Comparative Example 1; [Figure 6] is the SRP LOG comparison chart of Comparative Example 1; [Figure 7] is the SRP linear comparison diagram of Comparative Example 2; FIG. 8 is a comparison chart of the SRP LOG of Comparative Example 2. FIG.
1:為各個圖中的外延片中心的SRP曲線 1: SRP curve for the epitaxial wafer center in each figure
2:為各個圖中的外延片邊緣3mm處的SRP曲線 2: SRP curve at the edge of the epitaxial wafer at 3mm in each figure
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