CN106876246A - The method for improving resistivity evenness in epitaxial wafer piece - Google Patents

The method for improving resistivity evenness in epitaxial wafer piece Download PDF

Info

Publication number
CN106876246A
CN106876246A CN201710078668.1A CN201710078668A CN106876246A CN 106876246 A CN106876246 A CN 106876246A CN 201710078668 A CN201710078668 A CN 201710078668A CN 106876246 A CN106876246 A CN 106876246A
Authority
CN
China
Prior art keywords
epitaxial
temperature
furnace
hydrogen
growth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710078668.1A
Other languages
Chinese (zh)
Inventor
贾松
张绪刚
陈秉克
赵丽霞
袁肇耿
薛宏伟
侯志义
张志勤
吴会旺
周晓龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Puxing Electronic Science & Technology Co Ltd Hebei
Original Assignee
Puxing Electronic Science & Technology Co Ltd Hebei
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Puxing Electronic Science & Technology Co Ltd Hebei filed Critical Puxing Electronic Science & Technology Co Ltd Hebei
Priority to CN201710078668.1A priority Critical patent/CN106876246A/en
Publication of CN106876246A publication Critical patent/CN106876246A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

The invention discloses a kind of method for improving resistivity evenness in epitaxial wafer piece, it is related to the preparation method technical field of silicon substrate epitaxial layer.Methods described comprises the following steps：Hydrogen chloride gas using high-purity corrode to extension furnace foundation seat at high temperature；To silicon substrate film is loaded in extension furnace foundation seat piece hole, using the hydrogen purge extension furnace cavity of high-purity, the temperature until reaching setting in epitaxial furnace temperature-rise period；More than the min of constant temperature 5；Epitaxial furnace carries out big flow variable-flow purging after being warming up to design temperature, and gas flow is set as 100 400L/min, and the time is more than 4 min；Epitaxial furnace is cooled into epitaxial growth temperature, the epitaxial growth of silicon substrate film is carried out.Methods described can make resistivity in epitaxial wafer piece, and evenly, yield maximization is lifted, and SRP curved profile uniformity has larger lifting.

Description

The method for improving resistivity evenness in epitaxial wafer piece
Technical field
The present invention relates to electricity in the preparation method technical field of silicon substrate epitaxial layer, more particularly to a kind of raising epitaxial wafer piece The method of resistance rate uniformity.
Background technology
In the case of heavily doped arsenic substrate high temperature epitaxy, As vaporization at high temperature causes lack of homogeneity in electrical resistivity of epitaxy piece；Meanwhile, The substrate of different As concentration, As vaporization at high temperature situations are inconsistent, and auto-dope is different between causing stove, and then cause epitaxial layer electricity between stove The fluctuation of resistance rate is big.As heavy doping substrate vaporization at high temperature auto-dopes are gradually decreased with the epitaxial growth time, cause epitaxial layer longitudinal direction bent Line profile is a curve, and different auto-dope situations, and curved profile is inconsistent, and epitaxial wafer has extra change between causing stove Difference, influences subsequent device BVDSS discretenesses.Thus, new method is needed badly to suppress in the caused resistivity stove of high temperature As volatilizations Fluctuate big situation between lack of homogeneity and stove.
The content of the invention
The technical problems to be solved by the invention are how to provide one kind to improve resistivity evenness in epitaxial wafer piece Method.
In order to solve the above technical problems, the technical solution used in the present invention is：One kind improves resistivity in epitaxial wafer piece The method of uniformity, it is characterised in that comprise the following steps：
To silicon substrate film is loaded in extension furnace foundation seat piece hole, using the hydrogen purge epitaxial furnace of high-purity in epitaxial furnace temperature-rise period Cavity, gas flow is set as 130 L/min -400L/min, the temperature until reaching setting, and the temperature for setting is outer Prolong 5 DEG C -10 DEG C on stove epitaxial growth temperature；
More than the min of constant temperature 5, makes As impurity fully volatilize；
Epitaxial furnace carries out big flow variable-flow purging after being warming up to design temperature, and gas flow is set as 100--400L/min, when Between be more than 4 min；
Epitaxial furnace is cooled into epitaxial growth temperature, the epitaxial growth of silicon substrate film is carried out.
Further technical scheme is also to include before loading silicon substrate film in extension furnace foundation seat piece hole：
Hydrogen chloride gas using high-purity corrode to extension furnace foundation seat at high temperature, and temperature is set as more than 1000 DEG C, Hydrogen chloride gas flow set is that, more than 1L/min, etch period is set greater than 4min.
Further technical scheme is：Purity >=99.99% of the hydrogen chloride gas and hydrogen.
Further technical scheme is：The silicon substrate film is heavily doped As substrates, resistivity<0.005ohm.cm.
Further technical scheme is that the epitaxial growth method of the silicon substrate film comprises the following steps：
Carry out the growth of intrinsic epitaxial layer；
Silicon substrate film surface is purged using variable-flow hydrogen, by adsorb intrinsic epitaxial layer surface, base-plates surface it is miscellaneous Matter is removed and discharges extension furnace chamber；
It is doped the growth of epitaxial layer；
Doped epitaxial layer growth reaches and start after predetermined thickness cooling, by hydrogen and nitrogen flow be respectively set as 300L/min, 150L/min, purges epitaxial furnace reaction chamber 10min ~ 13 min successively, and then epitaxial wafer is taken out from pedestal.
Further technical scheme is：When carrying out the growth of intrinsic epitaxial layer, using the trichlorosilane for undoping in lining Intrinsic epitaxial layer is grown on bottom, substrate surface and edge are encapsulated.
Further technical scheme is：Intrinsic layer growth temperature is set as 1080 DEG C -1100 DEG C, and gaseous state is conveyed with hydrogen Trichlorosilane enters reaction chamber, and hydrogen flowing quantity is controlled in 180 L/min -220L/min.
Further technical scheme is：The flow of hydrogen first become greater to when variable-flow hydrogen is purged to silicon substrate film surface Certain value, then certain value is varied down to, excursion is 200 L/min-400 L/min.
Further technical scheme is：The control of epitaxial furnace pedestal rotating speed is in 5 r/ when being doped the growth of epitaxial layer Min -7r/min, growth temperature is set as 1080 DEG C -1100 DEG C, and hydrogen flowing quantity is controlled in 180 L/min -220L/min.
Further technical scheme is that the epitaxial growth method of the silicon substrate film also comprises the following steps：
The thickness and uniformity of epitaxial layer are measured using Fourier's infrared test method, using mercury probe CV methods of testing to silicon The resistivity and its uniformity of epitaxial wafer are measured, and the transition between substrate and epitaxial layer is measured using Spreading resistance method Plot structure.
It is using the beneficial effect produced by above-mentioned technical proposal：Methods described is by high before silicon substrate film epitaxial growth Temperature（It is higher by epitaxial growth temperature more than 5 degree）Constant temperature, makes As impurity fully volatilize；And caught up with for a long time by big flow and variable-flow As foreign gases in gas, fully emptying epitaxial furnace, evenly, yield maximization is lifted can to make resistivity in epitaxial wafer piece（From 70% Lifted to 95%）；And SRP（The spreading resistance rate curve of epitaxial layer）Curved profile uniformity has larger lifting.
Brief description of the drawings
Fig. 1 is the flow chart of embodiment of the present invention methods described.
Specific embodiment
With reference to the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Ground description, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made Embodiment, belongs to the scope of protection of the invention.
Many details are elaborated in the following description in order to fully understand the present invention, but the present invention can be with Other manner described here is different from using other to implement, those skilled in the art can be without prejudice to intension of the present invention In the case of do similar popularization, therefore the present invention is not limited by following public specific embodiment.
Overall, as shown in figure 1, the embodiment of the invention discloses a kind of side for improving resistivity evenness in epitaxial wafer piece Method, comprises the following steps：
S101：Hydrogen chloride gas using high-purity corrode to extension furnace foundation seat at high temperature, and temperature is set as 1000 DEG C More than, hydrogen chloride gas flow set is that, more than 1L/min, etch period is set greater than 4min；
S102：To silicon substrate film is loaded in extension furnace foundation seat piece hole, using the hydrogen purge of high-purity in epitaxial furnace temperature-rise period Extension furnace cavity, gas flow is set as 130 L/min -400L/min, the temperature until reaching setting, the temperature of the setting Spend for 5 DEG C -10 DEG C on epitaxial furnace epitaxial growth temperature；
S103：More than the min of constant temperature 5, makes As impurity fully volatilize；
S104：Epitaxial furnace carries out big flow variable-flow purging after being warming up to design temperature, and gas flow is set as 100--400L/ Min, the time is more than 4 min；
S105：Epitaxial furnace is cooled into epitaxial growth temperature, the epitaxial growth of silicon substrate film is carried out.
Specifically, the embodiment of the present invention improves resistivity evenness in epitaxial wafer piece by following steps：
Using the plate epitaxial growth systems of CSD 5000, high frequency radiation heating, high purity graphite pedestal is silicon chip carrier, protects gas It is ultra-pure H2 gas, purity reaches more than 99.999999%.
Hydrogen chloride using purity >=99.99% corrodes to extension furnace foundation seat at high temperature, removes on pedestal completely Residual deposits material, temperature is set as 1120 DEG C, and hydrogen chloride gas flow set is 2L/min, etch period is set as 10 ~ 15min；
To silicon substrate film is loaded in extension furnace foundation seat piece hole, the hydrogen in equipment temperature-rise period using purity >=99.999% blows Extension furnace cavity is swept, gas flow is set as 200L/min;Big flow flow of purge gas is proceeded by when the set temperature is reached Amount is set as 400L/min
In-situ corrosion is carried out to silicon substrate film surface using hydrogen chloride gas in big flow purge, surface throwing is played to substrate Light action, helps to improve lattice structure, the by-product produced when by the way of big flow H2 purgings by hydrogen chloride in-situ corrosion Thing, and absorption removes discharge chamber completely in the impurity of substrate surface, base-plates surface, effectively reduces auto-dope, gas flow It is set as 400L/min.
Variable-flow hydrogen is purged to silicon substrate film surface before intrinsic epitaxial layer growth（400-200 L/min）To adsorb at this Levy epi-layer surface, the impurity of base-plates surface removes discharge chamber completely, effectively reduces auto-dope.
The growth of intrinsic epitaxial layer is carried out, using the trichlorosilane for undoping in Grown intrinsic epitaxial layer, to lining Basal surface and edge are encapsulated, and prevent the spilling of heavily doped substrate impurity；Intrinsic layer growth temperature is set as 1095 DEG C, utilizes The quick intrinsic growing method of high temperature, quickly completes encapsulating, more conducively suppresses non-active doping effect；Gaseous state trichlorine is conveyed with hydrogen Hydrogen silicon enters reaction chamber, and hydrogen flowing quantity is controlled in 200L/min；
Intrinsic epitaxial layer growth finishes rear variable-flow hydrogen and silicon substrate film surface is purged（200-400-200 L/min）To inhale It is attached to intrinsic epitaxial layer surface, the impurity of base-plates surface removes discharge chamber completely, effectively reduces auto-dope.
The growth of epitaxial layer is doped, epitaxial furnace pedestal rotating speed is controlled in 6r/min；Growth temperature is set as 1095 DEG C Hydrogen flowing quantity is controlled in 200L/min
Outer layer growth starts cooling after reaching predetermined thickness, and hydrogen and nitrogen flow are respectively set as into 300,150L/min, Purging epitaxial furnace reaction chamber 10 ~ 13 minutes, then takes out epitaxial wafer from pedestal successively；Using Fourier's infrared test method Thickness and uniformity to epitaxial layer are measured, using mercury probe CV methods of testing to the resistivity and its uniformity of silicon epitaxial wafer Measure, the transition plot structure between substrate and epitaxial layer is measured using Spreading resistance method.

Claims (10)

1. it is a kind of improve epitaxial wafer piece in resistivity evenness method, it is characterised in that comprise the following steps：
To silicon substrate film is loaded in extension furnace foundation seat piece hole, using the hydrogen purge epitaxial furnace of high-purity in epitaxial furnace temperature-rise period Cavity, gas flow is set as 130 L/min -400L/min, the temperature until reaching setting, and the temperature for setting is outer Prolong 5 DEG C -10 DEG C on stove epitaxial growth temperature；
More than the min of constant temperature 5, makes As impurity fully volatilize；
Epitaxial furnace carries out big flow variable-flow purging after being warming up to design temperature, and gas flow is set as 100--400L/min, when Between be more than 4 min；
Epitaxial furnace is cooled into epitaxial growth temperature, the epitaxial growth of silicon substrate film is carried out.
2. the method for improving resistivity evenness in epitaxial wafer piece as claimed in claim 1, it is characterised in that to epitaxial furnace Also include before loading silicon substrate film in base pieces hole：
Hydrogen chloride gas using high-purity corrode to extension furnace foundation seat at high temperature, and temperature is set as more than 1000 DEG C, Hydrogen chloride gas flow set is that, more than 1L/min, etch period is set greater than 4min.
3. the method for improving resistivity evenness in epitaxial wafer piece as claimed in claim 2, it is characterised in that：The hydrogen chloride Purity >=99.99% of gas and hydrogen.
4. the method for improving resistivity evenness in epitaxial wafer piece as claimed in claim 1, it is characterised in that：The silicon substrate Piece is heavily doped As substrates, resistivity<0.005ohm.cm.
5. the method for improving resistivity evenness in epitaxial wafer piece as claimed in claim 1, it is characterised in that the silicon substrate The epitaxial growth method of piece comprises the following steps：
Carry out the growth of intrinsic epitaxial layer；
Silicon substrate film surface is purged using variable-flow hydrogen, by adsorb intrinsic epitaxial layer surface, base-plates surface it is miscellaneous Matter is removed and discharges extension furnace chamber；
It is doped the growth of epitaxial layer；
Doped epitaxial layer growth reaches and start after predetermined thickness cooling, by hydrogen and nitrogen flow be respectively set as 300L/min, 150L/min, purges epitaxial furnace reaction chamber 10min ~ 13 min successively, and then epitaxial wafer is taken out from pedestal.
6. the method for improving resistivity evenness in epitaxial wafer piece as claimed in claim 5, it is characterised in that：Carry out intrinsic outer When prolonging the growth of layer, using the trichlorosilane for undoping in Grown intrinsic epitaxial layer, substrate surface and edge are entered Row encapsulating.
7. the method for improving resistivity evenness in epitaxial wafer piece as claimed in claim 5, it is characterised in that：Intrinsic layer grows Temperature is set as 1080 DEG C -1100 DEG C, and conveying gaseous state trichlorosilane with hydrogen enters reaction chamber, and hydrogen flowing quantity is controlled 180 L/min -220L/min。
8. the method for improving resistivity evenness in epitaxial wafer piece as claimed in claim 5, it is characterised in that：Variable-flow hydrogen The flow of hydrogen first become greater to certain value when being purged to silicon substrate film surface, then is varied down to certain value, and excursion is 200 L/ min-400 L/min。
9. the method for improving resistivity evenness in epitaxial wafer piece as claimed in claim 5, it is characterised in that：It is doped outer In 5 r/min -7r/min, growth temperature is set as 1080 DEG C -1100 DEG C to the control of epitaxial furnace pedestal rotating speed when prolonging the growth of layer, Hydrogen flowing quantity is controlled in 180 L/min -220L/min.
10. the method for improving resistivity evenness in epitaxial wafer piece as claimed in claim 5, it is characterised in that：The silicon lining The epitaxial growth method of egative film also comprises the following steps：
The thickness and uniformity of epitaxial layer are measured using Fourier's infrared test method, using mercury probe CV methods of testing to silicon The resistivity and its uniformity of epitaxial wafer are measured, and the transition between substrate and epitaxial layer is measured using Spreading resistance method Plot structure.
CN201710078668.1A 2017-02-14 2017-02-14 The method for improving resistivity evenness in epitaxial wafer piece Pending CN106876246A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710078668.1A CN106876246A (en) 2017-02-14 2017-02-14 The method for improving resistivity evenness in epitaxial wafer piece

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710078668.1A CN106876246A (en) 2017-02-14 2017-02-14 The method for improving resistivity evenness in epitaxial wafer piece

Publications (1)

Publication Number Publication Date
CN106876246A true CN106876246A (en) 2017-06-20

Family

ID=59166211

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710078668.1A Pending CN106876246A (en) 2017-02-14 2017-02-14 The method for improving resistivity evenness in epitaxial wafer piece

Country Status (1)

Country Link
CN (1) CN106876246A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110456152A (en) * 2019-07-08 2019-11-15 河北普兴电子科技股份有限公司 A kind of test method, system and the terminal device of epilayer resistance rate
CN111489964A (en) * 2020-04-27 2020-08-04 中国电子科技集团公司第四十六研究所 Preparation method of thick-layer silicon epitaxial wafer for reducing pattern drift rate
CN113638043A (en) * 2021-08-16 2021-11-12 季华实验室 Purging and cooling system, method and device for epitaxial furnace, electronic equipment and storage medium
CN113737151A (en) * 2021-08-30 2021-12-03 中国电子科技集团公司第四十六研究所 Preparation method of silicon epitaxial wafer for PIN switch device
CN113737276A (en) * 2021-08-30 2021-12-03 中国电子科技集团公司第四十六研究所 Method for improving silicon epitaxial growth rate
CN114628243A (en) * 2022-03-10 2022-06-14 河北普兴电子科技股份有限公司 Preparation method of double-layer silicon epitaxial wafer for fast recovery epitaxial diode

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101295638A (en) * 2008-06-17 2008-10-29 河北普兴电子科技股份有限公司 Extension method of material for low forward voltage drop Schottky diode
CN102157359A (en) * 2011-01-30 2011-08-17 福建福顺微电子有限公司 Method for manufacturing 6-inch POWERMOS transistor epitaxial layer
CN103541001A (en) * 2013-10-31 2014-01-29 中国电子科技集团公司第四十六研究所 Preparation method for improving electrical resistivity and thickness consistency of epitaxial slice
CN104282535A (en) * 2014-10-23 2015-01-14 中国电子科技集团公司第四十六研究所 Method for improving electrical resistivity evenness of P-type silicon epitaxial wafer for CCD
CN104851784A (en) * 2015-05-29 2015-08-19 中国电子科技集团公司第四十六研究所 Method for growing high-resistance thick layer silicon epitaxy on 6-inch heavily As-doped silicon substrate
CN104947183A (en) * 2015-05-29 2015-09-30 中国电子科技集团公司第四十六研究所 Production method of heavily phosphorus-doped thin substrate silicon epitaxial layer for Schottky devices

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101295638A (en) * 2008-06-17 2008-10-29 河北普兴电子科技股份有限公司 Extension method of material for low forward voltage drop Schottky diode
CN102157359A (en) * 2011-01-30 2011-08-17 福建福顺微电子有限公司 Method for manufacturing 6-inch POWERMOS transistor epitaxial layer
CN103541001A (en) * 2013-10-31 2014-01-29 中国电子科技集团公司第四十六研究所 Preparation method for improving electrical resistivity and thickness consistency of epitaxial slice
CN104282535A (en) * 2014-10-23 2015-01-14 中国电子科技集团公司第四十六研究所 Method for improving electrical resistivity evenness of P-type silicon epitaxial wafer for CCD
CN104851784A (en) * 2015-05-29 2015-08-19 中国电子科技集团公司第四十六研究所 Method for growing high-resistance thick layer silicon epitaxy on 6-inch heavily As-doped silicon substrate
CN104947183A (en) * 2015-05-29 2015-09-30 中国电子科技集团公司第四十六研究所 Production method of heavily phosphorus-doped thin substrate silicon epitaxial layer for Schottky devices

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110456152A (en) * 2019-07-08 2019-11-15 河北普兴电子科技股份有限公司 A kind of test method, system and the terminal device of epilayer resistance rate
CN111489964A (en) * 2020-04-27 2020-08-04 中国电子科技集团公司第四十六研究所 Preparation method of thick-layer silicon epitaxial wafer for reducing pattern drift rate
CN111489964B (en) * 2020-04-27 2022-05-10 中国电子科技集团公司第四十六研究所 Preparation method of thick-layer silicon epitaxial wafer for reducing pattern drift rate
CN113638043A (en) * 2021-08-16 2021-11-12 季华实验室 Purging and cooling system, method and device for epitaxial furnace, electronic equipment and storage medium
CN113737151A (en) * 2021-08-30 2021-12-03 中国电子科技集团公司第四十六研究所 Preparation method of silicon epitaxial wafer for PIN switch device
CN113737276A (en) * 2021-08-30 2021-12-03 中国电子科技集团公司第四十六研究所 Method for improving silicon epitaxial growth rate
CN113737276B (en) * 2021-08-30 2024-04-16 中国电子科技集团公司第四十六研究所 Method for improving silicon epitaxial growth rate
CN114628243A (en) * 2022-03-10 2022-06-14 河北普兴电子科技股份有限公司 Preparation method of double-layer silicon epitaxial wafer for fast recovery epitaxial diode

Similar Documents

Publication Publication Date Title
CN106876246A (en) The method for improving resistivity evenness in epitaxial wafer piece
JP3888059B2 (en) Vapor growth equipment
CN107068539A (en) The method for reducing silicon carbide epitaxy base plane dislocation density
CN103370454B (en) Epitaxial silicon carbide single crystal substrate and manufacture method thereof
CN106128938B (en) A kind of VDMOS device method that thick-layer extension is prepared on thin Sb substrates
CN104947183B (en) A kind of preparation method of schottky device silicon epitaxy layer on heavily doped thin phosphorus substrate
US8709156B2 (en) Methods for producing epitaxially coated silicon wafers
CN105826186A (en) Growing method for high-surface-quality silicon carbide epitaxial layer
CN106757324A (en) A kind of manufacture method of silicon epitaxial wafer
CN102668033A (en) Semiconductor thin-film manufacturing method, seminconductor thin-film manufacturing apparatus, susceptor, and susceptor holding tool
CN104851784A (en) Method for growing high-resistance thick layer silicon epitaxy on 6-inch heavily As-doped silicon substrate
CN102610500A (en) Method for preparing N-type heavily-doping silicon carbide film epitaxy
CN115029782B (en) Silicon carbide epitaxial growth method
JP2010534940A (en) Apparatus and method for controlling substrate temperature during thin film solar manufacturing
CN103603048B (en) A kind of chemical vapor depsotition equipment for producing silicon carbide epitaxial wafer
JP2018083754A (en) Compound semiconductor wafer and photoelectric conversion element
CN101110356A (en) Control method for epitaxial layer transition zone on re-mixed arsenic underlay
CN113668058A (en) Growth method of n-type silicon carbide crystal for reducing nitrogen doping integral nonuniformity
CN105489478B (en) The regulation and control method of heavily doped phosphorus Substrate lamina extension transition region
CN116259534A (en) Silicon carbide epitaxy method
CN108538713A (en) A kind of method that photodetector prepares high resistant epitaxial layer with heavily doped silicon substrate
JP3424069B2 (en) Manufacturing method of epitaxial silicon substrate
CN105671631B (en) Method for cleaning back surface of 200mm-300mm epitaxial equipment base in situ
CN108767053A (en) A kind of manufacturing method of novel infrared detector BIB silicon epitaxial wafers
JP2020126885A (en) Film forming apparatus and film forming method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20170620

RJ01 Rejection of invention patent application after publication