WO2018120731A1

WO2018120731A1 - Manufacturing method for silicon epitaxial wafer

Info

Publication number: WO2018120731A1
Application number: PCT/CN2017/091796
Authority: WO
Inventors: 刘勇; 金龙; 谭卫东
Original assignee: 南京国盛电子有限公司
Priority date: 2016-12-26
Filing date: 2017-07-05
Publication date: 2018-07-05
Also published as: CN106757324A; CN106757324B

Abstract

Disclosed is a manufacturing method for a silicon epitaxial wafer, comprising the following technical process: First, a monolithic atmospheric-pressure silicon epitaxy apparatus is used and a suitable H₂ flow rate, temperature, and time are selected to conduct baking treatment on a substrate silicon wafer to remove a natural oxide layer on the surface and ensure the quality of the surface before epitaxy. A first layer is epitaxially grown: an undoped intrinsic layer is grown on the surface of the heavily doped substrate to encapsulate the substrate surface, and the growth temperature, growth rate, and growth time of the intrinsic layer are controlled to achieve a desirable encapsulation effect. A second layer is epitaxially grown: SiHCl₃ is used as a silicon source, the flow rate of main H₂ is increased, and HCl fed at a suitable flow rate, so as to reduce the growth rate to grow a thinner epitaxial layer having a thickness meeting a requirement for a device.

Description

Method for manufacturing silicon epitaxial wafer

Technical field

The invention relates to a silicon epitaxial wafer, that is, a method for manufacturing an ultrathin layer low resistance epitaxial wafer.

Background technique

The monolithic atmospheric pressure epitaxial device with SiHCl ₃ as the silicon source tends to have a growth rate of more than 2 μm/min, while for the 8-inch ultra-thin layer epitaxy with an epitaxial layer thickness of less than 2 μm, the faster growth rate leads to poor uniformity of the epitaxial layer thickness. The transition region between the epitaxial layer and the substrate is wider, which reduces the effective thickness of the epitaxial layer and cannot meet the requirements of the device end (the theoretical longitudinal resistivity distribution of the device end requirement is shown in FIG. 2). At present, thin layer epitaxy of less than 2 μm for 8-inch silicon epitaxial products often uses decompression epitaxy or replacement of other silicon sources such as silane (SiH ₄ ), which requires additional production costs and reduces the compatibility of atmospheric pressure epitaxy equipment.

In summary, it is necessary to design a fast and highly accurate control method for the micro hydraulic drive system.

Summary of the invention

Aiming at the problems existing in the prior art, according to the generation mechanism, the suppression method and the solid state diffusion theory of the epitaxial process self-doping effect, the invention proposes a novel manufacturing method of the epitaxial wafer, which can be optimized compared with the conventional epitaxial method. Epitaxial layer thickness and resistivity uniformity optimize the transition region width of the substrate and epitaxial layer.

In order to achieve the above object, the present invention can adopt the following technical solutions:

A method for manufacturing a silicon epitaxial wafer, comprising the steps of:

(1) performing high temperature treatment of the susceptor on the susceptor, removing residual reactants on the susceptor, and depositing a layer of intrinsic polysilicon;

(2) loading the substrate wafer after cooling the pedestal

(3), wafer baking

(4) First layer epitaxial growth: an intrinsic layer is grown on the surface of the substrate to encapsulate the surface of the substrate;

(5) Second layer epitaxial growth: When the second layer is epitaxially grown, HCl and TCS are simultaneously introduced, wherein 0.5-1 slm of HCl, 2-5 g of TCS, and 120-180 slm of H2 are introduced.

Advantageous Effects: The method for fabricating the epitaxial wafer of the present invention can optimize the thickness and resistivity uniformity of the 8-inch ultra-thin epitaxial layer and optimize the transition region width of the substrate and the epitaxial layer as compared with the conventional epitaxial method. In particular, HCl and TCS are simultaneously introduced during the epitaxial growth of the two layers, in order to reduce the growth thickness of the epitaxial layer and suppress the self-doping effect of the silicon wafer, which plays a key role in achieving the above technical effects.

Preferably, in step (2), the susceptor is cooled to 850 °C.

Preferably, in the step (3), the baking temperature is 1150-1180 ° C, the baking time is 40 seconds, and the H ₂ flow rate is 120-180 slm.

Preferably, it is characterized in that the appropriate epitaxial conditions for the first layer epitaxial growth are: baking temperature 1150-1180 ° C, baking main H 2 flow rate is 120-180 slm; first layer epitaxy, growth temperature 1100-1130 ° C, precipitation The product rate is 0.8-1.0 μm/min; when the second layer is epitaxially grown, the temperature is 1100-1130 ° C, and the deposition rate is 0.4-0.6 μm/min.

Preferably, the first layer is epitaxially grown without doping, and the second layer is doped epitaxially grown with an H2 flow rate of 120-180 slm.

Preferably, the deposition is selected to be: a growth temperature of 1100-1130 ° C, a growth silicon source flow rate of 2-5 g, a growth HCl flow rate of 0.5-1 slm, and a growth main H ₂ flow rate of 120-180 slm.

Preferably, the substrate sheet is selected: an 8-inch heavy-doped phosphorus-silicon polished sheet is used, the resistivity is ≤0.001 Ω·cm, the partial flatness of the substrate sheet is ≤1.5 m (10 mm×10 mm); the silicon dioxide back sealing layer (LTO) ) + Polysilicon back seal (Poly) back seal.

DRAWINGS

Figure 1 is a process flow diagram of an 8-inch thin layer epitaxy;

2 is a schematic view showing the longitudinal structure of an 8-inch thin layer epitaxial layer;

Figure 3 is a structural diagram of the ASM E2000 reaction chamber;

Figure 4 shows the measured longitudinal carrier distribution of an 8-inch thin-layer epitaxial layer.

detailed description

The invention discloses a method for manufacturing an epitaxial wafer, which is preferably suitable for the manufacture of an 8-inch ultra-thin layer low-resistance epitaxial wafer.

Embodiment 1:

The manufacturing method of an 8-inch ultra-thin layer low-resistance epitaxial wafer of this embodiment comprises the following steps:

The device used in the invention is the American ASM E2000 silicon epitaxial growth system. As shown in FIG. 3, the high-purity graphite base is used as the infrared heating body, and the purity of the main carrier gas H2 is 99.9999% or more.

Reaction chamber cleaning: The quartz bell and the quartz parts used in the reaction chamber must be carefully cleaned before the epitaxy to completely remove the deposition residue on the inner wall of the quartz bell jar and the quartz piece.

The first step: high temperature treatment of the reaction chamber: before each epitaxial growth, the graphite pedestal must be subjected to high temperature treatment of HC1 to remove residual reactants on the susceptor and deposit a layer of intrinsic polycrystalline silicon.

The second step: cooling the reaction chamber to a low temperature (850 ° C), loading the substrate wafer.

The third step: heating to 1150 ° C, H ₂ flow 100slm, and holding for 30 seconds for wafer baking, reducing epitaxial layer defects.

The fourth step: the first intrinsic epitaxial layer, 1100 ° C, 2 g of silicon source, 120 slm of main H2, deposition rate of 0.8 μm / min, growth time of 7 seconds.

Step 5: The temperature is set to 1100 ° C, H 2 is 120 slm, and the blow is performed for 10 seconds.

The sixth step: the second layer growth temperature is 1100 ° C, the HCl flow rate is 0.5 slm, and the silicon source is 2 g. At this time, the HCl and the silicon source are simultaneously introduced for growth, the main H2 is 120 slm, and the deposition rate is 0.4-0.6 μm/min. The growth time is 82 seconds.

Embodiment 2

The first three steps are the same as those described in the first embodiment.

The fourth step: the first intrinsic epitaxial layer, 1120 ° C, 3 g of silicon source, 150 slm of main H2, deposition rate of 0.8 μm / min, growth time of 7 seconds.

Step 5: The temperature is set to 1130 ° C, H 2 is 150 slm, and the blow is performed for 90 seconds.

The sixth step: the second layer growth temperature is 1120 ° C, the HCl flow rate is 0.8 slm, and the silicon source is 3 g. At this time, the HCl and the silicon source are simultaneously introduced for growth, the main H2 is 150 slm, and the deposition rate is 0.4-0.6 μm/min. The growth time is 82 seconds.

Embodiment 3

The first three steps are the same as those described in the first embodiment.

The fourth step: the first intrinsic epitaxial layer, 1130 ° C, 5 g of silicon source, 180 slm of main H2, deposition rate of 0.8 μm / min, growth time of 7 seconds.

Step 5: The temperature is set to 1150 ° C, H 2 is 120 slm, and the blow is performed for 120 seconds.

The sixth step: the second layer growth temperature is 1130 ° C, the HCl flow rate is 1 slm, and the silicon source is 5 g. At this time, the HCl and the silicon source are simultaneously introduced for growth, the main H2 is 180 slm, and the deposition rate is 0.4-0.6 μm/min. The growth time is 82 seconds.

The above operation steps are shown in Figure 1.

After testing the silicon epitaxial wafer manufactured by the methods of Embodiments 1, 2 and 3, the prepared silicon epitaxial wafer has a good lattice structure, the surface is bright and has no fine spots, no warping and edge crystallization, and enters the gas phase. The impurity is less, the self-doping effect is reduced, the dislocation is <100/cm ² , and the stacking fault is <10/cm ² . When the epitaxial thickness is less than 0.7 μm, the epitaxial transition region is less than 0.2 μm, and the longitudinal resistivity distribution diagram is as shown in the figure. 4, fully meet the requirements of device fabrication.

There are many ways and means for implementing the technical solution of the present invention, and the above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art will not deviate from the original invention. Under the premise of the rationale, a number of improvements and refinements can also be made, and these improvements and retouchings should also be considered as protection scope of the present invention. The components that are not clear in this embodiment can be implemented by the prior art.

Claims

A method for manufacturing a silicon epitaxial wafer, comprising the steps of:

(1) performing high temperature treatment of the susceptor on the susceptor, removing residual reactants on the susceptor, and depositing a layer of intrinsic polysilicon;

(2) loading the substrate wafer after cooling the pedestal

(3), wafer baking

(4) First layer epitaxial growth: an intrinsic layer is grown on the surface of the substrate to encapsulate the surface of the substrate;

(5) Second layer epitaxial growth: When the second layer is epitaxially grown, HCl and TCS are simultaneously introduced, wherein 0.5-1 slm of HCl, 2-5 g of TCS, and 120-180 slm of H2 are introduced.
The method of manufacturing a silicon epitaxial wafer according to claim 1, wherein in the step (2), the susceptor is cooled to 850 °C.
The method of manufacturing a silicon epitaxial wafer according to claim 1, wherein in the step (3), the baking temperature is 1150-1180 ° C, the baking time is 40 seconds, and the H 2 flow rate is 120-180 slm.
The method for fabricating a silicon epitaxial wafer according to claim 1 or 2 or 3, wherein the epitaxial growth condition of the first layer is selected to be: a baking temperature of 1150-1180 ° C, and a baking main H 2 flow rate of 120 - 180slm; first layer epitaxy, growth temperature 1100-1130 ° C, deposition rate of 0.8-1.0 μm / min; second layer epitaxial growth, temperature of 1100-1130 ° C, deposition rate of 0.4-0.6 μm / min.
The method of manufacturing a silicon epitaxial wafer according to claim 4, wherein the first layer is epitaxially grown without doping, and the second layer is doped epitaxially grown with an H2 flow rate of 120-180 slm.
The method for fabricating a silicon epitaxial wafer according to claim 4, wherein the deposition is selected by a growth temperature of 1100-1130 ° C, a growth silicon source flow rate of 2-5 g, a growth HCl flow rate of 0.5-1 slm, and a growth main H 2 flow rate. 120-180slm.
The method for fabricating a silicon epitaxial wafer according to claim 1, wherein the substrate sheet is selected by using an 8-inch heavy-doped phosphorus-silicon polished sheet, the resistivity is ≤0.001 Ω·cm, and the partial flatness of the substrate sheet is ≤1.5 m. (10mm × 10mm), silicon dioxide back sealing layer + polysilicon back sealing layer back sealing.