CN107012506B - A kind of preparation method of step-recovery diode silicon epitaxial wafer - Google Patents
A kind of preparation method of step-recovery diode silicon epitaxial wafer Download PDFInfo
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- CN107012506B CN107012506B CN201710253915.7A CN201710253915A CN107012506B CN 107012506 B CN107012506 B CN 107012506B CN 201710253915 A CN201710253915 A CN 201710253915A CN 107012506 B CN107012506 B CN 107012506B
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 61
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 61
- 239000010703 silicon Substances 0.000 title claims abstract description 61
- 238000011084 recovery Methods 0.000 title claims abstract description 18
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 239000001257 hydrogen Substances 0.000 claims abstract description 89
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 84
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 79
- 238000010926 purge Methods 0.000 claims abstract description 59
- 230000012010 growth Effects 0.000 claims abstract description 50
- 239000007789 gas Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000012535 impurity Substances 0.000 claims abstract description 22
- 238000006243 chemical reaction Methods 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 14
- 238000009792 diffusion process Methods 0.000 claims abstract description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 20
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 16
- 229910003822 SiHCl3 Inorganic materials 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 15
- 239000002994 raw material Substances 0.000 claims description 12
- SLLGVCUQYRMELA-UHFFFAOYSA-N chlorosilicon Chemical compound Cl[Si] SLLGVCUQYRMELA-UHFFFAOYSA-N 0.000 claims description 10
- 229910052757 nitrogen Inorganic materials 0.000 claims description 10
- 238000005498 polishing Methods 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 5
- -1 hydrogen Chemical class 0.000 claims description 5
- 150000002431 hydrogen Chemical class 0.000 claims description 5
- 230000006698 induction Effects 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 4
- 229910002804 graphite Inorganic materials 0.000 claims description 4
- 239000010439 graphite Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 238000007789 sealing Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 claims 4
- 239000002344 surface layer Substances 0.000 claims 1
- 230000007704 transition Effects 0.000 abstract description 26
- 238000000407 epitaxy Methods 0.000 abstract description 11
- 238000005457 optimization Methods 0.000 abstract description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 23
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 23
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 23
- 238000012360 testing method Methods 0.000 description 22
- 239000000523 sample Substances 0.000 description 9
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 6
- 229910052753 mercury Inorganic materials 0.000 description 6
- 238000005282 brightening Methods 0.000 description 4
- 238000011109 contamination Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 239000003595 mist Substances 0.000 description 4
- 238000005033 Fourier transform infrared spectroscopy Methods 0.000 description 3
- 230000003628 erosive effect Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000003892 spreading Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000002238 attenuated effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000026267 regulation of growth Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/18—Epitaxial-layer growth characterised by the substrate
- C30B25/186—Epitaxial-layer growth characterised by the substrate being specially pre-treated by, e.g. chemical or physical means
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
- C30B25/02—Epitaxial-layer growth
- C30B25/18—Epitaxial-layer growth characterised by the substrate
- C30B25/20—Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer
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- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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Abstract
The invention discloses a kind of preparation methods of step-recovery diode silicon epitaxial wafer.The preparation method overcomes the control problem of width of transition zone present in existing step-recovery diode silicon epitaxial wafer technique, using two sections of growths in epitaxial layer growth process, for a period of time using the hydrogen purge of variable-flow repeatedly first, impurity is constantly diluted and excludes epitaxial furnace reaction cavity, then low temperature bradyauxesis first segment extension, reduce the influence of gas phase auto-dope, improve the structure of transition region, then a period of time is purged again using the hydrogen of variable-flow repeatedly, then high temperature grows second segment epitaxial layer fastly, is finally reached target thickness and resistivity.By the optimization of epitaxy technique, the control under normal pressure to substrate impurity self-diffusion factor is realized, shortens the width of transition region, it is made to account for the 13%-15% of epitaxy layer thickness percentage, meets the requirement of step-recovery diode.
Description
Technical field
The present invention relates to the fabricating technology of semiconductor epitaxial material more particularly to a kind of step-recovery diode silicon
The preparation method of epitaxial wafer.
Background technique
Step-recovery diode abbreviation step pipe has forward voltage drop low, the high feature of breakdown reverse voltage, and under it
The drop time is extremely short, and forward conduction performance is also fine.Step pipe is very special in transient response, and fall time close to 0, closes
The variation of electric current is very rapidly when disconnected.Using its excellent C-V characteristic, it is whole that step pipe is mainly used for frequency multiplier circuit, ultrahigh speed pulse
Shape and generation circuit.
The characteristic of step pipe is built upon in the special distribution of PN junction impurity, and the feature in structure is in PN junction boundary
With precipitous impurity profile region, it is therefore desirable to which using high resistivity and the narrow silicon epitaxial wafer of width of transition zone is as crucial substrate
Material.The performances such as thickness, resistivity, the transition region pattern of silicon epitaxial wafer have particularly important influence to the quality of step pipe,
Highly important influence is played on the performance of the breakdown voltage of device, reverse leakage current and forward differential resistance.Wherein, made outer
The percentage range for prolonging epitaxy layer thickness shared by the width of transition zone diffuseed to form between layer and silicon monocrystalline substrate piece requires
10%-15% can seriously affect the step recovery time of device once epitaxial layer transition zone is wide.Since epitaxial layer preparation is in weight
The silicon monocrystalline substrate on piece mixed, needs to realize the deposit of the epitaxial layer of lower thickness and higher electric resistivity, therefore to auto-dope
Control proposes high requirement.There are also larger gap, systems for the width of transition zone of country's silicon epitaxial wafer and same kind of products at abroad at present
The percentage range that standby width of transition zone accounts for epitaxy layer thickness is commonly 15%-20%, is not met by device index request.
Summary of the invention
The purpose of the present invention is overcoming existing step-recovery diode silicon epitaxial wafer, existing transition region is wide in process
The control problem of degree realizes the control to self-diffusion by process optimization, obtains a kind of step-recovery diode silicon epitaxial wafer
Preparation method.Using two sections of growths in epitaxial layer growth process, for a period of time using the hydrogen purge of variable-flow repeatedly first,
Impurity is constantly diluted and excludes epitaxial furnace reaction cavity, then low temperature bradyauxesis first segment extension, reduces gas phase and mixes certainly
Miscellaneous influence improves the structure of transition region, then purges a period of time again using the hydrogen of variable-flow repeatedly, then high temperature is fast
Second segment epitaxial layer is grown, target thickness and resistivity are finally reached.To meet the requirement of step-recovery diode.
The technical solution adopted by the present invention is that: a kind of preparation method of step-recovery diode silicon epitaxial wafer, feature
It is, has the following steps:
(1), the graphite base of epitaxial furnace is performed etching first with the HCl gas of purity >=99.99%, completely removes base
Residual deposits substance on seat, etching temperature are set as 1130-1150 DEG C, and HCl gas flow is set as 1-3 L/min, and HCl is carved
The erosion time is set as 3-5 min, after the completion of etching, regrows one layer of non-impurity-doped polysilicon in base-plates surface immediately, growth is former
Material is SiHCl3, gas flow is set as 14-16 L/min, and growth time is set as 10-12 min；
(2), it is packed into silicon monocrystalline substrate piece into the base pieces of epitaxial furnace hole, successively the nitrogen using purity >=99.999%
Gas and hydrogen purge epitaxial furnace reaction cavity, gas flow are set as 290-310 L/min, and purge time is set as 10-12
min；
(3), it is polished using surface of the HCl gas to silicon monocrystalline substrate piece, HCl flow set is 1-3 L/min, is thrown
Light temperature is set as 1130-1150 DEG C, and polishing time is set as 1-3 min；
(4), variable-flow purging is carried out using hydrogen, impurity is constantly diluted and excludes to prolong furnace reaction cavity, hydrogen out
Changes in flow rate range is set as 40-400 L/min, and hydrogen flowing quantity rises to 400 L/min from 40 L/min, and the time is set as
0.5-1.0 min then carries out gas purging in the case where hydrogen flowing quantity is 400 L/min, and the time is set as 1-5 min, then will
Hydrogen flowing quantity drops to 40 L/min from 400 L/min, and the time is set as 0.5-1.0 min, is then 40 L/ in hydrogen flowing quantity
Gas purging is carried out under min, the time is set as 1-5 min, completes a variable-flow purge, carries out 2-3 unsteady flow in total
Measure purge；
(5), gaseous SiHCl is conveyed with hydrogen3For growth raw material, first segment is grown first on silicon monocrystalline substrate piece surface
Epitaxial layer, to inhibit substrate impurity self-diffusion process, hydrogen flowing quantity is set as 290-310 L/min, SiHCl3Flow set is
14-16 L/min, growth time are set as 20-30 sec, and growth temperature is set as 1000-1100oC；
(6), variable-flow purging is carried out with hydrogen again, impurity is constantly diluted and excludes to prolong out growing system, hydrogen
Changes in flow rate range is set as 40-400 L/min, and hydrogen flowing quantity rises to 400 L/min from 40 L/min, and the time is set as
0.5-1.0 min then carries out gas purging in the case where hydrogen flowing quantity is 400 L/min, and the time is set as 1-5 min, then will
Hydrogen flowing quantity drops to 40 L/min from 400 L/min, and the time is set as 0.5-1.0 min, is then 40 L/ in hydrogen flowing quantity
Gas purging is carried out under min, the time is set as 1-5 min, completes a variable-flow purge, needs to carry out 2-3 times in total
Variable-flow process；
(7), SiHCl is utilized3The growth of second segment epitaxial layer is carried out for growth raw material, growth temperature is set as 1120-
1130 DEG C, hydrogen flowing quantity is set as 290-310 L/min, SiHCl3Flow set is 25-28 L/min, when the growth of epitaxial layer
Between be set as 1min20sec-1min30sec, epitaxial furnace pedestal revolving speed is set as 4-5 r/min, the height setting of pedestal top plate
4# binding post for 40-50 mm, the heating induction coil of extension furnace apparatus is connected with 5# binding post；
(8), start to cool down after the completion of outer layer growth, hydrogen and nitrogen flow are set as 290-310 L/min, successively
Epitaxial furnace reaction cavity 10-12 min is purged, then takes out silicon epitaxial wafer from pedestal.
Epitaxial furnace used in the present invention is PE2061S type normal pressure cylinder epitaxial furnace.
The resistivity of silicon monocrystalline substrate piece of the present invention is 0.001-0.004 Ω cm, the silicon monocrystalline substrate piece back side
It is coated with the oxidation back sealing of 500 nm.
The beneficial effects of the present invention are: overcoming existing step-recovery diode silicon epitaxial wafer existing mistake in process
The control problem for crossing sector width provides a kind of preparation method of step-recovery diode silicon epitaxial wafer, this method is taken to set
The conduction type of the silicon epitaxial wafer of meter is N-type, surface-brightening, no road plan, fault, dislocation, skid wire, mist, orange peel, contamination etc.
Surface defect.The control under normal pressure to substrate impurity self-diffusion process is realized by the optimization of epitaxy technique, shortens transition
The width in area, makes it account for the percentage range 13%-15% of epitaxy layer thickness, and the use for meeting step-recovery diode is wanted
It asks.
Detailed description of the invention
Fig. 1 diffuses to form transition region shape appearance figure between the epitaxial layer and silicon monocrystalline substrate piece of embodiment 1；
Fig. 2 diffuses to form transition region shape appearance figure between the epitaxial layer and silicon monocrystalline substrate piece of embodiment 2；
Fig. 3 diffuses to form transition region shape appearance figure between the epitaxial layer and silicon monocrystalline substrate piece of embodiment 3.
Specific embodiment
Below in conjunction with attached drawing, detailed description of the preferred embodiments:
Use the thickness range of silicon epitaxial wafer prepared by this method for 2-3 μm, electrical resistivity range is 3-4 Ω cm, outside
The percentage range for prolonging epitaxy layer thickness shared by the width of transition zone diffuseed to form between layer and silicon monocrystalline substrate piece is 13%-
15%。
Embodiment 1
(1) graphite base of epitaxial furnace is performed etching first with the hydrogen chloride of purity >=99.99% (HCl) gas, completely
The residual deposits substance on pedestal is removed, etching temperature is set as 1130 DEG C, and HCl gas flow is set as 3 L/min, and HCl is carved
The erosion time is set as 3 min.It regrows one layer of non-impurity-doped polysilicon in base-plates surface immediately after the completion of etching, growth raw material is
SiHCl3, flow set is 15 L/min, and the time is set as 10 min.
(2) be packed into silicon monocrystalline substrate piece into extension furnace foundation seat piece hole, successively using purity >=99.999% nitrogen and
Hydrogen purge epitaxial furnace reaction cavity, gas flow are set as 300 L/min, and purge time is 10 min.
(3) HCl polishing is carried out to the surface of silicon monocrystalline substrate piece, HCl flow set is 1 L/min, polish temperature setting
It is 1130 DEG C, polishing time is set as 1 min.
(4) variable-flow purging is carried out using hydrogen, impurity is constantly diluted and excludes to prolong furnace reaction cavity, hydrogen stream out
Amount variation range is set as 40-400 L/min, and hydrogen flowing quantity rises to 400 L/min from 40 L/min, and the time is set as
0.5min, then hydrogen flowing quantity be 400 L/min under carry out gas purging, the time be 5 min, then by hydrogen flowing quantity from
400 L/min drop to 40 L/min, and the time is set as 0.5 min, then carry out gas in the case where hydrogen flowing quantity is 40L/min and blow
It sweeps, the time is set as 3 min, completes a variable-flow purge, carries out 3 variable-flow purges in total.
(5) gaseous SiHCl is conveyed with hydrogen3For growth raw material, first segment is grown first on silicon monocrystalline substrate piece surface
Epitaxial layer, to inhibit substrate impurity self-diffusion process.Hydrogen flowing quantity is set as 300 L/min, SiHCl3Flow set is 15 L/
Min, growth time are set as 30 sec, and growth temperature is set as 1100oC。
(6) variable-flow purging is carried out with hydrogen again, impurity is constantly diluted and excludes to prolong out growing system, hydrogen stream
Amount range is 40-400 L/min, and hydrogen flowing quantity rises to 400 L/min from 40 L/min, and the time is set as 0.5min, then
Gas purging is carried out in the case where hydrogen flowing quantity is 400 L/min, the time is 5 min, then declines hydrogen flowing quantity from 400 L/min
To 40 L/min, the time is set as 0.5 min, and gas purging, time setting are then carried out in the case where hydrogen flowing quantity is 40 L/min
For 3 min, a variable-flow purge is completed, carries out 3 variable-flow processes in total.
(7) SiHCl is utilized3The growth of second segment epitaxial layer is carried out again, and growth temperature is set as 1130 DEG C, hydrogen flowing quantity
Control is in 300 L/min, SiHCl3Flow set is 25 L/min, and the growth time of epitaxial layer is set as 1min20sec, extension
Furnace foundation seat revolving speed is set as 4r/min, and the height of pedestal top plate is set as 50mm, the 4# of the heating induction coil of extension furnace apparatus
Binding post is connected with 5# binding post.
(8) start to cool down after the completion of outer layer growth, hydrogen and nitrogen flow are set as 300 L/min, successively purged
10 min of epitaxial furnace reaction cavity, then takes out silicon epitaxial wafer from pedestal.
(9) 6700 Fourier Transform Infrared Spectrometer of Nicolet is utilized, records center point, four away from 10 mm's of edge
Position amounts to the thickness of 5 test points, obtains the thickness of silicon epitaxial wafer；Using SSM495 mercury probe C-V tester, in record
Heart point, four positions away from 10 mm of edge amount to the resistivity of 5 test points, the resistivity of silicon epitaxial wafer are obtained, wherein testing
Starting voltage is -5V, and test end voltage is -20V, and sample frequency is 2500 mv/sec, and the test preceding probe stationary time is
4.5sec, mercury area are 0.01915cm2, epitaxial layer and silicon monocrystalline substrate piece are obtained using 2000 Spreading resistance instrument of SRP
The width of the transition region diffuseed to form, wherein test stepping is 0.1 μm.
The conduction type of epitaxial layer made from embodiment 1 be N-type, silicon epitaxial wafer surface-brightening, no road plan, fault, dislocation,
The surface defects such as skid wire, mist, orange peel, contamination, silicon epitaxial wafer thickness value are 2.6 μm, and resistivity value is 3.2 Ω cm, transition region
Width is 0.35 μm, accounts for the 13.6% of epitaxy layer thickness percentage, (the depth indicated in figure that test results are shown in figure 1 for transition region
For epitaxial layer to longitudinal direction extension until substrate, referred to as depth since surface；Preamble is worked as in " ■ " expression in figure
The test point obtained under for 0.1 μm).
Embodiment 2
(1) graphite base of epitaxial furnace is performed etching first with the hydrogen chloride of purity >=99.99% (HCl) gas, completely
The residual deposits substance on pedestal is removed, etching temperature is set as 1130 DEG C, and HCl gas flow is set as 1 L/min, and HCl is carved
The erosion time is set as 3 min.It regrows one layer of non-impurity-doped polysilicon in base-plates surface immediately after the completion of etching, growth raw material is
SiHCl3, flow set is 14 L/min, and the time is set as 12 min.
(2) be packed into silicon monocrystalline substrate piece into extension furnace foundation seat piece hole, successively using purity >=99.999% nitrogen and
Hydrogen purge epitaxial furnace reaction cavity, gas flow are set as 300 L/min, and purge time is 12 min.
(3) HCl polishing is carried out to the surface of silicon monocrystalline substrate piece, HCl flow set is 1 L/min, polish temperature setting
It is 1130 DEG C, polishing time is set as 1 min.
(4) variable-flow purging is carried out using hydrogen, impurity is constantly diluted and excludes to prolong out growing system, gas flow
Range is 40-400 L/min, and hydrogen flowing quantity rises to 400 L/min from 40 L/min, and the time is set as 1.0 min, then exists
Hydrogen flowing quantity is that gas purging is carried out under 400 L/min, and the time is 3 min, then drops to hydrogen flowing quantity from 400 L/min
40 L/min, fall time are set as 1.0 min, then carry out gas purging, time 1 in the case where hydrogen flowing quantity is 40 L/min
Min completes a variable-flow purge, carries out 3 variable-flow purges in total.
(5) gaseous SiHCl is conveyed with hydrogen3For growth raw material, first segment is grown first on silicon monocrystalline substrate piece surface
Epitaxial layer, to inhibit self-diffusion process.Hydrogen flowing quantity is set as 290 L/min, SiHCl3Flow set is 14 L/min, growth
Time is set as 20 sec, and growth temperature is set as 1100oC。
(6) variable-flow purge is carried out with hydrogen again, impurity is constantly diluted and excludes to prolong furnace reaction cavity out,
The use of hydrogen flowing quantity range is 40-400 L/min, hydrogen flowing quantity is then risen into 400 L/min from 40 L/min, the time sets
It is set to 0.5 min, then carries out gas purging in the case where hydrogen flowing quantity is 400 L/min, the time is 3 min, then by hydrogen stream
Amount drops to 40 L/min from 400 L/min, and the time is set as 0.5 min, then carries out in the case where hydrogen flowing quantity is 40 L/min
Gas purging, time are 1 min, complete a variable-flow purge, carry out 3 variable-flow processes in total.
(7) SiHCl is utilized3The growth of second segment epitaxial layer is carried out again, and growth temperature is set as 1120 DEG C, hydrogen flowing quantity
It is set as 300 L/min, SiHCl3Flow set is 25 L/min, and the growth time of epitaxial layer is set as 1min30sec, extension
Furnace foundation seat revolving speed is set as 5 r/min, and the height of pedestal top plate is set as 50 mm, the heating induction coil of extension furnace apparatus
4# binding post is connected with 5# binding post.
(8) start to cool down after the completion of outer layer growth, hydrogen and nitrogen flow are set as 300 L/min, successively purged
10 min of epitaxial furnace reaction cavity, then takes out silicon epitaxial wafer from pedestal.
(9) 6700 Fourier Transform Infrared Spectrometer of Nicolet is utilized, records center point, four away from 10 mm's of edge
Position amounts to the thickness of 5 test points, to obtain the thickness of silicon epitaxial wafer；Using SSM495 mercury probe C-V tester, survey
Examination starting voltage is -5V, and test end voltage is -20V, and sample frequency is 2500 mv/sec, and the test preceding probe stationary time is
4.5sec, mercury area are 0.01915cm2, records center point, four positions away from 10 mm of edge amount to the electricity of 5 test points
Resistance rate obtains epitaxial layer using 2000 Spreading resistance instrument of SRP and silicon single crystal serves as a contrast to obtain the resistivity of silicon epitaxial wafer
The width for the transition region that egative film diffuses to form, wherein test stepping is set as 0.1 μm.
The conduction type of silicon epitaxial wafer made from embodiment 2 is N-type, surface-brightening, no road plan, fault, dislocation, sliding
The surface defects such as line, mist, orange peel, contamination, thickness value are 2.5 μm, and resistivity value is 3.2 Ω cm, width of transition zone 0.35
μm, account for the 14.0% of epitaxy layer thickness percentage, test results are shown in figure 2 for transition region (depth indicated in figure be epitaxial layer from
Surface starts to be extended to longitudinal direction until substrate, referred to as depth；" ■ " in figure is indicated when preamble is under for 0.1 μm
The test point of acquisition).
Embodiment 3
(1) extension furnace foundation seat is performed etching first with the hydrogen chloride of purity >=99.99% (HCl) gas, completely removes base
Residual deposits substance on seat, etching temperature are set as 1130 DEG C, and HCl gas flow is set as 3 L/min, HCl etch period
It is set as 3 min.It regrows one layer of non-impurity-doped polysilicon in base-plates surface immediately after the completion of etching, growth raw material is
SiHCl3, flow set is 15 L/min, and growth time is set as 10 min.
(2) be packed into silicon monocrystalline substrate piece into extension furnace foundation seat piece hole, successively using purity >=99.999% nitrogen and
Hydrogen purge cavity, gas flow are set as 300 L/min, and purge time is 10 min.
(3) HCl polishing is carried out to the surface of silicon monocrystalline substrate piece, HCl flow set is 1 L/min, polish temperature setting
It is 1130 DEG C, polishing time is set as 3 min.
(4) variable-flow purging is carried out using hydrogen, impurity is constantly diluted and excludes to prolong furnace reaction cavity, hydrogen stream out
Amount range is 40-400 L/min, and hydrogen flowing quantity rises to 400 L/min from 40 L/min, and the time is set as 0.5 min, then
Gas purging is carried out in the case where hydrogen flowing quantity is 400 L/min, the time is 3 min, then declines hydrogen flowing quantity from 400 L/min
To 40 L/min, the time is set as 0.5 min, then carries out gas purging, time 3 in the case where hydrogen flowing quantity is 40 L/min
Min completes a variable-flow purge, carries out 2 variable-flow purges in total.
(5) gaseous SiHCl is conveyed with hydrogen3For growth raw material, in the surface of silicon monocrystalline substrate piece growth regulation one first
Section epitaxial layer, to inhibit substrate impurity self-diffusion process.Hydrogen flowing quantity is set as 300 L/min, SiHCl3Flow set is 15
L/min, growth time are set as 30 sec, and growth temperature is set as 1000oC。
(6) variable-flow purging is carried out with hydrogen again, impurity is constantly diluted and excludes to prolong furnace reaction cavity, hydrogen out
Range of flow is set as 40-400 L/min, and hydrogen flowing quantity rises to 400 L/min from 40 L/min, and the time is set as 0.5
Min then carries out gas purging in the case where hydrogen flowing quantity is 400 L/min, and the time is set as 3 min, then by hydrogen flowing quantity from
400 L/min drop to 40 L/min, and the time is set as 0.5 min, then carry out gas in the case where hydrogen flowing quantity is 40 L/min
Purging, time are set as 3 min, complete a variable-flow purge, carry out 2 variable-flow purges in total.
(7) SiHCl is utilized3The growth of second segment epitaxial layer is carried out for growth raw material, growth temperature is set as 1130 DEG C, hydrogen
Throughput control is 300 L/min, SiHCl3Flow set is 25 L/min, and the growth time of epitaxial layer is set as
1min20sec, epitaxial furnace pedestal revolving speed are set as 5 r/min, and the height of pedestal top plate is set as 50 mm, extension furnace apparatus
The 4# binding post of heating induction coil is connected with 5# binding post.
(8) start to cool down after the completion of outer layer growth, hydrogen and nitrogen flow are set as 300 L/min, successively purged
10 min of epitaxial furnace reaction cavity, then takes out silicon epitaxial wafer from pedestal.
(9) 6700 Fourier Transform Infrared Spectrometer of Nicolet is utilized, records center point, four away from 10 mm's of edge
Position, amounts to the thickness of 5 test points, to obtain the thickness of silicon epitaxial wafer, using SSM495 mercury probe C-V tester, surveys
Examination starting voltage is -5V, and test end voltage is -20V, and sample frequency is 2500 mv/sec, and the test preceding probe stationary time is
4.5sec, mercury area are 0.01915cm2, records center point, four positions away from 10 mm of edge amount to the resistance of 5 test points
Rate obtains the resistivity of silicon epitaxial wafer, obtains silicon epitaxial wafer and silicon monocrystalline substrate piece using 2000 Spreading resistance instrument of SRP
The width of the transition region diffuseed to form, wherein test stepping is set as 0.1 μm.
The conduction type of silicon epitaxial wafer made from embodiment 3 is N-type, surface-brightening, no road plan, fault, dislocation, sliding
The surface defects such as line, mist, orange peel, contamination, thickness value are 2.7 μm, and resistivity value is 3.4 Ω cm, and width of transition zone is 0.4 μm,
The 14.8% of epitaxy layer thickness percentage is accounted for, test results are shown in figure 3 for transition region, and (depth indicated in figure is epitaxial layer from table
Face starts to be extended to longitudinal direction until substrate, referred to as depth；" ■ " in figure indicates to obtain when preamble under for 0.1 μm
The test point obtained).
Compared with embodiment 2, embodiment 3, embodiment 1 is all made of 3 variable-flow purges before growing every section of epitaxial layer,
And longest purge time is used in the case where hydrogen flowing quantity is the relatively air volume under 400L/min, preferably impurity can be diluted
And exclude to prolong furnace reaction cavity out, negative factor caused by such substrate impurity self-diffusion can be attenuated to minimum, therefore institute
It is minimum that width of transition zone obtained accounts for epitaxy layer thickness percentage.Embodiment 1 is highly preferred embodiment of the present invention.
Claims (3)
1. a kind of preparation method of step-recovery diode silicon epitaxial wafer, which is characterized in that have the following steps:
(1), the graphite base of epitaxial furnace is performed etching first with the HCl gas of purity >=99.99%, is completely removed on pedestal
Residual deposits substance, etching temperature is set as 1130-1150 DEG C, and HCl gas flow is set as 1-3 L/min, when HCl is etched
Between be set as 3-5 min, after the completion of etching, regrow one layer of non-impurity-doped polysilicon in base-plates surface immediately, growth raw material is
SiHCl3, gas flow is set as 14-16 L/min, and growth time is set as 10-12 min；
(2), be packed into silicon monocrystalline substrate piece into the base pieces of epitaxial furnace hole, successively using purity >=99.999% nitrogen and
Hydrogen purge epitaxial furnace reaction cavity, gas flow are set as 290-310 L/min, and purge time is set as 10-12 min；
(3), it is polished using surface of the HCl gas to silicon monocrystalline substrate piece, HCl flow set is 1L/min, polish temperature
It is set as 1130 DEG C, polishing time is set as 1min；
(4), variable-flow purging is carried out using hydrogen, impurity is constantly diluted and excludes to prolong furnace reaction cavity, hydrogen flowing quantity out
Variation range is set as 40-400 L/min, and hydrogen flowing quantity rises to 400 L/min from 40 L/min, and the time is set as 0.5
Min then carries out gas purging in the case where hydrogen flowing quantity is 400 L/min, and the time is set as 5 min, then by hydrogen flowing quantity from
400 L/min drop to 40 L/min, and the time is set as 0.5min, then carry out gas in the case where hydrogen flowing quantity is 40 L/min and blow
It sweeps, the time is set as 3min, completes a variable-flow purge, carries out 3 variable-flow purges in total；
(5), gaseous SiHCl is conveyed with hydrogen3For growth raw material, first segment extension is grown first on silicon monocrystalline substrate piece surface
Layer, to inhibit substrate impurity self-diffusion process, hydrogen flowing quantity is set as 290-310 L/min, SiHCl3Flow set is 14-16
L/min, growth time are set as 20-30 sec, and growth temperature is set as 1100 DEG C；
(6), variable-flow purging is carried out with hydrogen again, impurity is constantly diluted and excludes to prolong out growing system, hydrogen flowing quantity
Variation range is set as 40-400 L/min, and hydrogen flowing quantity rises to 400 L/min from 40 L/min, and the time is set as
0.5min then carries out gas purging in the case where hydrogen flowing quantity is 400 L/min, and the time is set as 5 min, then by hydrogen flowing quantity
40 L/min are dropped to from 400 L/min, the time is set as 0.5min, then carries out gas in the case where hydrogen flowing quantity is 40 L/min
Purging, time are set as 3min, complete a variable-flow purge, need to carry out 3 variable-flow processes in total；
(7), SiHCl is utilized3The growth of second segment epitaxial layer is carried out for growth raw material, growth temperature is set as 1130 DEG C, hydrogen stream
Amount is set as 290-310 L/min, SiHCl3Flow set is 25-28 L/min, and the growth time of epitaxial layer is set as
1min20sec-1min30sec, epitaxial furnace pedestal revolving speed are set as 4-5 r/min, and the height of pedestal top plate is set as 40-50
The 4# binding post of mm, the heating induction coil of extension furnace apparatus are connected with 5# binding post；
(8), start to cool down after the completion of outer layer growth, hydrogen and nitrogen flow are set as 290-310 L/min, successively purged
Epitaxial furnace reaction cavity 10-12 min, then takes out silicon epitaxial wafer from pedestal.
2. a kind of preparation method of step-recovery diode silicon epitaxial wafer according to claim 1, which is characterized in that institute
Epitaxial furnace is PE2061S type normal pressure cylinder epitaxial furnace.
3. a kind of preparation method of step-recovery diode silicon epitaxial wafer according to claim 1, which is characterized in that silicon
The resistivity 0.001-0.004 Ω cm of single crystalline substrate piece, the back side are coated with the oxidation back sealing of 500 nm.
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| CN109003885A (en) * | 2018-07-04 | 2018-12-14 | 上海晶盟硅材料有限公司 | Production method, epitaxial wafer and the semiconductor devices of twin polishing epitaxial wafer |
| CN110379704B (en) * | 2019-07-19 | 2021-05-28 | 中国电子科技集团公司第四十六研究所 | Preparation method of silicon epitaxial wafer for high-voltage power device |
| CN111463117B (en) * | 2020-04-27 | 2022-05-06 | 中国电子科技集团公司第四十六研究所 | Preparation method of silicon epitaxial wafer for high-frequency device |
| CN113737276B (en) * | 2021-08-30 | 2024-04-16 | 中国电子科技集团公司第四十六研究所 | Method for improving silicon epitaxial growth rate |
| CN113737151B (en) * | 2021-08-30 | 2023-06-27 | 中国电子科技集团公司第四十六研究所 | Preparation method of silicon epitaxial wafer for PIN switching device |
| CN114628243A (en) * | 2022-03-10 | 2022-06-14 | 河北普兴电子科技股份有限公司 | Preparation method of double-layer silicon epitaxial wafer for fast recovery epitaxial diode |
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Application publication date: 20170804 Assignee: CLP Jinghua (Tianjin) semiconductor materials Co.,Ltd. Assignor: CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION NO.46 Research Institute Contract record no.: X2024980004262 Denomination of invention: A preparation method of silicon epitaxial wafers for step recovery diodes Granted publication date: 20190524 License type: Common License Record date: 20240415 |