CN115094515A - Process for improving local flatness of logic epitaxial product - Google Patents

Process for improving local flatness of logic epitaxial product Download PDF

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Publication number
CN115094515A
CN115094515A CN202210616997.8A CN202210616997A CN115094515A CN 115094515 A CN115094515 A CN 115094515A CN 202210616997 A CN202210616997 A CN 202210616997A CN 115094515 A CN115094515 A CN 115094515A
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China
Prior art keywords
epitaxial
logic
contact position
local flatness
graphite base
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Pending
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CN202210616997.8A
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Chinese (zh)
Inventor
陆波
杨振域
郑岳亮
王瀚
王超
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Zhonghuan Advanced Semiconductor Materials Co Ltd
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Zhonghuan Advanced Semiconductor Materials Co Ltd
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Priority to CN202210616997.8A priority Critical patent/CN115094515A/en
Publication of CN115094515A publication Critical patent/CN115094515A/en
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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/10—Heating of the reaction chamber or the substrate
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
    • C30B23/02—Epitaxial-layer growth
    • C30B23/025—Epitaxial-layer growth characterised by the substrate
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
    • C30B23/02—Epitaxial-layer growth
    • C30B23/06—Heating of the deposition chamber, the substrate or the materials to be evaporated
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C30B25/186—Epitaxial-layer growth characterised by the substrate being specially pre-treated by, e.g. chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02634—Homoepitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments

Abstract

The invention discloses a process for improving the local flatness of a logic epitaxial product, S1, reducing the temperature of a graphite base in the epitaxial growth process, thereby inhibiting the epitaxial growth rate of the contact position of the graphite base and a silicon wafer; s2, carrying out silicon coating treatment on the graphite base before epitaxy, and reducing the temperature field difference of the contact position; the thickness of the silicon coating is increased to 2-3 μm, so that the heat conduction coefficient of the graphite base can be further reduced, and the temperature field difference between the silicon wafer and the contact position is reduced. The invention reduces the temperature field difference of the contact position of the silicon wafer and the base, so that the silicon wafer grows more uniformly as a whole, the process is simple, the repeatability is high, the local flatness requirements of 28nm and 55nm epitaxial products are met, and the method can be used as the process basis for optimizing 14nm products.

Description

Process for improving local flatness of logic epitaxial product
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a process for improving local flatness of a logic epitaxial product.
Background
A12-inch logic epitaxial product enters a stage of small line width, and the smaller line width has higher requirements on the surface geometric appearance of an epitaxial wafer, particularly the local flatness. Excessive local flatness can affect device processing, causing device failure and affecting yield. The higher thickness of the edge film of the epitaxial product than other positions is a main factor causing the excessive local flatness of the product.
Disclosure of Invention
The invention provides a process for improving local flatness of a logic epitaxial product.
A process for improving local flatness of a logic epitaxial product comprises the following steps:
s1, reducing the temperature of the graphite base in the epitaxial growth process, thereby inhibiting the epitaxial growth rate of the contact position of the graphite base and the silicon wafer;
s2, carrying out silicon coating treatment on the graphite base before epitaxy, and reducing the temperature field difference of the contact position; the thickness of the silicon-coated substrate is increased to 2-3 μm, so that the heat conduction coefficient of the graphite base can be further reduced, and the temperature field difference between the silicon wafer and the contact position is reduced.
Preferably, the heating power in the lower part of the reaction chamber before the adjustment is 58%.
Preferably, the heating power of the lower part of the reaction chamber after adjustment is 52%.
Preferably, the silicon-on-silicon has a thickness of 2 μm.
Preferably, the silicon-coated layer has a thickness of 3 μm.
Compared with the prior art, the invention has the beneficial effects that: the temperature field difference of the contact position of the silicon wafer and the base is reduced, so that the silicon wafer grows more uniformly as a whole, the process is simple, the repeatability is high, the local flatness requirements of 28nm and 55nm epitaxial products are met, and the method can be used as a process basis for optimizing 14nm products.
Drawings
FIG. 1 is a schematic view of a silicon wafer in contact with a susceptor.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below.
A process for improving local flatness of a logic epitaxial product comprises the following steps:
s1, reducing the temperature of the graphite base 100 in the epitaxial growth process, thereby inhibiting the epitaxial growth rate of the contact position of the graphite base 100 and the silicon wafer 200;
the contact position between the silicon wafer and the graphite base is shown in fig. 1, and because the heat conduction coefficient of the graphite base is different from that of the silicon wafer, temperature field distribution difference is generated at the contact position, so that the thickness difference is caused.
The graphite base has higher temperature, the temperature field difference of the contact position is large, the graphite base has low temperature, and the temperature field difference of the contact position is small. The heating power of the lower part of the reaction chamber before adjustment was 58%, and the heating power of the lower part of the reaction chamber after adjustment was 52%. The difference of the temperature field distribution is reduced, so that the difference of the thickness of the epitaxial layer between the position and other positions is reduced, and the local flatness of the epitaxial product is optimized.
S2, carrying out silicon-coating treatment on the graphite base before epitaxy, and reducing the temperature field difference of the contact position; the thickness of the silicon-coated substrate is increased to 2-3 μm, so that the heat conduction coefficient of the graphite base can be further reduced, and the temperature field difference between the silicon wafer and the contact position is reduced.
The invention reduces the temperature field difference of the contact position of the silicon wafer and the base, so that the silicon wafer grows more uniformly as a whole, the process is simple, the repeatability is high, the local flatness requirements of 28nm and 55nm epitaxial products are met, and the method can be used as the process basis for optimizing 14nm products.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described in the foregoing embodiments, or equivalents may be substituted for elements thereof.

Claims (5)

1. A process for improving local flatness of a logic epitaxial product is characterized by comprising the following steps:
s1, reducing the temperature of the graphite base in the epitaxial growth process, thereby inhibiting the epitaxial growth rate of the contact position of the graphite base and the silicon wafer;
s2, carrying out silicon coating treatment on the graphite base before epitaxy, and reducing the temperature field difference of the contact position; the thickness of the silicon-coated substrate is increased to 2-3 μm, so that the heat conduction coefficient of the graphite base can be further reduced, and the temperature field difference between the silicon wafer and the contact position is reduced.
2. The process for improving local flatness of a logic epitaxial product according to claim 1, wherein: the heating power in the lower part of the reaction chamber before the adjustment was 58%.
3. The process for improving local flatness of a logic epitaxial product according to claim 1, wherein: the heating power in the lower part of the reaction chamber after adjustment is 52%.
4. The process for improving local flatness of a logic epitaxial product according to claim 1, wherein: the thickness of the silicon-clad layer was 2 μm.
5. The process for improving local flatness of a logic epitaxial product according to claim 1, wherein: the thickness of the silicon-coated film was 3 μm.
CN202210616997.8A 2022-06-01 2022-06-01 Process for improving local flatness of logic epitaxial product Pending CN115094515A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116971025A (en) * 2023-06-09 2023-10-31 浙江丽水中欣晶圆半导体科技有限公司 Method for improving epitaxial deformation value of back-sealed substrate slice

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106057650A (en) * 2016-08-01 2016-10-26 中国电子科技集团公司第四十六研究所 Preparation method of silicon epitaxial wafer for LDMOS transistor
CN106803480A (en) * 2017-02-14 2017-06-06 河北普兴电子科技股份有限公司 The application of the method and epitaxial wafer of P+ Growns N silicon epitaxial wafers under normal pressure
CN108728898A (en) * 2017-04-24 2018-11-02 上海新昇半导体科技有限公司 A kind of epitaxial furnace silicon chip pedestal
CN109545653A (en) * 2017-09-22 2019-03-29 上海新昇半导体科技有限公司 Improve the method for epitaxial silicon chip edge flatness
CN111996591A (en) * 2020-08-26 2020-11-27 西安奕斯伟硅片技术有限公司 Base, device and method for epitaxial growth of silicon wafer
CN114188258A (en) * 2022-02-17 2022-03-15 西安奕斯伟材料科技有限公司 Silicon wafer substrate conveying device and method for improving flatness of epitaxial wafer

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106057650A (en) * 2016-08-01 2016-10-26 中国电子科技集团公司第四十六研究所 Preparation method of silicon epitaxial wafer for LDMOS transistor
CN106803480A (en) * 2017-02-14 2017-06-06 河北普兴电子科技股份有限公司 The application of the method and epitaxial wafer of P+ Growns N silicon epitaxial wafers under normal pressure
CN108728898A (en) * 2017-04-24 2018-11-02 上海新昇半导体科技有限公司 A kind of epitaxial furnace silicon chip pedestal
CN109545653A (en) * 2017-09-22 2019-03-29 上海新昇半导体科技有限公司 Improve the method for epitaxial silicon chip edge flatness
CN111996591A (en) * 2020-08-26 2020-11-27 西安奕斯伟硅片技术有限公司 Base, device and method for epitaxial growth of silicon wafer
CN114188258A (en) * 2022-02-17 2022-03-15 西安奕斯伟材料科技有限公司 Silicon wafer substrate conveying device and method for improving flatness of epitaxial wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116971025A (en) * 2023-06-09 2023-10-31 浙江丽水中欣晶圆半导体科技有限公司 Method for improving epitaxial deformation value of back-sealed substrate slice

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