JPH0482052B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, particularly a method for manufacturing an integrated circuit device, in which elements having different characteristics are monolithically formed on a semiconductor substrate of a certain conductivity type.

[Technical background of the invention]

Recently, the DOPOS structure has been widely used as the emitter structure of bipolar transistors. this
In the DOPOS method, a method is adopted in which a polycrystalline silicon layer containing a high concentration of impurity elements is deposited on the emitter forming portion and then the emitter region is obtained by thermal diffusion of the impurity elements.

This method is widely used because it has the advantage that device characteristics can be controlled by the type and amount of impurities added to polycrystalline silicon, the thickness of the polycrystalline silicon layer, and the temperature and time of thermal diffusion. is the current situation.

A bipolar transistor to which this DOPOS method is applied will be explained with reference to FIG. A silicon semiconductor substrate 30 exhibiting P conductivity type is prepared, and an N ⁺ conductivity type region 31 is formed on its surface, and this region functions as a buried region of a bipolar transistor to be described later. A vapor phase epitaxial layer 32 is deposited on the P conductivity type silicon semiconductor substrate 30 in which the N ⁺ conductivity type region 31 is formed, and then P is introduced into a predetermined position by ion implantation to form an N-well layer.

Although the steps are different, after the vapor phase epitaxial layer is formed, a field oxide layer 34 is provided by a conventionally known selective oxidation method. This N-well layer 33
After coating the surface with a thin silicon oxide layer 35, B ions are implanted from above this oxide layer 35 to form the base region 3.
6 is formed, and an emitter region 3 is formed in this oxide layer 35.
An impurity-containing polycrystalline silicon layer 39 is formed only in this opening for the emitter region.
Deposit. This impurity containing P is introduced into the base region 36 to form an emitter region 37.
On the other hand, an opening is also provided in the field oxide layer 34 formed by the selective oxidation method, and an N ⁺ region 41 is formed therein by introducing P to function as a collector contact. Further, the base contact 38 is formed as a P ⁺ type region by high concentration diffusion of B. The collector contact 41 and the base contact 38 are made of conductive metal Al.
was used to manufacture bipolar transistors by depositing them as respective electrodes.

[Problems with background technology]

The technique of forming a bipolar transistor, especially an emitter region, using this impurity-containing polycrystalline silicon layer is extremely inconvenient for forming elements with different characteristics. That is, in order to obtain desired characteristics, the thickness of the polycrystalline silicon layer and the type and amount of added impurities must be changed. Therefore, many difficulties arise in the manufacture of integrated circuit devices, such as an increase in the number of manufacturing steps, an accompanying increase in manufacturing costs, and an increase in the number of man-hours that causes a decrease in yield.

[Purpose of the invention]

The present invention provides a novel method for manufacturing a semiconductor device that eliminates the above-mentioned difficulties, and in particular allows elements with different characteristics to be formed monolithically and simultaneously on a semiconductor substrate.

[Summary of the invention]

In order to achieve the above object, the present invention provides an impurity introduction opening in a thin insulating layer deposited on a semiconductor substrate, and introduces the impurity in the lateral direction of the polycrystalline layer deposited there, that is, in the direction along the semiconductor substrate surface. We adopted a method in which P is diffused and controlled by silicon oxide provided in the polycrystalline layer facing the opening. Among the highly versatile impurities, P has the fastest diffusion rate in polycrystalline silicon. Use as an impurity.

[Embodiments of the invention]

The present invention will be explained in detail with reference to FIGS. 1A to 1E.

As the surface concentration showing P conductivity type, B is approximately
A semiconductor substrate 1 containing 10 ¹⁴ atoms/cc is prepared, and an N ⁺ region 2 which functions as a buried region of a bipolar transistor to be described later is filled with 5×10 ¹⁹ atoms/cc.
Formed by degree sb. A P-type epitaxial layer 3 containing about 10 ¹⁵ atoms/cc of B is deposited on this semiconductor substrate 1, and a field insulating layer 4 with a thickness of 8000 Å is formed thereon by a known selective oxidation method or thermal oxidation method.

Next, the field insulator layer 4 is placed at the location where the element is to be formed.
An opening is made by etching the exposed epitaxial layer, and P ions are implanted at approximately 10 ¹⁶ atoms/cc into the exposed epitaxial layer.
-Well regions 5, 5 are formed, and oxide films 6, 6 of approximately several hundred Å thick are formed on their surfaces. The cross-sectional structure at this point is shown in FIG. 1A. Although the collector contact 11 is shown in this figure, it may be formed between the steps described later. Its surface concentration is
This is an N ⁺ region of about 10 to ²⁰ atoms/cc.

Next, B is introduced through the thin oxide films 6, 6.
Ions are implanted under the conditions of 35 KeV4.9×10 ¹³ cm ⁻² and further heat treated at 900° C. in an N ⁺ atmosphere to form base regions 7 and 7, and the N-well region functions as a collector of a bipolar transistor.

Openings for the emitter region and the base contact are provided in the oxide films 6, 6. First, the openings 8, 8 for the emitter region are formed by an etching method, and then polycrystalline silicon is formed on the semiconductor substrate 1 having these openings. layer 10 about 3500
As a result, the field insulator layer 4 and the thin oxide films 6, 6 are also laminated.

Further, on this polycrystalline silicon layer 10, a silicon dioxide layer 15 having a thickness of about 6000 Å is deposited by the CVD method as shown in FIG. Next, the polycrystalline silicon layers 10 and 1 exposed around the patterned silicon dioxide layer, that is, the silicon oxide layer 15 and 15 are
P is introduced into the openings 8, 8 by ion implantation or from POCl ₃ and emitter regions 12, 12 are provided in the exposed base regions 7, 7.
The surface concentration of these emitter regions 12, 12 is approximately
10 ^{to 20} atoms/cc, and its cross-sectional view is shown in FIG. 1C. When introducing this P, silicon oxide layers 15,1
The amount of introduction is controlled by the area of 5, that is,
If the bottom area of the silicon oxide layers 15, 15 is larger than the area of the openings 8, 8, the amount introduced will be small, and vice versa, the amount introduced will be large, and the resulting emitter region will be
xj becomes large when the amount introduced is large. However, in FIG. 1D, for example, if the opening 8 is provided with a so-called taper, the amount of P introduced increases.
It is also possible to adjust the amount introduced depending on the conditions.

After introducing this P, as shown in FIG. 1D, in order to use the polycrystalline silicon layer 10 stacked facing the emitter regions 12, 12 as an emitter electrode, the remaining parts are melted away and the exposed thin silicon oxide layer is used as a base. Contact openings 9, 9 are provided, and B is diffused therein to provide P ⁺ conductivity type regions 13, 13. Further, a conductive metal Al is deposited on the base contact region and the N ⁺ conductivity type regions 11 for collector contact to form a base electrode and a collector electrode (not shown), thereby forming an integrated circuit device having a bipolar transistor.

〔Effect of the invention〕

The present invention utilizes the phenomenon that the diffusion rate of P in polycrystalline silicon is extremely high, and since the polycrystalline silicon at the position where the emitter region is planned to be formed is covered with a silicon oxide layer, it is possible to Thus, the emitter region is formed by being introduced into the opening formed in the thin oxide film on the P base region. Moreover,
The amount introduced depends on the area of the silicon oxide layer, and can also be adjusted by the taper provided in the opening.

Since bipolar transistors having different electrical characteristics can be formed simultaneously on the same substrate, the degree of freedom in integrated circuit design can be increased, and an integrated circuit with better performance can be obtained.

[Brief explanation of drawings]

FIGS. 1A to 1E are views showing the cross-sectional structure of the present invention in the order of steps, and FIG. 2 is a cross-sectional view showing a part of the conventional process.

Claims (1)

[Claims] 1. A step of forming a plurality of island regions made of a semiconductor layer of a first conductivity type, a step of covering the island regions with a new thin insulating layer, and a step of diffusing a first impurity through the thin insulating layer. forming a region of a second conductivity type; providing an opening in the thin insulating layer; depositing a non-doped polycrystalline silicon layer over the thin insulating layer; and forming a non-doped polycrystalline silicon layer opposite to the opening. When forming a silicon oxide layer on a crystalline silicon layer, forming the area of the silicon oxide layer in an arbitrary island region to be different from the area of other silicon oxide layers, and the exposed surface of the non-doped polycrystalline silicon. A method of manufacturing a semiconductor device, comprising the step of: introducing a second impurity into a region of a second conductivity type located in the opening to form a region of a first conductivity type.