JPH0481871B2 - - Google Patents
Info
- Publication number
- JPH0481871B2 JPH0481871B2 JP58248509A JP24850983A JPH0481871B2 JP H0481871 B2 JPH0481871 B2 JP H0481871B2 JP 58248509 A JP58248509 A JP 58248509A JP 24850983 A JP24850983 A JP 24850983A JP H0481871 B2 JPH0481871 B2 JP H0481871B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- conductivity type
- semiconductor
- semiconductor region
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 22
- 239000012535 impurity Substances 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 206010034972 Photosensitivity reaction Diseases 0.000 description 5
- 239000000969 carrier Substances 0.000 description 5
- 238000000605 extraction Methods 0.000 description 5
- 230000036211 photosensitivity Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 230000031700 light absorption Effects 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000007733 ion plating Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/103—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PN homojunction type
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Light Receiving Elements (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、光電変換素子のスイツチング速度を
改良した半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device in which the switching speed of a photoelectric conversion element is improved.
従来、半導体装置例えばNPNホトトランジス
タとしては、第１図ａ〜ｃに示すものが知られて
いる。図中の１は、Ｎ型のシリコン基板である。
この基板１の表面には、P+型のベース領域２が
設けられている。このベース領域２表面には、前
記基板１、ベース領域２と受光素子を構成する
N+型のエミツタ領域３が設けられている。前記
基板１上には絶縁膜４が設けられており、該絶縁
膜４のベース領域２、エミツタ領域３に対応する
部分には夫々電極取出し部５1，５2が設けられて
いる。この電極取出し部５1，５2には夫々Al取出
し電極６1，６2が設けられている。また、従来、
上記と異なる構造のNPNホトトランジスタとし
て、第２図ａ〜ｃに示す如く、P+型のベース領
域７，７を離隔して設け、このベース領域７，７
相互間の表面に高濃度のP++型のベース受光部領
域８を設けたものが知られている。前述した２種
のNPNトランジスタは、いずれもベース面積を
広くして光吸収時のキヤリアの発生を多くし、光
感度が高いのを特徴とするものである。
2. Description of the Related Art Conventionally, semiconductor devices such as NPN phototransistors shown in FIGS. 1a to 1c are known. 1 in the figure is an N-type silicon substrate.
A P + type base region 2 is provided on the surface of this substrate 1 . On the surface of this base region 2, the substrate 1, the base region 2, and a light receiving element are formed.
An N + type emitter region 3 is provided. An insulating film 4 is provided on the substrate 1, and electrode lead-out portions 5 1 and 5 2 are provided in portions of the insulating film 4 corresponding to the base region 2 and emitter region 3, respectively. Al extraction electrodes 6 1 and 6 2 are provided in the electrode extraction portions 5 1 and 5 2 , respectively. Also, conventionally,
As an NPN phototransistor having a structure different from that described above, as shown in FIGS .
It is known that a highly concentrated P ++ type base light receiving region 8 is provided on the surface between them. The two types of NPN transistors mentioned above are both characterized by having a wide base area to increase the generation of carriers when absorbing light, resulting in high photosensitivity.
しかしながら、従来のNPNホトトランジスタ
によれば、ベース領域が広いため、光吸収時のキ
ヤリアの発生が多く、入射光が遮断状態になる
と、このキヤリアが再結合するまでに時間がかか
り、ターンオフ時間が長くなるという欠点があつ
た。このターンオフの時間は、短くてもスイツチ
ングスピードは15〜20μ秒が限界であつた。一
方、受光部であるベース領域の面積を小さく、シ
リコン基板の比抵抗を下げるとスイツチングスピ
ードは速くなるが、今度は光感度や耐圧が低下す
るなどの問題点があつた。 However, since the conventional NPN phototransistor has a wide base area, many carriers are generated when light is absorbed, and when the incident light is blocked, it takes time for these carriers to recombine, resulting in a turn-off time. It had the disadvantage of being long. Even if this turn-off time was short, the switching speed was limited to 15 to 20 microseconds. On the other hand, reducing the area of the base region, which is the light receiving part, and lowering the specific resistance of the silicon substrate increases the switching speed, but this results in problems such as a decrease in photosensitivity and breakdown voltage.
このようなことから、第３図ａ〜ｃ及び第４図
ａ〜ｃに示す構造のNPNホトトランジスタが提
案されている（特願昭57−198604）。即ち、前者
はベース領域２の表面にN+型の不純物拡散層９
を設けたものであり、後者はベース受光部領域８
の表面に同不純物拡散層９を設けたものである。
しかしながら、こうした改良されたNPNホトト
ランジスタによれば、従来問題となつていたター
ンオフ時間をやや短縮できるものの、十分満足す
るものではなかつた。 For this reason, an NPN phototransistor having the structure shown in FIGS. 3a-c and 4a-c has been proposed (Japanese Patent Application No. 57-198604). That is, the former has an N + type impurity diffusion layer 9 on the surface of the base region 2.
The latter is provided with a base light receiving area 8.
The same impurity diffusion layer 9 is provided on the surface.
However, although these improved NPN phototransistors can somewhat shorten the turn-off time, which has been a problem in the past, they are not fully satisfactory.
本発明は、上記事情に鑑みてなされたもので、
従来と比べ光感度や耐圧を劣化させることなくス
イツチングスピードを向上し得る半導体装置を提
供することを目的とするものである。
The present invention was made in view of the above circumstances, and
It is an object of the present invention to provide a semiconductor device that can improve switching speed without deteriorating photosensitivity or breakdown voltage compared to conventional devices.
本願第１の発明は、第１導電型の半導体基板
と、この基板表面に設けられ入射した光が供給さ
れる第２導電型の半導体領域と、この半導体領域
の一部表面上に設けられた電極と、同半導体領域
表面に前記電極から離隔してその周囲を囲むよう
に形成された第１導電型の不純物導入領域とを具
備することによつて、スイツチングスピードの向
上を図つたものである。
The first invention of the present application provides a semiconductor substrate of a first conductivity type, a semiconductor region of a second conductivity type provided on the surface of this substrate and to which incident light is supplied, and a semiconductor region provided on a part of the surface of this semiconductor region. The switching speed is improved by providing an electrode and an impurity-introduced region of the first conductivity type formed on the surface of the semiconductor region so as to surround the electrode and away from the electrode. be.
本願第２の発明は、第１導電型の半導体基板
と、この基板表面に設けられ入射した光が供給さ
れる第２導電型の半導体領域と、この半導体領域
の一部表面に設けられた第１導電型の半導体領域
と、この第１導電型の半導体領域の表面上に設け
られた電極と、前記第２導電型の半導体領域表面
に第１導電型の半導体領域から離隔してその周囲
を囲むように形成された第１導電型の不純物導入
領域とを具備することによつて、本願第１の発明
と同様な効果を得ることを図つたものである。 The second invention of the present application provides a semiconductor substrate of a first conductivity type, a semiconductor region of a second conductivity type provided on the surface of this substrate and to which incident light is supplied, and a second conductivity type semiconductor region provided on a part of the surface of this semiconductor region. a semiconductor region of one conductivity type; an electrode provided on the surface of the semiconductor region of the first conductivity type; By providing a first conductivity type impurity doped region formed so as to surround the first conductivity type impurity introduction region, it is intended to obtain the same effect as the first invention of the present application.
以下、本発明の一実施例に係るNPNホトトラ
ンジスタを第５図ａ〜ｃを参照して説明する。
Hereinafter, an NPN phototransistor according to an embodiment of the present invention will be described with reference to FIGS. 5a to 5c.
図中の２１は、半導体基板としてのＮ型のシリ
コン基板である。この基板２１の表面には、受光
部として機能する例えば深さ3μｍ、広さ600×
500μｍ□
のP+型のベース領域２２が形成されて
いる。このベース領域２２は、例えば硼素を基板
２１に熱拡散することによつて形成される。この
ベース領域２２の不純物濃度は、例えば１×1011
〜２×1013cm-13cm-3である。前記ベース領域２２
の一部表面には、広さ200×200μｍ□
のN+型のエ
ミツタ領域２３が設けられている。このエミツタ
領域２３の不純物濃度は例えば１×1020〜１×
1021cm-3であり、その面積は前記ベース領域２２
のそれの1/2以下である。前記ベース領域２２の
電極取出し部２４1の周囲及びエミツタ領域２３
の周囲には、Ｎ型不純物導入領域２５が形成され
ている。このＮ型不純物導入領域２５は、エミツ
タ領域２３を形成する時に同時に熱拡散により形
成できる。この場合、Ｎ型不純物導入領域２５
は、エミツタ領域２３より不純物濃度が低くとも
長いので、薄い酸化膜を介して熱酸化すると製造
工程の削減に大きな効果がある。なお、図中の２
４2，２８は夫々エミツタ領域２３の電極取出し
部、絶縁膜を示し、前記電極取出し部２４1，２
４2には夫々金又はアルミニウム等からなるベー
ス電極２６、エミツタ電極２７が設けられてい
る。また、図示しないが、前記Ｎ型のシリコン基
板２１の裏面にはコレクタ電極が設けられてい
る。 21 in the figure is an N-type silicon substrate as a semiconductor substrate. The surface of this substrate 21 has a surface with a depth of 3 μm and a width of 600×, which functions as a light receiving section.
A P + type base region 22 of 500 μm□ is formed. This base region 22 is formed by thermally diffusing boron into the substrate 21, for example. The impurity concentration of this base region 22 is, for example, 1×10 11
~2×10 13 cm -13 cm -3 . The base region 22
An N + type emitter region 23 having a width of 200×200 μm is provided on a part of the surface of the substrate. The impurity concentration of this emitter region 23 is, for example, 1×10 20 to 1×
10 21 cm -3 and its area is the base region 22
It is less than 1/2 of that of . Around the electrode extraction portion 24 1 of the base region 22 and the emitter region 23
An N-type impurity introduced region 25 is formed around the . This N-type impurity introduced region 25 can be formed by thermal diffusion at the same time as the emitter region 23 is formed. In this case, the N-type impurity introduced region 25
Although the impurity concentration is lower than that of the emitter region 23, it is longer, so thermal oxidation via a thin oxide film has a great effect in reducing the number of manufacturing steps. In addition, 2 in the figure
Reference numerals 4 2 and 28 indicate an electrode lead-out portion and an insulating film of the emitter region 23, respectively, and the electrode lead-out portions 24 1 and 2
4 2 is provided with a base electrode 26 and an emitter electrode 27 made of gold, aluminum, or the like, respectively. Although not shown, a collector electrode is provided on the back surface of the N-type silicon substrate 21.
しかして、本発明に係るホトトランジスタによ
れば、エミツタ領域２３の周囲及びベース領域２
２の電極取り出し部２４1の周囲にＮ形不純物導
入領域２５を設けるようにしたので、光吸収時に
発生したキヤリアは光を遮断した時にＮ形不純物
導入領域２５で吸収される。このため、ターンオ
フ時のスイツチング速度は、従来にくらべて向上
させることができる。しかも、受光部となるベー
ス領域２２の面積、シリコン基板２１自体の比抵
抗は、従来と変わらないので、光感度や耐電圧を
劣化させることはない。事実、本発明に係るホト
トランジスタと従来のもの（特願昭57−198604）
とのスイツチング速度を比較したところ第６図に
示す特性図が得られた。なお、図中のＡは従来の
ホトトランジスタの特性線を、Ｂは本発明に係る
ホトトランジスタの特性線を夫々示す。同図にお
いて、横軸には電流増幅率hfeが、縦軸にはスイ
ツチング速度がそれぞれとられている。同図によ
り、本発明のものでは従来に比べてスイツチング
速度が大幅に向上することが確認できる。また、
このようなスイツチング速度を改善したホトトラ
ンジスタの光電感度や耐電圧は、受光部面積や抵
抗値については従来通りで長いので劣化は見られ
なかつた。 According to the phototransistor according to the present invention, the periphery of the emitter region 23 and the base region 2
Since the N-type impurity introduced region 25 is provided around the second electrode extraction portion 24 1 , carriers generated during light absorption are absorbed in the N-type impurity introduced region 25 when the light is blocked. Therefore, the switching speed at turn-off can be improved compared to the prior art. Moreover, since the area of the base region 22 serving as the light receiving section and the resistivity of the silicon substrate 21 itself are the same as in the prior art, there is no deterioration in photosensitivity or withstand voltage. In fact, the phototransistor according to the present invention and the conventional one (Japanese Patent Application No. 1986-04)
When the switching speeds were compared, the characteristic diagram shown in FIG. 6 was obtained. Note that in the figure, A indicates a characteristic line of a conventional phototransistor, and B indicates a characteristic line of a phototransistor according to the present invention. In the figure, the horizontal axis represents the current amplification factor h fe and the vertical axis represents the switching speed. From the figure, it can be confirmed that the switching speed of the present invention is significantly improved compared to the conventional one. Also,
The photoelectric sensitivity and withstand voltage of the phototransistor with improved switching speed were not deteriorated because the light-receiving area and resistance value remained the same as before.
なお、本発明に係るNPNホトトランジスタは、
上記実施例のものに限らない。例えば、上記実施
例よりも若干効果が劣る面はあるが、Ｎ型不純物
領域２５をエミツタ領域２３の周囲または電極取
り出し部２４1のいずれか一方のみに設けてもほ
ぼ同様な満足のいく効果が得られた。また、第７
図ａ〜ｃに示す構造のものでもよい。図中の３１
１，３１2は、Ｎ型のシリコン基板２１表面に互い
に離隔して設けられたP+領域である。これらP+
領域３１1，３１2間にはP++領域３２が設けられ
ている。もちろん、このP+領域３１1及び３１2は
環状に形成したP+領域の一部として存在させ、
P++領域３２を環状P+領域の上側開口部を塞ぐ状
態に形成してよい。また、ベース領域２２の電極
取出し部２４1の周囲及びエミツタ領域２３の周
囲にはＮ型領域２５が設けられている。こうした
構造のホトトランジスタによれば、前述したと同
様の理由により光感度や耐電圧を劣化させること
なくスイツチング速度を向上できる。 Note that the NPN phototransistor according to the present invention is
The invention is not limited to the above embodiments. For example, although the effect is slightly inferior to that of the above embodiment, almost the same satisfactory effect can be obtained by providing the N-type impurity region 25 only around the emitter region 23 or in the electrode lead-out portion 241 . Obtained. Also, the seventh
The structures shown in Figures a to c may also be used. 31 in the diagram
1 and 31 2 are P + regions provided at a distance from each other on the surface of the N-type silicon substrate 21 . These P +
A P ++ region 32 is provided between the regions 31 1 and 31 2 . Of course, these P + regions 31 1 and 31 2 are made to exist as part of the P + region formed in a ring shape,
The P ++ region 32 may be formed to close the upper opening of the annular P + region. Furthermore, an N-type region 25 is provided around the electrode extraction portion 24 1 of the base region 22 and around the emitter region 23 . According to the phototransistor having such a structure, the switching speed can be improved without deteriorating the photosensitivity or withstand voltage for the same reason as mentioned above.
上記実施例では、Ｎ形領域をエミツタ領域と同
程度の高い濃度で形成した例について説明した
が、このＮ型領域がかなり低くてもスイツチング
速度の改善に効果がある。 In the above embodiment, an example has been described in which the N-type region is formed with a concentration as high as that of the emitter region, but even if the N-type region has a considerably low concentration, it is effective in improving the switching speed.
上記実施例では、Ｎ形領域は熱拡散で形成した
例について説明したが、イオン注入、イオンプレ
ーテイング、蒸着など何れの手段で形成しても上
記実施例と同様な効果がある。 In the above embodiment, an example was explained in which the N-type region was formed by thermal diffusion, but the same effect as in the above embodiment can be obtained even if the N-type region is formed by any means such as ion implantation, ion plating, or vapor deposition.
上記実施例では、NPNホトトランジスタに適
用した場合について述べたが、これに限らず、ホ
トダイオードの受光部に適用しても光吸収で発生
したキヤリアについて入射光遮断時のキヤリア吸
収効果を有するものである。 In the above embodiment, the case where the application is applied to an NPN phototransistor is described, but the application is not limited to this, and even when applied to the light receiving part of a photodiode, it has the effect of absorbing carriers generated by light absorption when blocking incident light. be.
以上詳述した如く本発明によれば、ターンオフ
時間を短縮できるPNPホトトランジスタ等の性
能のよい半導体装置を提供できるものである。
As described in detail above, according to the present invention, it is possible to provide a high-performance semiconductor device such as a PNP phototransistor that can shorten the turn-off time.
第１図ａは従来のNPNホトトランジスタの平
面図、同図ｂは同図ａのＸ−Ｘ線に沿う断面図、
同図ｃは同図ａのＹ−Ｙ線に沿う断面図、第２図
ａは従来の他のNPNホトトランジスタの平面図、
同図ｂは同図ａのＸ−Ｘ線に沿う断面図、同図ｃ
は同図ａのＹ−Ｙ線に沿う断面図、第３図ａは従
来の改良型のNPNホトトランジスタの平面図、
同図ｂは同図ａのＸ−Ｘ線に沿う断面図、同図ｃ
は同図ａのＹ−Ｙ線に沿う断面図、第４図ａは従
来の他の改良型のNPNホトトランジスタの平面
図、同図ｂは同図ａのＸ−Ｘ線に沿う断面図、同
図ｃは同図ａのＹ−Ｙ線に沿う断面図、第５図ａ
は本発明の一実施例に係るNPNホトトランジス
タの平面図、同図ｂは同図ａのＸ−Ｘ線に沿う断
面図、同図ｃは同図ａのＸ−Ｘ線に沿う断面図、
第６図は従来及び本発明に係るNPNホトトラン
ジスタのスイツチング速度と電流増幅率との関係
を示す特性図、第７図ａは本発明の他の実施例に
係るNPNホトトランジスタの平面図、同図ｂは
同図ａのＸ−Ｘ線に沿う断面図、同図ｃは同図ａ
のＹ−Ｙ線に沿う断面図である。
２１……Ｎ型のシリコン基板、２２……P+型
のベース領域、２３……N+型のエミツタ領域、
２４1，２４2……電極出し部、２５……Ｎ型不純
物導入領域、２６……ベース電極、２７……エミ
ツタ電極、３１1，３１2……P+領域、３２……
P++領域。
Fig. 1a is a plan view of a conventional NPN phototransistor, Fig. 1b is a cross-sectional view taken along line X-X in Fig. 1a,
Figure c is a cross-sectional view along the Y-Y line in figure a, Figure 2a is a plan view of another conventional NPN phototransistor,
Figure b is a sectional view taken along line X-X in figure a, figure c is
is a cross-sectional view taken along the Y-Y line in Figure 3A, and Figure 3A is a plan view of a conventional improved NPN phototransistor.
Figure b is a sectional view taken along line X-X in figure a, figure c is
4A is a cross-sectional view taken along line Y-Y in FIG. 4A, FIG. Figure c is a sectional view taken along the Y-Y line in figure a, Figure 5a
is a plan view of an NPN phototransistor according to an embodiment of the present invention, FIG.
FIG. 6 is a characteristic diagram showing the relationship between switching speed and current amplification factor of NPN phototransistors according to the conventional and present invention, and FIG. 7a is a plan view of an NPN phototransistor according to another embodiment of the present invention. Figure b is a cross-sectional view taken along the line X-X of figure a, and figure c is a cross-sectional view of figure a.
FIG. 2 is a sectional view taken along the Y-Y line. 21...N type silicon substrate, 22...P + type base region, 23...N + type emitter region,
24 1 , 24 2 ... electrode extension part, 25 ... N-type impurity introduced region, 26 ... base electrode, 27 ... emitter electrode, 31 1 , 31 2 ... P + region, 32 ...
P ++ area.
Claims (1)
設けられ入射した光が供給される第２導電型の半
導体領域と、この半導体領域の一部表面上に設け
られた電極と、同半導体領域表面に前記電極から
離隔してその周囲を囲むように形成された第１導
電型の不純物導入領域とを具備することを特徴と
する半導体装置。 ２ 第１導電型の半導体基板と、この基板表面に
設けられ入射した光が供給される第２導電型の半
導体領域と、この半導体領域の一部表面に設けら
れた第１導電型の半導体領域と、この第１導電型
の半導体領域の表面上に設けられた電極と、前記
第２導電型の半導体領域表面に第１導電型の半導
体領域から離隔してその周囲を囲むように形成さ
れた第１導電型の不純物導入領域とを具備するこ
とを特徴とする半導体装置。 ３ 第２導電型の半導体領域がホトトランジスタ
のベース領域で、かつ第１導電型の半導体領域が
ホトトランジスタのエミツタ領域であることを特
徴とする特許請求の範囲第２項記載の半導体装
置。[Claims] 1. A semiconductor substrate of a first conductivity type, a semiconductor region of a second conductivity type provided on the surface of this substrate and to which incident light is supplied, and a semiconductor region provided on a part of the surface of this semiconductor region. 1. A semiconductor device comprising: an electrode; and a first conductivity type impurity-introduced region formed on the surface of the semiconductor region so as to surround and be spaced apart from the electrode. 2. A semiconductor substrate of a first conductivity type, a semiconductor region of a second conductivity type provided on the surface of this substrate and to which incident light is supplied, and a semiconductor region of a first conductivity type provided on a partial surface of this semiconductor region. and an electrode provided on the surface of the semiconductor region of the first conductivity type, and an electrode formed on the surface of the semiconductor region of the second conductivity type so as to be spaced apart from and surrounding the semiconductor region of the first conductivity type. 1. A semiconductor device comprising: a first conductivity type impurity-introduced region. 3. The semiconductor device according to claim 2, wherein the semiconductor region of the second conductivity type is a base region of a phototransistor, and the semiconductor region of the first conductivity type is an emitter region of the phototransistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58248509A JPS60136272A (en) | 1983-12-24 | 1983-12-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58248509A JPS60136272A (en) | 1983-12-24 | 1983-12-24 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60136272A JPS60136272A (en) | 1985-07-19 |
| JPH0481871B2 true JPH0481871B2 (en) | 1992-12-25 |
Family
ID=17179236
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58248509A Granted JPS60136272A (en) | 1983-12-24 | 1983-12-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60136272A (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4982667U (en) * | 1972-11-02 | 1974-07-17 |
-
1983
- 1983-12-24 JP JP58248509A patent/JPS60136272A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60136272A (en) | 1985-07-19 |
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| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |