JPS622673A - Semiconductor light receiving device - Google Patents

Semiconductor light receiving device

Info

Publication number
JPS622673A
JPS622673A JP60143200A JP14320085A JPS622673A JP S622673 A JPS622673 A JP S622673A JP 60143200 A JP60143200 A JP 60143200A JP 14320085 A JP14320085 A JP 14320085A JP S622673 A JPS622673 A JP S622673A
Authority
JP
Japan
Prior art keywords
layer
region
light
semiconductor layer
depletion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60143200A
Other languages
Japanese (ja)
Inventor
Seiichi Nagai
永井 精一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP60143200A priority Critical patent/JPS622673A/en
Publication of JPS622673A publication Critical patent/JPS622673A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To obtain high speed response all the time, by covering a region, in which an intrinsic semiconductor layer is not converted into a depletion layer, by a light shielding layer. CONSTITUTION:A metal layer 11, which is a light shielding layer, is provided on an insulating film 5. The size of the metal layer 11 is determined so as to cover a region 9, which is not converted into a depletion layer. Namely, the inner end side of the metal layer 11 covers a P-N junction part 7. The outer end side is extended to a channel cutting region 4. Therefore, incident light to the region 9 can be shielded. Yield of an electric charge component, whose moving speed is slow, in the vicinity of the P-N junction can be prevented. Therefore, hole-electron pairs, which are excited by the incident light, are generated only in the depletion layer, which is moved under a high electric field. Thus, high speed response can be always obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は高速応答性を特徴とする半導体受光装置に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor light receiving device characterized by high-speed response.

〔従来の技術〕[Conventional technology]

従来の高速応答性を特徴とする半導体受光装置としては
、例えば、第2図に示すPIN形フォトダイオードがあ
る。
As a conventional semiconductor light receiving device characterized by high-speed response, there is, for example, a PIN type photodiode shown in FIG.

図において、1は真性半導体層(以下1層という)、2
はP形半導体層(以下P層という)、3はN形半導体層
(以下N層という)で、1層1は2層2と8層3の間に
はさまれ、1層1の一部は2層2の周囲から主表面に表
出している。4は主表面に表出した1層1の周辺部に設
けたチャンネルカット領域、5は主表面を被覆する酸化
膜等の絶縁膜、6は2層2と導通する電極である。
In the figure, 1 is an intrinsic semiconductor layer (hereinafter referred to as 1 layer), 2 is
is a P-type semiconductor layer (hereinafter referred to as P layer), 3 is an N-type semiconductor layer (hereinafter referred to as N layer), 1 layer 1 is sandwiched between 2 layers 2 and 8 layers 3, and a part of 1 layer 1 is exposed from the periphery of the second layer 2 to the main surface. Reference numeral 4 designates a channel cut region provided at the periphery of the first layer 1 exposed on the main surface, 5 an insulating film such as an oxide film covering the main surface, and 6 an electrode electrically connected to the second layer 2.

次に動作について説明する。電圧が印加されて1層1が
、破線で示すように、空乏層化され、この領域8に光が
入射すると、正孔・電子対が生じ、高電界の下でドリフ
トにより移動する。このため、高速応答性が得られ、変
換効率もよい。
Next, the operation will be explained. When a voltage is applied, layer 1 becomes a depletion layer as shown by the broken line, and when light enters this region 8, hole-electron pairs are generated and move by drift under a high electric field. Therefore, high-speed response can be obtained and conversion efficiency is also good.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、上記フォトダイオードにおいては、主表
面に表出した1層1と絶縁膜5との界面には正の界面電
荷が存在しており、この影響によリエ層1の表面がN形
化され、実質的にその部分の不純物濃度が高くなるので
、第2図に示すように、上記N形化された部分と2層2
とのPN接合部7の近傍で空乏層が伸びにくくなり、1
層1に空乏層化されない領域9が広く生じ易かった。こ
のため、この空乏層化されない領域9に光が入射される
と、励起された正孔の電子対は拡散により移動するが、
移動速度がドリフトによる移動に比べ著しく遅いため、
高速応答性が得られなくなるという問題があった。
However, in the above photodiode, a positive interfacial charge exists at the interface between the layer 1 and the insulating film 5 exposed on the main surface, and this effect causes the surface of the layer 1 to become N-type. , the impurity concentration in that part becomes substantially high, so as shown in FIG.
The depletion layer becomes difficult to grow near the PN junction 7 with 1
A wide region 9 that was not converted into a depletion layer was likely to occur in the layer 1. Therefore, when light enters the region 9 that is not made into a depletion layer, the electron pairs of the excited holes move due to diffusion.
Because the movement speed is significantly slower than movement by drift,
There was a problem that high-speed response could no longer be obtained.

これを解決する方法として、従来は第3図に示すように
、チャンネルカット領域4と電気的に導通した金属層l
Oを絶縁ItI5の表面周辺部に延在させて、空乏層化
されていない領域9に光が入射しないようにする方法が
あった。この場合、金属層10は、絶縁膜5上に吸着さ
れる電荷がI層lの表面へ影響するのを防ぎ、チャンネ
ル性リークを防止する効果をも持っている。しかし、金
属層10は、チャンネルカット領域4と導通し絶縁膜5
上に延在するため、電極容量となり、その容量が増加す
るので、高速応答性が得られにくい欠点があった。勿論
、金属層10の絶縁膜5上への延在幅をせまくすれば容
量は小さくなるが、こんどはI層lの表面の空乏層化さ
れていない領域9への光入射を防ぐ効果が減少するとい
う問題があった。
Conventionally, as a method to solve this problem, as shown in FIG.
There is a method of extending O around the surface of the insulating ItI 5 to prevent light from entering the region 9 which is not made into a depletion layer. In this case, the metal layer 10 prevents the charges adsorbed on the insulating film 5 from affecting the surface of the I layer 1, and also has the effect of preventing channel leakage. However, the metal layer 10 is electrically conductive with the channel cut region 4 and the insulating film 5
Since it extends upward, it becomes an electrode capacitance and the capacitance increases, which has the disadvantage that it is difficult to obtain high-speed response. Of course, if the extension width of the metal layer 10 onto the insulating film 5 is narrowed, the capacitance will be reduced, but this will reduce the effect of preventing light from entering the region 9 on the surface of the I layer 1 that is not a depletion layer. There was a problem.

この発明は、このような従来の問題点を解決するために
なされたもので、空乏層化されない領域への入射光を効
果的に遮蔽することができ、したがって、常に高速応答
性が得られる半導体受光装置を提供することを目的とす
る。
This invention was made in order to solve these conventional problems, and it is possible to effectively block the incident light to the region where the depletion layer is not formed, and therefore, it is possible to create a semiconductor that can always provide high-speed response. The purpose is to provide a light receiving device.

〔問題点を解決するための手段〕[Means for solving problems]

P形半導体層とN形半導体層との間に真性半導体層をは
さみ、かつ真性半導体層の一部がP形半導体層の周囲に
表出した主表面を絶縁膜で被覆した半導体受光装置にお
いて、前記真性半導体層の空乏層化されない領域への入
射光を遮る遮光層を、前記絶縁膜上に設けたものである
In a semiconductor light-receiving device in which an intrinsic semiconductor layer is sandwiched between a P-type semiconductor layer and an N-type semiconductor layer, and a main surface of which a part of the intrinsic semiconductor layer is exposed around the P-type semiconductor layer is covered with an insulating film, A light-shielding layer is provided on the insulating film to block incident light to a region of the intrinsic semiconductor layer that is not made into a depletion layer.

〔作用〕[Effect]

この発明による半導体受光装置においては、電圧印加時
に空乏層化されない領域への入射光が遮られるので、空
乏層化される領域のみに光が入射される。このため、励
起される電荷は高電界の下で専らドリフトにより移動し
、拡散により移動する電荷成分は除去される。したがっ
て、常に高速応答性を確保できる。
In the semiconductor light-receiving device according to the present invention, when a voltage is applied, incident light to the region that is not formed into a depletion layer is blocked, so that light is incident only to the region that is formed into a depletion layer. Therefore, excited charges move exclusively by drift under a high electric field, and charge components that move by diffusion are removed. Therefore, high-speed response can always be ensured.

〔発明の実施例〕[Embodiments of the invention]

第1図はこの発明の実施例を示す、この実施例は従来例
と同様PIN形フォトダイオードである。図において、
第2図と同符号は同一ないし相当部分を示す、11は絶
縁膜5上に設けた遮光層である。この層11は、内端側
はPN接合部7を覆う位置から外端側はチャンネルカー
/ )領域4に及ぶ幅を有する環状の金属層で、電極6
を構成する金属と同一の金属で形成しである。この実施
例では、アルミニウムを真空蒸着して形成しである。ま
た、遮光層11はチャンネルカー/ 上領域4および電
極6と電気的に導通しないように構成しである。
FIG. 1 shows an embodiment of the present invention. This embodiment is a PIN type photodiode similar to the conventional example. In the figure,
The same reference numerals as in FIG. 2 indicate the same or corresponding parts, and 11 is a light shielding layer provided on the insulating film 5. This layer 11 is an annular metal layer having a width ranging from a position covering the PN junction 7 on the inner end side to a channel car region 4 on the outer end side, and
It is made of the same metal as the metal that composes it. In this embodiment, aluminum is formed by vacuum deposition. Further, the light shielding layer 11 is configured so as not to be electrically connected to the channel car/upper region 4 and the electrode 6.

次に動作について説明する。Next, the operation will be explained.

前述したように、この実施例においても、電圧印加時に
PN接合部7の近傍で空乏層が伸びに〈〈なり、I層l
に空乏層化されない領域9が広く生ずることになる。し
かし、遮光層である金m層11は、上記空乏層化されな
い領域9を覆うだけの大きさで絶縁膜5上に設けである
ので、すなわち、金属層llの内端側はPN接合部7を
覆い、外端側はチャンネルカット領域4に及ぶので、上
記領域9への入射光を遮ることができ、PN接合部7近
傍における移動速度の遅い電荷成分の発生を防止できる
。したがって、入射光で励起される正孔・電子対は、高
電界の下でドリフトにより移動する空乏層内でのみ発生
することとなり、常に高速応答性が得られることになる
As mentioned above, in this embodiment as well, the depletion layer becomes elongated near the PN junction 7 when voltage is applied, and the I layer l
This results in a wide region 9 that is not depleted. However, since the gold m layer 11, which is a light shielding layer, is provided on the insulating film 5 with a size that is large enough to cover the region 9 that is not made into a depletion layer, that is, the inner end side of the metal layer 11 is located at the PN junction 7. Since the outer end side extends to the channel cut region 4, it is possible to block the incident light to the region 9, and to prevent the generation of slow-moving charge components in the vicinity of the PN junction portion 7. Therefore, hole-electron pairs excited by incident light are generated only in the depletion layer that moves due to drift under a high electric field, and high-speed response can always be obtained.

さらに、この実施例では、金属層11は、チャンネルカ
ー/ 上領域4や電極6と電気的に導通していないので
、その容量が増加することはなく、この点からも高速応
答性を確保できる。
Furthermore, in this embodiment, the metal layer 11 is not electrically connected to the channel car/upper region 4 or the electrode 6, so its capacitance does not increase, and from this point of view, high-speed response can be ensured. .

なお、実施例では、PIN形フォトダイオードを例にと
り説明したが、この発明は高速応答性を低下させる領域
への光入射を遮る遮光層を設けることを内容としている
ので、例えば、アバランシェフォトダイオード等信の高
速応答性を必要とする半導体受光装置にも適用できるこ
とは言うまでもない。
Although the embodiments have been described using a PIN type photodiode as an example, this invention is intended to provide a light shielding layer that blocks light from entering a region that degrades high-speed response. Needless to say, the present invention can also be applied to semiconductor photodetectors that require high-speed response.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明によれば、真性半導体層
の空乏層化されない領域を遮光層で覆うようにしたから
、空乏層化されない領域への入射光を遮ることができ、
したがって、常に高速応答性が得られる。
As explained above, according to the present invention, since the region of the intrinsic semiconductor layer that is not depleted is covered with the light shielding layer, it is possible to block the incident light to the region that is not depleted.
Therefore, high-speed responsiveness can always be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は従来の半導体受光装置を示す断面
図、第3図はこの発明の実施例を示す断面図である。 図において、工は真性半導体層、2はP形半導体層、3
はN形半導体層、4はチャンネルカット領域、5は絶縁
膜、6は電極、7はPN接合部、8は空乏層化された領
域、9は空乏層化されない領域、11は遮光層である金
属層である。 なお1図中、回灯は同一または相当部分を示す。
1 and 2 are cross-sectional views showing a conventional semiconductor light receiving device, and FIG. 3 is a cross-sectional view showing an embodiment of the present invention. In the figure, N is an intrinsic semiconductor layer, 2 is a P-type semiconductor layer, and 3 is a P-type semiconductor layer.
is an N-type semiconductor layer, 4 is a channel cut region, 5 is an insulating film, 6 is an electrode, 7 is a PN junction, 8 is a depletion layer region, 9 is a non-depletion region, and 11 is a light shielding layer. It is a metal layer. Note that in Figure 1, round lights indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] P形半導体層とN形半導体層との間に真性半導体層をは
さみ、かつ真性半導体層の一部がP形半導体層の周囲に
表出した主表面を絶縁膜で被覆した半導体受光装置にお
いて、前記真性半導体層の空乏層化されない領域への入
射光を遮る遮光層を、前記絶縁膜上に設けたことを特徴
とする半導体受光装置。
In a semiconductor light-receiving device in which an intrinsic semiconductor layer is sandwiched between a P-type semiconductor layer and an N-type semiconductor layer, and a main surface of which a part of the intrinsic semiconductor layer is exposed around the P-type semiconductor layer is covered with an insulating film, A semiconductor light-receiving device characterized in that a light-shielding layer is provided on the insulating film to block incident light to a region of the intrinsic semiconductor layer that is not converted into a depletion layer.
JP60143200A 1985-06-28 1985-06-28 Semiconductor light receiving device Pending JPS622673A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60143200A JPS622673A (en) 1985-06-28 1985-06-28 Semiconductor light receiving device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60143200A JPS622673A (en) 1985-06-28 1985-06-28 Semiconductor light receiving device

Publications (1)

Publication Number Publication Date
JPS622673A true JPS622673A (en) 1987-01-08

Family

ID=15333200

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60143200A Pending JPS622673A (en) 1985-06-28 1985-06-28 Semiconductor light receiving device

Country Status (1)

Country Link
JP (1) JPS622673A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5315148A (en) * 1990-08-31 1994-05-24 Sumitomo Electric Industries, Ltd. Photo-sensing device
JPH09257685A (en) * 1996-03-26 1997-10-03 Horiba Ltd Photodetector
EP1079440A2 (en) * 1999-08-26 2001-02-28 Oki Electric Industry Co., Ltd. Semiconductor light-receiving element
JP2015053415A (en) * 2013-09-09 2015-03-19 株式会社東芝 Photodiode

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5315148A (en) * 1990-08-31 1994-05-24 Sumitomo Electric Industries, Ltd. Photo-sensing device
JPH09257685A (en) * 1996-03-26 1997-10-03 Horiba Ltd Photodetector
EP1079440A2 (en) * 1999-08-26 2001-02-28 Oki Electric Industry Co., Ltd. Semiconductor light-receiving element
EP1079440A3 (en) * 1999-08-26 2004-05-12 Oki Electric Industry Co., Ltd. Semiconductor light-receiving element
JP2015053415A (en) * 2013-09-09 2015-03-19 株式会社東芝 Photodiode

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