JPH0479014B2 - - Google Patents

Info

Publication number
JPH0479014B2
JPH0479014B2 JP57229421A JP22942182A JPH0479014B2 JP H0479014 B2 JPH0479014 B2 JP H0479014B2 JP 57229421 A JP57229421 A JP 57229421A JP 22942182 A JP22942182 A JP 22942182A JP H0479014 B2 JPH0479014 B2 JP H0479014B2
Authority
JP
Japan
Prior art keywords
logic
result
bit
zero
condition code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57229421A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59121539A (ja
Inventor
Koichi Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57229421A priority Critical patent/JPS59121539A/ja
Publication of JPS59121539A publication Critical patent/JPS59121539A/ja
Publication of JPH0479014B2 publication Critical patent/JPH0479014B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30094—Condition code generation, e.g. Carry, Zero flag

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
JP57229421A 1982-12-28 1982-12-28 条件コ−ド決定回路 Granted JPS59121539A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57229421A JPS59121539A (ja) 1982-12-28 1982-12-28 条件コ−ド決定回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57229421A JPS59121539A (ja) 1982-12-28 1982-12-28 条件コ−ド決定回路

Publications (2)

Publication Number Publication Date
JPS59121539A JPS59121539A (ja) 1984-07-13
JPH0479014B2 true JPH0479014B2 (enrdf_load_stackoverflow) 1992-12-14

Family

ID=16891958

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57229421A Granted JPS59121539A (ja) 1982-12-28 1982-12-28 条件コ−ド決定回路

Country Status (1)

Country Link
JP (1) JPS59121539A (enrdf_load_stackoverflow)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2532083B2 (ja) * 1987-02-26 1996-09-11 株式会社日立製作所 フラグ発生回路
JPH01277931A (ja) * 1988-04-29 1989-11-08 Nec Ic Microcomput Syst Ltd 零検出回路
US5598514A (en) * 1993-08-09 1997-01-28 C-Cube Microsystems Structure and method for a multistandard video encoder/decoder
US5910909A (en) * 1995-08-28 1999-06-08 C-Cube Microsystems, Inc. Non-linear digital filters for interlaced video signals and method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3983382A (en) * 1975-06-02 1976-09-28 International Business Machines Corporation Adder with fast detection of sum equal to zeroes or radix minus one
JPS5587243A (en) * 1978-12-25 1980-07-01 Fujitsu Ltd Zero detection system of adder output

Also Published As

Publication number Publication date
JPS59121539A (ja) 1984-07-13

Similar Documents

Publication Publication Date Title
US5373459A (en) Floating point processor with high speed rounding circuit
US5508950A (en) Circuit and method for detecting if a sum of two multibit numbers equals a third multibit constant number prior to availability of the sum
JPH0479013B2 (enrdf_load_stackoverflow)
JPH07210368A (ja) 算術演算の結果として生じる正および負のオーバーフローのハードウェアによる効率的な取り扱い方法
JPH02144624A (ja) 先行ゼロ予測による正規化装置及び方法
JPH01211119A (ja) 条件コードの予測装置
US3825895A (en) Operand comparator
JPH0823811B2 (ja) ３オペランド演算論理機構におけるオーバーフローを決定する方法及び算術上のオーバーフローを検出する機構
GB1579100A (en) Digital arithmetic method and means
JPH0479014B2 (enrdf_load_stackoverflow)
US6629118B1 (en) Zero result prediction
JP2511527B2 (ja) 浮動小数点演算器
JP3012357B2 (ja) シフト量検出回路
JPS59226944A (ja) 浮動小数点デ−タ加減算方式
JPH0464091B2 (enrdf_load_stackoverflow)
JPH05150948A (ja) 浮動小数点乗算器における丸め回路
JPH0511980A (ja) 桁あふれ検出方式とその回路
US8612500B2 (en) Method and decimal arithmetic logic unit structure to generate a magnitude result of a mathematic
JPH0319568B2 (enrdf_load_stackoverflow)
JPH0799808B2 (ja) 算術論理演算装置
JP2752698B2 (ja) 浮動小数点加減算回路
JPS59184944A (ja) 丸め演算方式
JP3696669B2 (ja) 比較器機構及び比較器
JP2591250B2 (ja) データ処理装置
JPS60235241A (ja) 浮動小数点加算回路