JPH0478167A - Manufacture of semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent deterioration of a gate insulating film by carrying out thermal treatment after ion implantation of large diffusion coefficient of conductivity type opposite to that of a semiconductor substrate at a low energy using a gate electrode of a transistor to carry out data programming as a mask. CONSTITUTION:A resist film 111 which is provided with a contact hole 106 is applied to only a transistor part whereto data 'ON' is written. Then, a substrate of conductivity type opposite to that of a semiconductor substrate such as phosphorus whose thermal diffusion coefficient is larger than that of arsenic is injected at an energy of about 50 to 70 kev to form an N<->-region 207 using a gate electrode as a mask through a contact hole 106. After the resist film 111 is removed, thermal treatment of 850 to 900 deg.C is carried out. Thereby, a source region and a drain region are connected by the N<->-region 207 or they come so near each other as to shortcircuit by punch-through, if apart, by a drain voltage which is applied in a use state, and at least, shortcircuiting becomes possible.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly to a method of data programming by ion implantation of a mask ROM having a submicron gate electrode.

[Conventional technology]

Conventionally, an ion implantation programming method has been used as a data programming method in the manufacturing process of a NAND mask ROM. This will be explained below using FIGS. 2(a) to 2(c).

First, a P-type silicon substrate 201 is selectively oxidized as shown in FIG.
A gate oxide film 203 is formed in the element region. Next, a polycrystalline silicon film is deposited over the entire surface and etched using the resist film as a mask to form a gate electrode 204. after that,
Using the gate electrode 204 as a mask, ions are implanted to form a source/drain region 205 (hereinafter collectively referred to as a source region and a train region).

Next, as shown in FIG. 2(b), a contact hole 206 is formed only in the transistor part where data "'ON" is to be written.
A resist M211 with holes is applied. Then, using the resist film 211 as a mask, phosphorous is ion-implanted with high energy so as to penetrate through the gate electrode 204, and N is implanted into the channel region.
- Due to the area forming area, depletion type MO
S) - A transistor is obtained, and it becomes a diagonal with the data ゛○N'' written in it.6 Next, as shown in Fig. 2(c), after depositing PSG etc. and forming the glabella!208, the digit line contact is made. A mask ROM semiconductor device is obtained by opening holes 209 and forming digit lines 210 using an aluminum film.

[Problem to be solved by the invention]

In the conventional method of writing an "ON" bit by implanting phosphorus except for the gate electrode to form a channel, high energy is implanted, which has the disadvantage of causing deterioration of the film quality of the gate insulating film. There is.

[Means for Solving the Problems] The method for manufacturing a semiconductor device of the present invention includes a step of selectively forming a gate electrode on an element region of a semiconductor substrate via a gate insulating film, and a step of forming a gate electrode using the gate electrode as a mask. a step of implanting first ions of a conductivity type opposite to that of the semiconductor substrate to form a source/train region to form a transistor; and a step of selectively masking regions other than the desired transistor with a resist film and then implanting the first ions. implanting second ions of the same conductivity type and having a higher thermal diffusion coefficient than the first ions into the source/drain region using the gate electrode of the desired transistor as a mask; and performing heat treatment to form the desired transistor. The process includes a step of making at least a short circuit possible between the source region and the drain region.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(c) are cross-sectional views shown in the order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1 (a), a P-type silicon substrate 101
is selectively oxidized to form a field oxide film 102 in the element isolation region.
A gate oxide film 103 is formed to a thickness of about 6,000 to 8,000 λ, and a gate oxide film 103 of about 150 to 300 is formed in the element region. Thereafter, a polycrystalline silicon film is deposited and etched using a resist film as a mask to form electrodes 1 to 104. At this time, it is important to use a submicron gate length of 0.6 to 0.8 μm. Next, in order to form source/drain regions 105, a material of the opposite conductivity type to the semiconductor substrate, such as arsenic, is applied using the gate electrode 104 as a mask.

3X101 with an energy of about 50 to 70 kev
6. Next, as shown in FIG. 1(b), a resist M111 is covered with a contact hole 106 formed only in the transistor part where data "ON" is to be written. wear. Next, using the gate electrode as a mask through the contact hole 106, for example, phosphorus, which is a material of the opposite conductivity type to the semiconductor substrate and has a higher thermal diffusion coefficient than arsenic, is heated 8X at an energy of about 50 to 70 keV.
A N-m region 107 is formed by implanting at a dose of 1012 to 3×10” cm −2 .

Next, after removing resist M111, 850 to 900
Heat treatment is performed at ℃ for 30 minutes to 1 hour.

Then, the source region and the train region are connected by the N- region 207, or even if they are separated as shown in the figure, the source and drain regions are close enough to each other to punch through and short circuit due to the train voltage applied during use. do. In other words, it is at least short-circuitable.

Next, as shown in FIG. 1C, after depositing PSG or the like to form an interlayer film 108, a digit line contact 109 is opened in the train region, and a digit line 110 is formed using aluminum or the like. By making the electrode length submicron and easily short-circuitable, a NAND mask ROM semiconductor device in which an ON bit is written can be obtained.

〔Effect of the invention〕

As explained above, in the present invention, using the gate electrode of the transistor for which data programming is desired as a mask, ions of a conductivity type opposite to that of the semiconductor substrate and having a large diffusion C series are implanted at low energy, and then three heat treatments are performed. Since a depletion type transistor can be obtained, it is possible to manufacture semiconductor memory devices without causing deterioration of the gate insulating film during data programming.

108.208...Interlayer film, 109.209...Tissint line contact, 110,210...Tissint line, 111.211...Resist film.

Claims (1)

[Claims] A step of selectively forming a gate electrode on an element region of a semiconductor substrate via a gate insulating film, and a step of implanting first ions of a conductivity type opposite to that of the semiconductor substrate using the gate electrode as a mask to form a source/drain region. After selectively masking other than the desired transistor with a resist film, a second ion having the same conductivity type as the first ion and having a larger thermal diffusion coefficient than the first ion is formed. The method includes a step of implanting ions into the source/drain region using the gate electrode of the desired transistor as a mask, and a step of performing heat treatment to make at least a short circuit possible between the source region and the drain region of the desired transistor. A method of manufacturing a semiconductor memory device, characterized in that: