JPH0476728U

JPH0476728U -

Info

Publication number: JPH0476728U
Application number: JP12141890U
Authority: JP
Priority date: 1990-11-19
Filing date: 1990-11-19
Publication date: 1992-07-03

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例による位相同期ル
ープを示す図、第２図は第１図の各部の波形を示
す図、第３図はこの考案の他の実施例を示す図、
第４図は従来の位相同期ループを示す図、第５図
は第４図の各部の波形を示す図である。図において、１は位相検波器、２はＡ／Ｄ変換
器、３はデイジタルループフイルタ、３ａは第１
乗算器、３ｂは第２乗算器、３ｃは第１加算器、
３ｄは遅延回路、３ｅは第２加算器、３ｆは補正
回路、３ｇはスイツチ、４はＤ／Ａ変換器、５は
ＶＣＯ、６はロツクオン検出器。なお、図中、同
一符号は同一、又は相当部分を示す。 FIG. 1 is a diagram showing a phase-locked loop according to an embodiment of this invention, FIG. 2 is a diagram showing waveforms of each part of FIG. 1, and FIG. 3 is a diagram showing another embodiment of this invention.
FIG. 4 is a diagram showing a conventional phase-locked loop, and FIG. 5 is a diagram showing waveforms at various parts in FIG. In the figure, 1 is a phase detector, 2 is an A/D converter, 3 is a digital loop filter, and 3a is a first
a multiplier; 3b is a second multiplier; 3c is a first adder;
3d is a delay circuit, 3e is a second adder, 3f is a correction circuit, 3g is a switch, 4 is a D/A converter, 5 is a VCO, and 6 is a lock-on detector. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims

[Scope of utility model registration request]

a phase detector; an A/D converter that A/D converts the output of the phase detector; a first multiplier, a second multiplier, a first adder that filters the A/D converter output;
Consisting of a second adder and a delay circuit, the A/D converter output is input to the first multiplier and the second multiplier, and the output of the first multiplier is supplied to one input of the second adder, The output of the second multiplier is supplied to one input of the first adder, the output of the first adder is supplied to the other input of the second adder and also supplied to the delay circuit, and the delay circuit output is supplied to the second adder. A digital loop filter supplied to the other input of the adder and a D/A converting the output of the digital leap filter.
In a phase-locked loop comprising a converter, a voltage-controlled oscillator whose oscillation frequency is controlled by a D/A converter output signal, and a lock-on detector, the first multiplier output in the digital loop filter is input and the first A phase-locked loop comprising a correction circuit that calculates the amount of change in the output of the first multiplier when the multiplication coefficient of the first multiplier is changed and supplies the amount of change to the delay circuit as an initial value of the delay circuit. .