JPH0474436A - Vertical pnp transistor - Google Patents

Abstract

PURPOSE:To prevent an N-type poor layer form being produced in a base region by a method wherein a high-concentration N<+> type base barrier is formed between an N-type base and a P-type collector and a high-concentration emitter barrier is formed between the N-type base and a P<+> type emitter. CONSTITUTION:An N<+> type base barrier 6 of high-concentration boron on the order of 10<19> to 10<20> is formed in a P-type collector layer. Since the N<+> type base barrier 6 is situated at a fairly deep part, e.g. at 0.5 to 1mum, in the P-type collector 3, it is required to execute RTA (high-speed heat treatment) in order to diffuse boron by a large-output ion implantation operation and to form a steep concentration distribution. Then, an N-type base 4 is formed in the P-type collector layer 3. After that, in the same manner as the formation method of the N<+> type base barrier 6, an N<+> type emitter barrier 7 of high concentration boron on the order of 10<19> to 10<20> is formed in the N-type base 4. Lastly, a P<+> type emitter 5 is formed. The P-type collector 3, the N-type base 4 and the P<+> type emitter 5 are diffused and buried by using an ordinary semiconductor manufacturing means.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a vertical PNP transistor, and particularly to a vertical PNP transistor for high frequency use.

[Conventional technology]

Figure 2 is an impurity concentration distribution diagram in an example of a conventional vertical PNP transistor.
- type semiconductor substrate 1 and an N- type buried layer 2. P type connector 3
．． It had a structure in which an N-type base 4 and a P'-type emitter 5 were sequentially stacked in a contracted form.

The impurity concentration in each region at that time is approximately IQ18 in the emitter region of IQ21, as shown in Figure 2.
Base area of 1017 units Collector area IQ1!
Semiconductor substrates with i levels of embedded layers and IQ levels of 15 levels were common. Note that the horizontal axis in FIG. 2 represents the depth from the surface of the semiconductor on a linear scale, and the vertical axis represents the impurity concentration on a logarithmic scale.

[Problem to be solved by the invention]

The above-mentioned conventional vertical PNP transistor is characterized by the outward diffusion of holons from the P-type collector 3 to the N-type base 4 when forming the N-type base 4 by pressing, and by the outward diffusion of holons from the P+-type emitter 5 when forming the P+-type emitter 5 by pressing. The outward diffusion of holons into the N-type base 4 generates an N-type 17 layer 16 with a low phosphorus concentration in the N-type base 4 region. This is caused by the difference in diffusion rates between boron and phosphorus.

Therefore, as shown by the broken line in FIG. 2, there are disadvantages such as an increase in the emitter ground current amplification factor (hvt) due to the narrowing of the effective base width Wb, and noise deterioration due to the increase in the base resistance.

[Means to solve the problem]

The vertical PNP transistor of the present invention has an N" type emitter barrier layer formed directly below the P+ type emitter region and encompassing the emitter region, and an N" type emitter barrier layer formed directly below the N type base region and covering a part of the base region. and an N+ type base barrier layer formed under the N+ type emitter barrier layer.

〔Example〕

Next, the present invention will be explained with reference to FIG.

FIG. 1 is a diagram showing an embodiment of a vertical PNP transistor of the present invention, FIG. 1(a) is a longitudinal sectional view thereof, and FIG. 1(b)
is an impurity concentration distribution diagram in the A-All cross section of FIG. 1 (a>).

In FIG. 1, 1 is a P-type semiconductor substrate, 2 is an N-type buried layer, and a P-type collector 3 called a P-well is formed above them. After that, 1Q19~1 in the P type collector layer.
An N+ type base barrier 6 of high concentration boron on the order of 0.02° is formed. Since the N+ type base barrier 6 is located quite deep in the P type collector 3, for example, 0.5 to 1 μm, it has a large output (several 1
In addition to diffusing boron by ion implantation (00KeV),
RTA (Rapid Heat Treatment) to form a steep concentration distribution
need to be done.

Next, an N-type base 4 is formed in the P-type collector 3 layer. After that, the N
An N″′ type emitter barrier 7 of high concentration boron in the order of 1019 to 1020 is formed in the mold base 4.Finally, a P+ type emitter 5 is formed. The diffusion and embedding of 8 is carried out by normal semiconductor manufacturing means.
Reference numeral 9 indicates an MM film for the transistor, 9 indicates a P" collector contact which is an electrode of the collector region, and 10 indicates an N+ base contact which indicates an electrode of the base region.

Figure 1(b) shows the impurity concentration distribution of the vertical PNP)-transistor fabricated in this way.The base region has a high concentration N+ type emitter barrier 7, an N+ type base barrier 6, and a conventional N+ type base barrier 6. It is composed of a high concentration N-type base 4, and impurities have a wave-like distribution.

Note that the vertical axis in FIG. 1(b) represents the impurity concentration on a logarithmic scale, and the horizontal axis represents the depth from the transistor surface on a linear scale.

〔Effect of the invention〕

As explained above, the present invention forms a highly doped N+ type base barrier between the N type base and the P type collector, and forms a highly doped N+ type emitter barrier between the N type base and the P'' type emitter. By forming a
Since the generation of the type 17 layer is prevented, the effective base width Wb can be made to almost any desired value, which has the effect of preventing the deterioration of hFE, and furthermore, the high concentration barrier layer lowers the base resistance and reduces noise. It has an improved effect.

[Brief explanation of drawings]

FIG. 1(a) is a vertical sectional view showing an embodiment of the vertical PNP transistor of the present invention, and FIG. 1(b) is A of FIG. 1<a>.
FIG. 2 is an impurity concentration distribution diagram in an example of a conventional vertical PNP l-transistor. DESCRIPTION OF SYMBOLS 1...P-type semiconductor substrate, 2...N-type buried layer, 3
...P type collector, 4...N type base, 5...P
4 type emitter, 6...N''' type base barrier, 7...
・N゛-type emitter barrier, 8... Isolation oxide film, 9...
・P+ collector contact, 10...N" base contact, 16...N type 17 layer.

Claims (1)

[Claims] an N^+ type emitter barrier layer formed immediately below the P^+ type emitter region and encompassing the emitter region;
A vertical PNP transistor comprising an N^+ type base barrier layer which is located directly under the type base region, includes a part of the base region, and is formed under the N^+ type emitter barrier layer.