Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu LtdfiledCriticalFujitsu Ltd
Priority to JP59165635ApriorityCriticalpatent/JPS6145276A/ja
Publication of JPS6145276ApublicationCriticalpatent/JPS6145276A/ja
Publication of JPH0469390B2publicationCriticalpatent/JPH0469390B2/ja
Random access memory with latency arranged for operating synchronously with a micro processor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock