JPH046843A - Electrode structure of semiconductor-device mounting substrate - Google Patents
Electrode structure of semiconductor-device mounting substrateInfo
- Publication number
- JPH046843A JPH046843A JP2108115A JP10811590A JPH046843A JP H046843 A JPH046843 A JP H046843A JP 2108115 A JP2108115 A JP 2108115A JP 10811590 A JP10811590 A JP 10811590A JP H046843 A JPH046843 A JP H046843A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- conductor lead
- plated
- width
- tip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 48
- 239000004020 conductor Substances 0.000 claims abstract description 46
- 239000000463 material Substances 0.000 claims abstract description 13
- 241000218202 Coptis Species 0.000 claims description 8
- 235000002991 Coptis groenlandica Nutrition 0.000 claims description 8
- 239000010931 gold Substances 0.000 abstract description 14
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052737 gold Inorganic materials 0.000 abstract description 10
- 230000008646 thermal stress Effects 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 4
- 229910000846 In alloy Inorganic materials 0.000 abstract description 2
- 230000035882 stress Effects 0.000 description 9
- 238000007747 plating Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は半導体装置実装基板に係り、特に半導体装置を
フェースダウンボンディングする実装基板の電極構造に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device mounting board, and more particularly to an electrode structure of a mounting board for face-down bonding a semiconductor device.
第７図は、従来の半導体装置実装基板の電極と半導体装
置との接続方法を示すものである。半導体装置実装基板
１の基板２は＾１２０．やＳｉＣ、ＡＩＮ等のセラミッ
ク系材料で形成され、その片面にはＣｕ層又はそのＣｕ
層にＮｉメンキを施した導体リード３が設けられ、導体
リード３の先端部分には、突起状のＡｕ又は半田からな
る電極ハンプ４が設けられている。このような電極ハン
プ４は、底面積が小さく、基板からの高さｈをさほど高
くすることができない。FIG. 7 shows a conventional method of connecting electrodes of a semiconductor device mounting board and a semiconductor device. The board 2 of the semiconductor device mounting board 1 is ^120. It is made of ceramic material such as SiC, AIN, etc., and one side has a Cu layer or its Cu layer.
A conductor lead 3 whose layer is coated with Ni is provided, and a protruding electrode hump 4 made of Au or solder is provided at the tip of the conductor lead 3. Such an electrode hump 4 has a small bottom area, and the height h from the substrate cannot be increased very much.
このような半導体装置実装基板１に半導体装置５をフェ
ースダウンボンディングして実装するには、ボンディン
グヘッド（図示せず）に吸着させた半導体装置５を電極
ハンプ４上に、半導体装置５に設けられたパッド６との
位置を合わせて載置し、荷重を加えると同時に加熱する
、いわゆる熱圧着法により、電極バンブ４と半導体装置
５のバッド６とを接合するという方法が採られていた。In order to mount the semiconductor device 5 on such a semiconductor device mounting board 1 by face-down bonding, the semiconductor device 5 adsorbed by a bonding head (not shown) is placed on the electrode hump 4 and mounted on the semiconductor device 5. The electrode bump 4 and the pad 6 of the semiconductor device 5 are bonded by a so-called thermocompression bonding method in which the electrode bump 4 and the pad 6 are placed in alignment with each other, and a load is applied and heating is applied at the same time.
〔発明が解決しようとする！ＩＮ）
ところで、このように構成された従来の半導体装置実装
基板ｌでは、電極バンブ４が、Ｃｕ層又はそのＣｕ層に
Ｎｉメッキが施された導体リード３の先端部に設けられ
ているため、実装基板１の電極ハンプ４と、半導体装置
５のパッド６を接合した場合、半導体装１５と実装基板
１の基板２を構成する部材の熱膨張率（例えば半導体装
１５が５１では３．５ Ｘｌ０−’／ ’Ｃ１半導体装
置実装基板１の基板２がＡ１□０３では７．４ Ｘｌ０
−’／ ”Ｃ）の差により応力が発生する。この応力は
導体リード３と突起状電極バンプ４に加わるが、導体リ
ード３はＣｕで構成されているため電極バンブ４のＡｕ
又は半田よりも剛性が高く、その応力は突起状電極バン
プ４に集中する。この応力が小さい間は突起状電極バン
プ４が変形して応力を吸収するが、これが大きくなると
突起状電極バンプ４と半導体装置５のパッド６に断線や
剥離を生ずるという問題点があった。[Invention tries to solve it! By the way, in the conventional semiconductor device mounting board l configured in this way, the electrode bump 4 is provided at the tip of the conductor lead 3 in which the Cu layer or the Cu layer is plated with Ni. When the electrode hump 4 of the mounting board 1 and the pad 6 of the semiconductor device 5 are bonded, the coefficient of thermal expansion of the members constituting the semiconductor device 15 and the substrate 2 of the mounting board 1 (for example, if the semiconductor device 15 is 51, the coefficient of thermal expansion is 3.5 Xl0 -'/'If board 2 of C1 semiconductor device mounting board 1 is A1□03, 7.4 Xl0
-'/"C) stress is generated. This stress is applied to the conductor lead 3 and the protruding electrode bump 4, but since the conductor lead 3 is made of Cu, the Au of the electrode bump 4
Alternatively, it has higher rigidity than solder, and its stress is concentrated on the protruding electrode bumps 4. While this stress is small, the protruding electrode bump 4 deforms and absorbs the stress, but when it becomes large, there is a problem in that the protruding electrode bump 4 and the pad 6 of the semiconductor device 5 may be disconnected or peeled off.
また、剛性の低い材料を導体リード３にメッキする方法
によれば、メッキにより導体リード３の幅が広がり実装
密度の低下を招くといった欠点があった。Furthermore, the method of plating the conductor leads 3 with a material having low rigidity has the disadvantage that the width of the conductor leads 3 increases due to the plating, resulting in a reduction in packaging density.
本発明は、前記背景に鑑みてなされたものであり、その
目的とするところは、実装密度を低下させることなく、
熱的ストレスにより突起状電極ハンプと半導体装置の接
続部分に、クラックや断線が生ずることなく信顧性の高
い電極構造を提供することにある。The present invention has been made in view of the above background, and its purpose is to
It is an object of the present invention to provide a highly reliable electrode structure that does not cause cracks or disconnections at the connection portion between a protruding electrode hump and a semiconductor device due to thermal stress.
〔課題を解決するための手段］
上記課題を解決するため本発明は、片面に導体リード３
を有する基板２と、その導体リード３先端に半導体装置
５のパッド６が接続される突起状電極バンプ４を有して
なる半導体装置実装基板ｌにおいて、前記導体リード３
の先端部３ａの幅Ｗ１を他の部分の幅Ｗ２よりも細く形
成すると共に、該先端部３ａに金糸材料をメッキしたメ
ッキ部７を形成し、該メッキ部７の半導体装置５のパッ
ド６対向位置に突起状電極バンプ４を設けたことを特徴
とするものである。[Means for Solving the Problems] In order to solve the above problems, the present invention provides conductor leads 3 on one side.
In a semiconductor device mounting board l comprising a substrate 2 having a conductor lead 3 and a protruding electrode bump 4 to which a pad 6 of a semiconductor device 5 is connected to the tip of the conductor lead 3, the conductor lead 3
The width W1 of the tip 3a is made narrower than the width W2 of the other parts, and a plated part 7 plated with gold thread material is formed on the tip 3a, and the plated part 7 faces the pad 6 of the semiconductor device 5. It is characterized in that protruding electrode bumps 4 are provided at the positions.
上記のように構成されているため、本発明の半導体装置
実装基板１においては、半導体装置５と実装基板１の基
板２の熱膨張率の差により生ずる応力は、突起状バンプ
４とその実装基板１側に設けた比較的剛性の低い金糸材
料によるメンキ部７によって吸収され、熱的ストレスに
より突起状電極バンプ４と半導体装置５のパッド６との
接続部分に、クラックや断線が生ずることが少なくなる
。また、導体リード３の先端部３ａの幅Ｗ１を、他の部
分の幅Ｗ２よりも細く形成したため、その上に金糸材料
をメッキして導体リード３の一部であるメッキ部７を形
成しても、メッキのふくれにより導体リードが短絡する
ことがなく、そのふくれをも含めたメッキ部の幅は導体
リード３の他の部分の幅Ｗ２と略同等に抑えられ、導体
リード３の幅を殆ど広げることがなく、したがって、基
板２上での実装密度を低下させることはない。Because of the above structure, in the semiconductor device mounting board 1 of the present invention, the stress caused by the difference in thermal expansion coefficient between the semiconductor device 5 and the substrate 2 of the mounting board 1 is transmitted between the protruding bumps 4 and the mounting board 1. The thermal stress is absorbed by the thin layer 7 made of a gold thread material with relatively low rigidity provided on the 1 side, so that cracks and disconnections are less likely to occur at the connection portion between the protruding electrode bump 4 and the pad 6 of the semiconductor device 5 due to thermal stress. Become. Furthermore, since the width W1 of the tip portion 3a of the conductor lead 3 is formed to be narrower than the width W2 of the other portion, a gold thread material is plated thereon to form the plated portion 7, which is a part of the conductor lead 3. Also, the conductor lead will not be short-circuited due to the bulge in the plating, and the width of the plated part including the bulge can be kept approximately equal to the width W2 of the other part of the conductor lead 3, making the width of the conductor lead 3 almost the same. There is no need to spread out, and therefore, there is no reduction in the packaging density on the board 2.
〔実施例］
第り図及び第４図は、本発明の第１の実施例を示すもの
であり、前記従来例と異なる点について以下詳述する。[Embodiment] Figures 1 and 4 show a first embodiment of the present invention, and the differences from the conventional example will be described in detail below.
導体リード３は、前記従来例と同様に、同材質により形
成され基板２上に設けられてはいるが、その形状が前記
従来例と異なり、先端部３ａの幅ｗｌが他の部分の輻Ｗ
２よりも狭く形成されたものである。Although the conductor lead 3 is made of the same material and provided on the substrate 2 as in the conventional example, its shape is different from that in the conventional example, and the width wl of the tip portion 3a is the same as the width W of other parts.
It is narrower than 2.
メッキ部７は、前記導体リード３の先端部３ａに金糸材
料である金を電解メッキすることにより形成されたもの
で、メッキ部７は電気的には導体リード３の一部を構成
するものである。また、このメッキ部７上であって半導
体装置５のパッド６に対向する位置にはＡｕ又はＩｎ合
金等からなる突起状電極バンプ４が設けられ、半導体装
置５のパッド６と接合されて電気的接続がとられる。The plated portion 7 is formed by electrolytically plating gold, which is a gold thread material, on the tip portion 3a of the conductor lead 3, and the plated portion 7 electrically constitutes a part of the conductor lead 3. be. Further, a protruding electrode bump 4 made of Au or In alloy is provided on the plated portion 7 at a position facing the pad 6 of the semiconductor device 5, and is connected to the pad 6 of the semiconductor device 5 for electrical connection. A connection is established.
このような実装基板１は、第３図及び第４図に示すよう
な方法で製造される。つまり、まずセランミック系の基
板２上にＣｕ層又はそのＣｕ層にＮｉメッキが施された
導体リード３を、その先端部３ａの幅寸法ｗｌを他の部
分の幅寸法Ｗ２よりも狭く、かつその厚み１１も他の部
分の厚みｔ２よりも薄く形成して設け（第３図（ａｌ、
建）及び第４図（ａ）参照）、導体リード３の先端部３
ａを除いてマスキンクテープ８を貼り付けてマスキング
する（第４図（ｂ）参照）、その状態で導体リード３の
先端部３ａに金の電解メッキ処理を施して金を堆積させ
、マスキングテープ８をはがす（同図ＦＣ）参照）。次
に、全体をレジスト９（例えばポジレジスト）を塗布し
乾燥させた後に、メッキ部７上で半導体装Ｗ５のパッド
６の対向位置に紫外線を照射し、現像して窓１０をあけ
（同図（ロ）参照）、金による電解メッキ処理を行って
突起状電極バンブ４を形成させた後にレジスト９を剥離
して実装基板１が製作される（同図（ｅ）参照）。Such a mounting board 1 is manufactured by the method shown in FIGS. 3 and 4. That is, first, a conductor lead 3 having a Cu layer or a Ni plating applied to the Cu layer is placed on a ceramic substrate 2 so that the width wl of the tip 3a is narrower than the width W2 of the other part, and The thickness 11 is also formed to be thinner than the thickness t2 of other parts (Fig. 3 (al,
construction) and Fig. 4(a)), the tip 3 of the conductor lead 3
Apply masking tape 8 to all parts except point a for masking (see Fig. 4 (b)). In this state, conductive gold electrolytic plating treatment is applied to the tip 3a of the conductor lead 3 to deposit gold, and masking tape is applied. 8 (see FC in the same figure). Next, after applying a resist 9 (for example, a positive resist) to the entire surface and drying it, ultraviolet rays are irradiated onto the plated part 7 at a position opposite to the pad 6 of the semiconductor device W5, and the window 10 is opened by developing the resist 9 (in the same figure). After electrolytic plating with gold is performed to form the protruding electrode bumps 4, the resist 9 is peeled off to produce the mounting board 1 (see (e) in the same figure).
このように構成したため、本発明の半導体装置実装基板
１においては、半導体装置５と実装基板１の基板２の熱
膨張率の差により生ずる応力は、突起状バンブ４とあわ
せてその実装基板１側に設けた金メッキ部７によっても
吸収され熱的ストレスにより突起状電極バンブ４と、半
導体装置５のパッド６の接続部分にクラックや断線が生
ずることが少なくなり、接続の信顧性が向上する。また
、導体リード３の先端部３ａの幅Ｗｌを他の部分の幅Ｗ
２よりも細く形成したため、その上に金をメッキして導
体リード３の一部としてメッキ部７を形成しても、メン
キのふくれを含めたメッキ部７の幅は導体リード３の他
の部分の幅Ｗ２と路間等に抑えられ、導体リード３の幅
を殆ど広げることがなく、第２図に示すように各導体リ
ード３間のピッチを広げずに間隔Ｗ３が確保でき、した
がって、実装密度を低下させることがない。Because of this structure, in the semiconductor device mounting board 1 of the present invention, the stress caused by the difference in thermal expansion coefficient between the semiconductor device 5 and the substrate 2 of the mounting board 1 is applied to the mounting board 1 side together with the protruding bumps 4. It is also absorbed by the gold plated portion 7 provided on the surface of the semiconductor device 5, and cracks and disconnections are less likely to occur at the connection portion between the protruding electrode bump 4 and the pad 6 of the semiconductor device 5 due to thermal stress, thereby improving the reliability of the connection. In addition, the width Wl of the tip portion 3a of the conductor lead 3 is set to the width Wl of the other portion.
2, so even if the plated part 7 is formed as a part of the conductor lead 3 by plating gold on it, the width of the plated part 7 including the bulge is the same as that of other parts of the conductor lead 3. The width W2 of the conductor leads 3 is suppressed to the distance between the paths, etc., and the width of the conductor leads 3 is hardly increased.As shown in FIG. No reduction in density.
第５図及び第６図は、本発明の第２の実施例を示すもの
で、前記第１の実施例と異なる点は、導体リード３の先
端部３ａの厚さｔ３を厚くした点と、電極バンブ４の基
板からの高さｈｌを高くした点であり、この異なる点に
ついて、以下詳述する。5 and 6 show a second embodiment of the present invention, which differs from the first embodiment in that the thickness t3 of the tip portion 3a of the conductor lead 3 is increased; The difference is that the height hl of the electrode bump 4 from the substrate is increased, and this different point will be described in detail below.
導体リード３は、前記実施例と同様にその幅Ｗ１を他の
部分の幅Ｗ２よりも細（して構成されており、また、そ
の先端部３ａの厚みｔ３は、他の部分の厚みｔ２と等し
く、この先端部３ａに金糸材料である金メンキを施して
導体リード３から突出したメッキ部７とし、さらに、そ
の上に突起状電極バンプ４を設けて構成したもので、こ
のため、電極バンブ４の基板からの高さｈｌが高く形成
されたものである。The conductor lead 3 is configured so that its width W1 is thinner than the width W2 of the other portion, as in the previous embodiment, and the thickness t3 of the tip portion 3a is the same as the thickness t2 of the other portion. Similarly, this tip portion 3a is coated with gold coating, which is a gold thread material, to form a plated portion 7 protruding from the conductor lead 3, and a protruding electrode bump 4 is further provided thereon. The height hl from the substrate No. 4 is formed to be high.
このように構成したため、本実施例においても前記第１
の実施例と同様の効果を奏すると共に、基板２からの突
起状電極バンプ４先端まで高さが高くとれるため、さら
に熱により生ずる応力を吸収でき、また、半導体装置５
と基板２の間に樹脂を充填して半導体装置５と基板２と
の接合性を向上する場合においては、隙間が大きいため
低熱膨張率でかつ粘度が高い樹脂であってもその充填が
し昂いという効果をも奏する。Because of this configuration, in this embodiment as well, the first
In addition to producing the same effect as in the embodiment, since the height from the substrate 2 to the tip of the protruding electrode bump 4 can be increased, stress caused by heat can be further absorbed, and the semiconductor device 5
In order to improve the bonding between the semiconductor device 5 and the substrate 2 by filling the gap between the semiconductor device 5 and the substrate 2, even if the resin has a low coefficient of thermal expansion and high viscosity, the filling will be difficult. It also has the effect of
〔発明の効果〕
本発明は前述の通り構成されているので、半導体装置と
半導体装置実装基板の熱膨張率の差により生ずる応力は
、突起状バンプとあわせてその実装基板側に設けた金糸
材料によるメッキ部によっても吸収され熱的ストレスに
より突起状電極バンプと、半導体装置の接続部分にクラ
ンクや断線が生ずることが少なくなり、接合の信鯨性が
高まる、また、導体リードの先端部の幅を他の部分より
も細く形成したため、その上に金糸材料をメッキして導
体リードの一部であるメッキ部を形成しても、メッキの
ふくれを含めたメッキ部の幅は導体リードの他の部分の
幅と路間等に抑えられ、導体リートの幅を殆ど広げるこ
とがなく、従って、実装密度を低下させることがない。[Effects of the Invention] Since the present invention is constructed as described above, the stress caused by the difference in thermal expansion coefficient between the semiconductor device and the semiconductor device mounting board is absorbed by the gold thread material provided on the mounting board side in addition to the protruding bumps. It is also absorbed by the plating part, which reduces the occurrence of cranks and disconnections at the connection between the protruding electrode bump and the semiconductor device due to thermal stress, increasing the reliability of the bond. Because it is formed thinner than other parts, even if a gold thread material is plated on it to form a plated part that is part of the conductor lead, the width of the plated part including the plating bulge is smaller than that of the other parts of the conductor lead. The width of the conductor lead is kept within the width of the part, the width of the conductor lead, etc., and the width of the conductor lead is hardly increased, so that the packaging density is not reduced.
第１図は本発明の第１の実施例を示す側面図、第２図は
同上の導体リードが実装基板上に２つ並んだ状態の要部
平面図、第３図は同上の導体リードの要部形状を示すも
ので、（ａ）は平面図、（ｂ）は側面図、第４図（ａ）
〜（ｅ）は同上の製造工程を示す側面図、第５図は本発
明の第２の実施例を示す側面図、第６図は同上の導体リ
ードの要部形状を示すもので、（ａ）は平面図、（５）
は側面図、第７図は従来の半導体装置実装基板と半導体
装置を示す側面図である。
１−半導体装！実装基板 ２一基板
３−導体リード ３ａ 先端部４−突起状電極
ハンプ ５−半導体装置パッド
メンキ部Fig. 1 is a side view showing the first embodiment of the present invention, Fig. 2 is a plan view of the main part of the same conductor lead with two of them lined up on a mounting board, and Fig. 3 is a side view of the same conductor lead as above. It shows the shape of the main part, (a) is a plan view, (b) is a side view, and Fig. 4 (a)
-(e) are side views showing the same manufacturing process as above, FIG. 5 is a side view showing the second embodiment of the present invention, and FIG. ) is a plan view, (5)
is a side view, and FIG. 7 is a side view showing a conventional semiconductor device mounting board and a semiconductor device. 1-Semiconductor equipment! Mounting board 2 - Board 3 - Conductor lead 3a Tip part 4 - Projected electrode hump 5 - Semiconductor device pad opening part
Claims (1)
ド先端に半導体装置のパッドが接続される突起状電極バ
ンプを有してなる半導体装置実装基板において、前記導
体リードの先端部の幅を他の部分よりも細く形成すると
共に、該先端部に金糸材料をメッキしたメッキ部を形成
し、該メッキ部上であって半導体装置のパッド対向位置
に突起状電極バンプを設けたことを特徴とする半導体装
置実装基板の電極構造。(1) In a semiconductor device mounting board comprising a substrate having a conductor lead on one side and a protruding electrode bump to which a pad of a semiconductor device is connected to the tip of the conductor lead, the width of the tip of the conductor lead is It is characterized by forming a plated part thinner than the part, and forming a plated part plated with a gold thread material at the tip part, and providing a protruding electrode bump on the plated part at a position facing the pad of the semiconductor device. Electrode structure of semiconductor device mounting board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2108115A JPH046843A (en) | 1990-04-24 | 1990-04-24 | Electrode structure of semiconductor-device mounting substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2108115A JPH046843A (en) | 1990-04-24 | 1990-04-24 | Electrode structure of semiconductor-device mounting substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH046843A true JPH046843A (en) | 1992-01-10 |
Family
ID=14476290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2108115A Pending JPH046843A (en) | 1990-04-24 | 1990-04-24 | Electrode structure of semiconductor-device mounting substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH046843A (en) |
-
1990
- 1990-04-24 JP JP2108115A patent/JPH046843A/en active Pending
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