JPH0467650B2 - - Google Patents

Info

Publication number
JPH0467650B2
JPH0467650B2 JP60018322A JP1832285A JPH0467650B2 JP H0467650 B2 JPH0467650 B2 JP H0467650B2 JP 60018322 A JP60018322 A JP 60018322A JP 1832285 A JP1832285 A JP 1832285A JP H0467650 B2 JPH0467650 B2 JP H0467650B2
Authority
JP
Japan
Prior art keywords
carry
circuit
sign
ahead
adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60018322A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61177542A (ja
Inventor
Tomohiko Endo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP1832285A priority Critical patent/JPS61177542A/ja
Publication of JPS61177542A publication Critical patent/JPS61177542A/ja
Publication of JPH0467650B2 publication Critical patent/JPH0467650B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
JP1832285A 1985-02-01 1985-02-01 符号補数・符号絶対値併用加減算装置 Granted JPS61177542A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1832285A JPS61177542A (ja) 1985-02-01 1985-02-01 符号補数・符号絶対値併用加減算装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1832285A JPS61177542A (ja) 1985-02-01 1985-02-01 符号補数・符号絶対値併用加減算装置

Publications (2)

Publication Number Publication Date
JPS61177542A JPS61177542A (ja) 1986-08-09
JPH0467650B2 true JPH0467650B2 (cg-RX-API-DMAC7.html) 1992-10-29

Family

ID=11968371

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1832285A Granted JPS61177542A (ja) 1985-02-01 1985-02-01 符号補数・符号絶対値併用加減算装置

Country Status (1)

Country Link
JP (1) JPS61177542A (cg-RX-API-DMAC7.html)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6225325A (ja) * 1985-07-25 1987-02-03 Fujitsu Ltd 絶対値数加減算回路

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5930143A (ja) * 1982-08-11 1984-02-17 Hitachi Ltd 演算処理方式
JPS5999542A (ja) * 1982-11-30 1984-06-08 Fujitsu Ltd 演算回路

Also Published As

Publication number Publication date
JPS61177542A (ja) 1986-08-09

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