JPH0466688B2 - - Google Patents
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- Publication number
- JPH0466688B2 JPH0466688B2 JP59156161A JP15616184A JPH0466688B2 JP H0466688 B2 JPH0466688 B2 JP H0466688B2 JP 59156161 A JP59156161 A JP 59156161A JP 15616184 A JP15616184 A JP 15616184A JP H0466688 B2 JPH0466688 B2 JP H0466688B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- firing
- substrate
- ceramic
- ceramic substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000000758 substrate Substances 0.000 claims description 48
- 238000000034 method Methods 0.000 claims description 43
- 239000000919 ceramic Substances 0.000 claims description 42
- 238000010304 firing Methods 0.000 claims description 32
- 229910052802 copper Inorganic materials 0.000 claims description 17
- 229910052726 zirconium Inorganic materials 0.000 claims description 14
- 239000006023 eutectic alloy Substances 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 230000005496 eutectics Effects 0.000 claims description 8
- 239000010409 thin film Substances 0.000 claims description 8
- 230000008018 melting Effects 0.000 claims description 7
- 238000002844 melting Methods 0.000 claims description 7
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 5
- 229910052574 oxide ceramic Inorganic materials 0.000 claims description 5
- 239000011224 oxide ceramic Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 4
- 238000001704 evaporation Methods 0.000 claims 1
- 239000010949 copper Substances 0.000 description 58
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 8
- 238000009713 electroplating Methods 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 239000010408 film Substances 0.000 description 7
- 239000011521 glass Substances 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 4
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 3
- 239000005751 Copper oxide Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000003153 chemical reaction reagent Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 229910000431 copper oxide Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000011261 inert gas Substances 0.000 description 3
- 239000007791 liquid phase Substances 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 238000007872 degassing Methods 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000005211 surface analysis Methods 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- 229910000505 Al2TiO5 Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910017309 Mo—Mn Inorganic materials 0.000 description 1
- 229910000905 alloy phase Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005238 degreasing Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- AABBHSMFGKYLKE-SNAWJCMRSA-N propan-2-yl (e)-but-2-enoate Chemical compound C\C=C\C(=O)OC(C)C AABBHSMFGKYLKE-SNAWJCMRSA-N 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 239000006104 solid solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
Landscapes
- Laminated Bodies (AREA)
- Ceramic Products (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
〔技術分野〕
この発明は、アルミナ等の酸化物系セラミツク
ス基板上にCu層は形成してなり、電子回路板あ
るいはその放熱板として用いられるセラミツクス
回路板の製法に関する。
〔背景技術〕
従来、電子回路用等の回路板には、ハイブリツ
ドIC等に見られるように、プラスチツクス基板
にCu層を形成したものや、金属基板に絶縁層を
介してCu層を形成したもの等がある。しかしな
がら、昨今の電子回路の軽薄短小化に伴い、電子
部品の高密度実装化、多層実装化、温度や湿度変
化に対する寸法安定性や対熱温度向上に見られる
高信頼性化等が求められるようになり、これらの
観点から熱伝導率が大きく、かつ熱寸法変化が小
さいセラミツクス基板の利用が求められるように
なつてきた。そこで、セラミツクス基板<一般に
は酸化物系セラミツクスのうちのアルミナ基板>
上に回路を形成する様々な方法が試みられるに至
つた。
ここで、現在提案または実際に行われている5
つの方法について説明する。第1は、Ag−Pdペ
ースト法あるいはAuペースト法である。これは
Ag,PdあるいはAuの金属微粉末をガラスフリツ
ト、有機系ビヒクルと混合しペースト化し、セラ
ミツクス基板上にスクリーン印刷等した後、ガラ
スフリツトがセラミツクス基板に溶融接合する温
度で焼成し、回路を形成するものである。この方
法には、せいぜい70〜100μmと太い線幅の回路
しか形成できず、フアイン・パターンが困難であ
る、回路の抵抗が大きいので、微細配線に不向
きである、回路表面にガラス層が出来易く、そ
のためはんだ付着性が劣り、不良および使用時の
故障をおこしやすい等の欠点がある。第2は、
Cuペースト法であり、Cuおよび微量の銅酸化物
とガラスフリツト、有機ビヒクルを混合しペース
ト化し、セラミツクス基板上にスクリーン印刷等
を行い、これをN2やArの不活性ガス雰囲気中で
ガラスフリツトがセラミツクス基板に溶融接合す
る温度で焼成し、回路を形成するものである。こ
の方法の欠点は、回路の抵抗が大きいので、フ
アイン・パターンに向かない、雰囲気焼成が必
要で、焼成コストがかさむ、第1の方法同様ガ
ラス層によりはんだ付着性が劣る等である。第3
の方法は、高融点金属法(テレフンケン法)で、
これはMoあるいはMo−Mnをペースト化しセラ
ミツクス基板上に印刷し、加湿水素あるいは加湿
フオーシングガス(H2/N2)中で1300〜1700℃
でMn+H2O→MnO+H2の反応をおこさせる。
すると、生成したMnOがセラミツクス粒界のガ
ラス相へ溶解し、ガラス粘度を低下させ、セラミ
ツクス表面にメタライジング層を形成するので、
この表面にNiメツキを施し、ろう材でCu板を接
合し、回路を形成するものである。この方法で
は、密着力は強化されるが、セラミツクス粒界
が侵食されるので、セラミツクスの強度が低下す
る、セラミツクス基板と導電層との間に、密着
拡散層およびMo,Mn層等の高抵抗層が生じる
ので、高周波特性が悪い等の欠点がある。第4
は、W,Mo法であり、W,Moスラリーで焼成
前のアルミナグリーンセラミツクスシート上に回
路を描き、還元雰囲気中で一体に焼成するもので
ある。この方法も、回路の抵抗が大きいので、フ
アイン・パターンには不向きである。
アルミナ基板上に回路を形成する方法として
は、特に他の導体材料に比べて、導電性、基板と
の結合力、はんだ付着性等にすぐれ、その上廉価
なCu導体を基板上に接合して回路を形成する方
法への要請が高い。しかしながら、セラミツクス
とCuとの熱膨張率の違いにより強固な接合は、
なかなか難かしく、そこで試みられているのが、
第5の酸化銅法である。これは、Cuとセラミツ
クス基板を酸素を微量含有する雰囲気中で焼成す
る、Cu板表面を酸化させセラミツクス基板と接
触させて不活性ガス雰囲気中で焼成する、あるい
はタフピツチ銅等酸素を含有するCu板を不活性
ガス雰囲気中で焼成する等して、Cuとセラミツ
クスを反応性雰囲気中で加熱し、共晶融体を生成
して冷却することにより、セラミツクス基板に
Cu板を接合する方法である。これらの方法は、
特公57−13515、特開50−132022、特開52−
37914、特開53−77212、特開57−82181、特開57
−36892、特開58−67095、特開58−67096、特開
58−137285、特開59−13677、特開59−3076等に
見られる。この酸化銅法では、1回の操作で強力
な接着力が得られ、界面は低抵抗層という長所は
あるが、接合面に空洞や泡を生じ易い、Cu
の融点1083℃と共晶温度1065℃との狭い温度間に
焼成温度範囲が限定され、焼成時間も5〜60分で
あるため、焼成条件が厳しい、薄膜を得ること
が困難であるため、フアイン・パターンに不向き
である、焼成時にパターンが動き、回路位置が
不安定である等の欠点がある。
〔発明の目的〕
この発明は、上記のような現状に鑑みてなされ
たものであり、酸化物系セラミツクス基板とCu
導体との接合に際し、密度強度が高くはんだ付着
性が良好で低抵抗導電層であり、接合面に空洞や
泡が生じることなく、しかも焼成条件がゆるやか
になり、コストの低減を図ることのできるセラミ
ツクス回路板の製法を提供するものである。
〔発明の開示〕
この発明は、上記の目的を達成するために、酸
化物系セラミツクス基板にCu層を接合するため
にあたり、Cu層とセラミツクス基板との間に、
中間接合層として、Tiおよび/またはZrとCuと
の共晶合金層を形成する方法であり、中間接合層
となるTiおよび/またはZrとCuを薄膜形成した
後、焼成することにより共晶合金層を形成するこ
とを特徴とするセラミツクス回路板の製法をその
要旨としている。すなわち、この発明は、酸化物
系セラミツクス中の酸素と結合しやすく、高温度
での活性の非常に高い金属であるTi,Zrをセラ
ミツクス基板とCu層との間に介在させて、基板
との密着性を計ると同時に、Cuとの共晶合金層
(共晶組成相)を生成させ、この液相によるぬれ
効果を利用して接着度の強化を図るものである。
以下にこれを詳しく説明する。
まず、セラミツクス基板上にTiおよび/また
はZrの薄い被膜を形成する。この被膜は、基板
の微細構造に密着して形成されることが望まし
く、PVD法、CVD法や等により蒸着形成される
のが望ましい。この方法により基板と密着した被
膜を形成することができるので、焼成後も泡や空
洞を界面に生じることがない。次に、その上に回
路として必要な厚みのCu層を形成する。通常、
回路としてのCu層は、3μm以上の厚みが必要で
あるため、湿式の電気メツキか化学メツキによつ
て形成することが適当であるが、薄いものであれ
ば、PVDやCVD法によつて形成してもよい。
その後上記セラミツクス基板を、Tiおよび/
またはZrとCuとの共晶温度以上で、かつCuの融
点以下で焼成する。焼成はN2等の不活性ガス雰
囲気中で行うことが好ましい。この発明の焼成条
件では、Cuの融点とこれらの共晶温度との間に
は約300℃の幅ができ、管理が非常に容易となる。
この焼成時には、セラミツクス基板とCu層との
間に、Cuと各金属との共晶合金相が液相の中間
接合層として生成し、基板とCu層との界面をよ
くぬらして、両者の接着強度を増加させる。この
ようにして、セラミツクス基板上に回路となる
Cu層を〓間なく形成することができるのである。
第1層たる被膜(中間接合層)の厚みは、通
常、200Å程度の極めて薄いものであり、界面の
ごくわずかな厚みにCuとの固溶体を作るだけで
あるので、回路の抵抗値はCuと同様に極めて小
さくおさえることができる。実際には、Cuのシ
ート抵抗3mΩ/□に対し、5mΩ/□とAg程
度の小ささである。
上記の実施例の他に、まず基板上にCuの薄い
被膜をPVD法、CVD法等の蒸着法で微細構造に
密着させて形成し、つぎに同様の方法でTiまた
は/およびZrの薄い被膜を形成し、その後Cu層
を形成した後、前述の焼成条件で焼成を行つて
も、同様に密着性のよいセラミツクス回路板が製
造される。
あるいはまた、PVD,CVD法等によりCuとTi
および/またはZrを同時に蒸着してCuとTiおよ
び/またはZrとの混合被膜を形成し、つぎにCu
層を形成した後、前述の焼成条件で同様に焼成し
てもよい。この場合には、最もよく液相化がすす
み、最も強力な密着力と品質安定性の良いセラミ
ツクス回路板が製造される。なお、Cu層を電気
メツキ法で形成する場合において、第1層がTi
および/またはZrのみの膜であるときは、その
上もしくは下に予め1000Å程度のCu薄膜を形成
しておくのが普通である。
つぎに、この発明にかかるセラミツクス回路板
の製法の実施例を、比較例と併せて説明する。
(実施例 1)
50×50×0.635(mm)のトリクレン脱脂を行つた
96%純度のAl2O3基板上に、純度99.9%のTi(真
空蒸着用の脱ガス試薬)を蒸着法により200Åの
厚みに蒸着し、つぎに純度99.9%のCu(真空蒸着
用の脱ガス試薬)を同様の方法により1000Åの厚
みに蒸着した。その上に電気メツキ法により
70μmの厚みのCu層を形成した。つづいて上記
Al2O3基板をN2気流中で1000℃,10分間焼成し
た。なお、蒸着法は、基板に加熱を行わず、すべ
て100℃以下の表面温度条件下で行われた。
(実施例 2)
実施例1で用いたものと同じAl2O3基板上に、
実施例1と同様の方法で、純度99.9%のTiと純度
99.9%のZrを200Åの厚みに同時に蒸着した。こ
の上に実施例1と同じ方法により純度99.9%のCu
を1000Åの厚みに蒸着した。その上に電気メツキ
法により70μmの厚みのCu層を形成し、実施例1
と同様の焼成条件で焼成した。
(実施例 3)
実施例1に用いたものと同様のAl2O3基板上に
純度99.9%のCuをスパツタリング法により1000Å
の厚みに蒸着した。つぎに純度99.9%のZrをスパ
ツタリング法を用いて200Åの厚みに蒸着し、そ
の上に電気メツキ法により70μmのCu層を形成
し、実施例1と同様の焼成条件で焼成した。
(実施例 4)
実施例1に用いたものと同様のAl2O3基板上
に、実施例1と同じ方法で、純度99.9%のTiと、
純度99.9%のCuを1000Åの厚みで同時蒸着した。
螢光X線、XMAの面分析によりCuとTiとの混
合金属膜ができていることを確認した。その後、
その上に、電気メツキ法によつて70μmの厚みの
Cu層を形成し、実施例1と同様の焼成条件で焼
成した。
(実施例 5)
実施例1に用いたのと同様のAl2O3基板上に、
実施例1と同様の方法で、純度99.9%のTi、純度
99.9%Zrおよび純度99.9%のCuを1000Åの厚みに
同時蒸着した。これを螢光X線、XMAの面分析
によりCuとTi,Zrの混合金属膜ができているこ
とを確認した。その後、その上に、電気メツキ法
によつて70μmの厚みのCu層を形成し、実施例1
と同様の焼成条件で焼成した。
(比較例 1)
実施例1に用いたのと同様のAl2O3基板上に、
1000Å厚にCuを蒸着し、これを極として、電気
メツキ法により70μmの厚みにCu層を形成し、実
施例1と同じ条件で焼成した。
(比較例 2)
実施例1で用いたのと同じAl2O3基板上に
20μmのTi箔と50μmのCu箔を重ね、上からチタ
ン酸アルミニウム焼結体で押え、加圧してN2気
流中で1050℃、3時間焼成して、基板上に箔を接
合した。
つぎに、上記実施例1〜5および比較例1,2
により得られた基板の中央部を10mm幅に切り出
し、ピール強度の測定を行つた。それにより得ら
れた結果を、焼成前のそれと併せて、下記の表に
示す。
[Technical Field] The present invention relates to a method for manufacturing a ceramic circuit board, which is formed by forming a Cu layer on an oxide-based ceramic substrate such as alumina, and is used as an electronic circuit board or a heat sink thereof. [Background technology] Conventionally, circuit boards for electronic circuits, etc., have either a Cu layer formed on a plastic substrate or a Cu layer formed on a metal substrate with an insulating layer interposed between them, as seen in hybrid ICs. There are things etc. However, as electronic circuits have become lighter, thinner, shorter, and smaller in recent years, there has been a demand for higher reliability, such as higher density mounting of electronic components, multilayer mounting, dimensional stability against changes in temperature and humidity, and improved heat resistance. From these viewpoints, there has been a demand for the use of ceramic substrates that have high thermal conductivity and small thermal dimensional changes. Therefore, ceramic substrates (generally alumina substrates of oxide ceramics)
Various methods of forming circuits thereon have been tried. Here are the 5 currently proposed or actually implemented
We will explain two methods. The first is the Ag-Pd paste method or the Au paste method. this is
A circuit is formed by mixing Ag, Pd, or Au metal fine powder with glass frit and an organic vehicle to form a paste, screen printing it on a ceramic substrate, and then firing it at a temperature that melts and bonds the glass frit to the ceramic substrate. be. This method can only form circuits with a thick line width of 70 to 100 μm at most, making it difficult to form fine patterns.The circuit has high resistance, making it unsuitable for fine wiring.A glass layer is likely to form on the circuit surface. Therefore, there are disadvantages such as poor solder adhesion and a tendency to cause defects and failures during use. The second is
This is a Cu paste method, in which Cu and a small amount of copper oxide, glass frit, and an organic vehicle are mixed to form a paste, which is then screen printed onto a ceramic substrate. It is fired at a temperature that allows it to be melted and bonded to the substrate to form a circuit. The disadvantages of this method are that it is not suitable for fine patterns because the circuit resistance is large, that it requires atmosphere firing, which increases the firing cost, and as with the first method, the solder adhesion is poor due to the glass layer. Third
The method is the high melting point metal method (Telefunken method),
This is made by printing Mo or Mo-Mn into a paste on a ceramic substrate and heating it at 1300 to 1700°C in humidified hydrogen or humidified facing gas (H 2 /N 2 ).
The reaction of Mn + H 2 O → MnO + H 2 occurs.
Then, the generated MnO dissolves into the glass phase at the ceramic grain boundaries, lowering the glass viscosity and forming a metallizing layer on the ceramic surface.
This surface is plated with Ni and bonded to a Cu plate using a brazing material to form a circuit. In this method, the adhesion is strengthened, but the strength of the ceramic is reduced because the ceramic grain boundaries are eroded. Since layers are formed, there are drawbacks such as poor high frequency characteristics. Fourth
This is the W, Mo method, in which a circuit is drawn on an alumina green ceramic sheet before firing using a W, Mo slurry, and the circuit is fired as a unit in a reducing atmosphere. This method is also unsuitable for fine patterns because the circuit resistance is large. One way to form a circuit on an alumina substrate is to bond a Cu conductor onto the substrate, which has excellent conductivity, bonding strength with the substrate, solder adhesion, etc., and is inexpensive compared to other conductive materials. There is a high demand for methods for forming circuits. However, due to the difference in thermal expansion coefficient between ceramics and Cu, strong bonding is difficult.
It is quite difficult, and what is being attempted is
This is the fifth copper oxide method. This can be done by firing Cu and a ceramic substrate in an atmosphere containing a small amount of oxygen, by oxidizing the surface of the Cu plate and bringing it into contact with the ceramic substrate and firing it in an inert gas atmosphere, or by firing a Cu plate containing oxygen such as tough pitch copper. By heating Cu and ceramics in a reactive atmosphere, such as by firing in an inert gas atmosphere, a eutectic melt is generated and then cooled to form a ceramic substrate.
This is a method of joining Cu plates. These methods are
JP57-13515, JP50-132022, JP52-
37914, JP 53-77212, JP 57-82181, JP 57
−36892, JP 58-67095, JP 58-67096, JP
58-137285, JP-A No. 59-13677, JP-A No. 59-3076, etc. This copper oxide method has the advantage of providing strong adhesion with a single operation and having a low-resistance layer at the interface.
The firing temperature range is limited between the melting point of 1083°C and the eutectic temperature of 1065°C, and the firing time is 5 to 60 minutes, so the firing conditions are harsh and it is difficult to obtain a thin film.・There are disadvantages such as it is not suitable for patterns, the pattern moves during firing, and the circuit position is unstable. [Purpose of the Invention] This invention was made in view of the above-mentioned current situation, and relates to an oxide ceramic substrate and a Cu
When bonded to a conductor, it is a low-resistance conductive layer with high density and strength, good solder adhesion, and does not create cavities or bubbles on the bonding surface. Moreover, the firing conditions are gentler, reducing costs. A method for manufacturing a ceramic circuit board is provided. [Disclosure of the Invention] In order to achieve the above object, the present invention is directed to bonding a Cu layer to an oxide-based ceramic substrate.
This is a method of forming a eutectic alloy layer of Ti and/or Zr and Cu as the intermediate bonding layer. After forming a thin film of Ti and/or Zr and Cu as the intermediate bonding layer, the eutectic alloy is formed by firing. The gist of this paper is a method for manufacturing ceramic circuit boards characterized by the formation of layers. In other words, this invention uses Ti and Zr, which are metals that easily combine with oxygen in oxide ceramics and have very high activity at high temperatures, to be interposed between the ceramic substrate and the Cu layer, thereby improving the bond between the ceramic substrate and the Cu layer. At the same time as measuring adhesion, a eutectic alloy layer (eutectic composition phase) with Cu is generated, and the wetting effect of this liquid phase is used to strengthen the adhesion. This will be explained in detail below. First, a thin film of Ti and/or Zr is formed on a ceramic substrate. This film is preferably formed in close contact with the fine structure of the substrate, and is preferably formed by vapor deposition using a PVD method, a CVD method, or the like. This method makes it possible to form a film that is in close contact with the substrate, so that no bubbles or cavities are generated at the interface even after firing. Next, a Cu layer of the thickness required for the circuit is formed on top of it. usually,
The Cu layer used as a circuit requires a thickness of 3 μm or more, so it is appropriate to form it by wet electroplating or chemical plating, but if it is thin, it can be formed by PVD or CVD. You may. After that, the above ceramic substrate was coated with Ti and/or
Alternatively, it is fired at a temperature higher than the eutectic temperature of Zr and Cu and lower than the melting point of Cu. The firing is preferably performed in an inert gas atmosphere such as N 2 . Under the firing conditions of this invention, there is a width of about 300°C between the melting point of Cu and these eutectic temperatures, which makes management very easy.
During this firing, a eutectic alloy phase of Cu and each metal is formed as a liquid phase intermediate bonding layer between the ceramic substrate and the Cu layer, and thoroughly wets the interface between the substrate and the Cu layer to bond them together. Increase strength. In this way, a circuit is formed on the ceramic substrate.
A Cu layer can be formed quickly. The thickness of the first layer (intermediate bonding layer) is usually extremely thin, about 200 Å, and only forms a solid solution with Cu in a very small thickness at the interface, so the resistance value of the circuit is lower than that of Cu. Similarly, it can be kept extremely small. In reality, the sheet resistance of Cu is 5 mΩ/□, which is about as small as that of Ag. In addition to the above embodiments, first a thin film of Cu is formed on the substrate by a vapor deposition method such as PVD or CVD in close contact with the microstructure, and then a thin film of Ti or/and Zr is formed by the same method. After forming a Cu layer, a ceramic circuit board with good adhesion can be manufactured even if firing is performed under the above-mentioned firing conditions. Alternatively, Cu and Ti can be formed by PVD, CVD, etc.
and/or Zr are simultaneously deposited to form a mixed film of Cu, Ti, and/or Zr, and then Cu
After forming the layer, it may be fired in the same manner under the above-mentioned firing conditions. In this case, the liquid phase progresses best, and a ceramic circuit board with the strongest adhesion and quality stability is produced. Note that when forming the Cu layer by electroplating, the first layer is Ti.
When the film is made only of Zr and/or Zr, it is common to form a Cu thin film of about 1000 Å on or below it in advance. Next, an embodiment of the method for manufacturing a ceramic circuit board according to the present invention will be described together with a comparative example. (Example 1) Triclean degreasing of 50 x 50 x 0.635 (mm) was performed.
On a 96% pure Al 2 O 3 substrate, 99.9% pure Ti (degassing reagent for vacuum evaporation) was deposited to a thickness of 200 Å by vapor deposition method, and then 99.9% pure Cu (degassing reagent for vacuum evaporation) was deposited to a thickness of 200 Å. A gas reagent) was deposited to a thickness of 1000 Å using the same method. On top of that, by electroplating method
A Cu layer with a thickness of 70 μm was formed. Continued above
The Al 2 O 3 substrate was fired at 1000°C for 10 minutes in a N 2 stream. Note that the vapor deposition method was performed without heating the substrate, and under conditions of a surface temperature of 100° C. or less. (Example 2) On the same Al 2 O 3 substrate used in Example 1,
Using the same method as in Example 1, 99.9% pure Ti and
99.9% Zr was simultaneously deposited to a thickness of 200 Å. On top of this, Cu with a purity of 99.9% was added by the same method as in Example 1.
was deposited to a thickness of 1000 Å. On top of that, a 70 μm thick Cu layer was formed by electroplating, and Example 1
It was fired under the same firing conditions. (Example 3) Cu with a purity of 99.9% was deposited to a thickness of 1000 Å on an Al 2 O 3 substrate similar to that used in Example 1 by sputtering.
It was deposited to a thickness of . Next, Zr with a purity of 99.9% was deposited to a thickness of 200 Å using a sputtering method, and a 70 μm Cu layer was formed thereon by an electroplating method, and fired under the same firing conditions as in Example 1. (Example 4) On an Al 2 O 3 substrate similar to that used in Example 1, Ti with a purity of 99.9% was deposited using the same method as in Example 1.
Cu with a purity of 99.9% was simultaneously deposited to a thickness of 1000 Å.
Fluorescent X-ray and XMA surface analysis confirmed that a mixed metal film of Cu and Ti was formed. after that,
On top of that, a 70μm thick layer was coated by electroplating.
A Cu layer was formed and fired under the same firing conditions as in Example 1. (Example 5) On an Al 2 O 3 substrate similar to that used in Example 1,
In the same manner as in Example 1, Ti with a purity of 99.9%, purity
99.9% Zr and 99.9% pure Cu were co-deposited to a thickness of 1000 Å. It was confirmed by fluorescent X-ray and XMA surface analysis that a mixed metal film of Cu, Ti, and Zr was formed. Thereafter, a Cu layer with a thickness of 70 μm was formed thereon by electroplating, and Example 1
It was fired under the same firing conditions. (Comparative Example 1) On the same Al 2 O 3 substrate as used in Example 1,
Cu was deposited to a thickness of 1000 Å, and using this as a pole, a Cu layer was formed to a thickness of 70 μm by electroplating, and fired under the same conditions as in Example 1. (Comparative Example 2) On the same Al 2 O 3 substrate used in Example 1
A 20 μm Ti foil and a 50 μm Cu foil were stacked, pressed down with an aluminum titanate sintered body from above, and baked at 1050° C. for 3 hours in a N 2 stream under pressure to bond the foils onto the substrate. Next, the above Examples 1 to 5 and Comparative Examples 1 and 2
The center part of the substrate obtained was cut out to a width of 10 mm, and the peel strength was measured. The results obtained are shown in the table below, together with the results before firing.
この発明は、セラミツクス基板とCu層との間
の接合層をTiおよび/またはZrとCuとの共晶合
金層で形成する際に、中間接合層となるTiおよ
び/またはZrとCuを薄膜形成した後、焼成する
ことにより共晶合金層を形成するようにしている
ので、極めて密着力が高く、はんだ付着性の良好
なセラミツクス回路板を製造することができる。
CuとTiおよび/またはZrとを同時に蒸着して、
これらの混合金属膜を形成し、焼成する方法は、
特に密着力にすぐれ、かつ密着層の幅も一定とな
り、品質安定性の高い製品を提供することができ
るのである。
This invention involves forming a thin film of Ti and/or Zr and Cu to serve as an intermediate bonding layer when forming a bonding layer between a ceramic substrate and a Cu layer using a eutectic alloy layer of Ti and/or Zr and Cu. After that, a eutectic alloy layer is formed by firing, so that a ceramic circuit board with extremely high adhesion and good solder adhesion can be manufactured.
By simultaneously depositing Cu, Ti and/or Zr,
The method of forming and firing these mixed metal films is as follows:
In particular, it has excellent adhesion and the width of the adhesion layer is constant, making it possible to provide products with high quality stability.
Claims (1)
るにあたり、Cu層とセラミツクス基板との間に、
中間接合層として、Tiおよび/またはZrとCuと
の共晶合金層を形成する方法であり、中間接合層
となるTiおよび/またはZrとCuを薄膜形成した
後、焼成することにより共晶合金層を形成するこ
とを特徴とするセラミツクス回路板の製法。 2 セラミツクス基板上にTiおよび/またはZr
を蒸着した後Cu層を形成し、これをTiおよび/
またはZrとCuとの共晶温度以上でかつCuの融点
以下の温度で焼成することにより共晶合金層を形
成する特許請求の範囲第1項記載のセラミツクス
回路板の製法。 3 セラミツクス基板上にCuを蒸着した後、Ti
および/またはZrを蒸着し、その上にCu層を形
成し、これをTiおよび/またはZrとCuとの共晶
温度以上でかつCuの融点以下の温度で焼成する
ことにより共晶合金層を形成する特許請求の範囲
第1項記載のセラミツクス回路板の製法。 4 セラミツクス基板上にCuとTiおよび/また
はZrを同時に蒸着した後、その上にCu層を形成
し、これをTiおよび/またはZrとCuとの共晶温
度以上でかつCuの融点以下の温度で焼成するこ
とにより共晶合金層を形成する特許請求の範囲第
1項記載のセラミツクス回路板の製法。 5 酸化物系セラミツクス基板がアルミナ基板で
ある特許請求の範囲第1項から第4項までのいず
れかに記載のセラミツクス回路板の製法。[Claims] 1. When bonding a Cu layer to an oxide ceramic substrate, between the Cu layer and the ceramic substrate,
This is a method of forming a eutectic alloy layer of Ti and/or Zr and Cu as the intermediate bonding layer. After forming a thin film of Ti and/or Zr and Cu as the intermediate bonding layer, the eutectic alloy is formed by firing. A method for manufacturing a ceramic circuit board characterized by forming layers. 2 Ti and/or Zr on ceramic substrate
A Cu layer is formed after evaporating Ti and/or
The method for manufacturing a ceramic circuit board according to claim 1, wherein a eutectic alloy layer is formed by firing at a temperature higher than the eutectic temperature of Zr and Cu and lower than the melting point of Cu. 3 After depositing Cu on the ceramic substrate, Ti
A eutectic alloy layer is formed by depositing Zr and/or Zr, forming a Cu layer thereon, and firing this at a temperature higher than the eutectic temperature of Ti and/or Zr and Cu and lower than the melting point of Cu. A method for manufacturing a ceramic circuit board according to claim 1. 4 After simultaneously depositing Cu, Ti and/or Zr on a ceramic substrate, a Cu layer is formed thereon, and this is heated at a temperature above the eutectic temperature of Ti and/or Zr and Cu and below the melting point of Cu. A method for manufacturing a ceramic circuit board according to claim 1, wherein a eutectic alloy layer is formed by firing the ceramic circuit board. 5. The method for manufacturing a ceramic circuit board according to any one of claims 1 to 4, wherein the oxide ceramic substrate is an alumina substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15616184A JPS6132752A (en) | 1984-07-25 | 1984-07-25 | Manufacture of ceramics circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15616184A JPS6132752A (en) | 1984-07-25 | 1984-07-25 | Manufacture of ceramics circuit board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6132752A JPS6132752A (en) | 1986-02-15 |
JPH0466688B2 true JPH0466688B2 (en) | 1992-10-26 |
Family
ID=15621679
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15616184A Granted JPS6132752A (en) | 1984-07-25 | 1984-07-25 | Manufacture of ceramics circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6132752A (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0273227A3 (en) * | 1986-12-22 | 1989-01-25 | Kalman F. Zsamboky | A method of improving bond strength between a metal layer and a non-metallic substrate |
JPS63254031A (en) * | 1987-04-10 | 1988-10-20 | 昭和電工株式会社 | Manufacture of circuit substrate |
JPH0292872A (en) * | 1988-09-28 | 1990-04-03 | Kyocera Corp | Bonding between ceramic material and copper material |
JP3495052B2 (en) * | 1992-07-15 | 2004-02-09 | 株式会社東芝 | Metallized body and manufacturing method thereof |
DE102020111700A1 (en) * | 2020-04-29 | 2021-11-04 | Rogers Germany Gmbh | Carrier substrate and method for producing a carrier substrate |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5195777A (en) * | 1975-02-06 | 1976-08-21 | HANDO TAIYOKI | |
JPS5645318A (en) * | 1979-09-11 | 1981-04-25 | Hitachi Metals Ltd | Combined milling tool and preparation thereof |
JPS593077A (en) * | 1982-06-29 | 1984-01-09 | 株式会社東芝 | Method of bonding ceramic member and metal |
-
1984
- 1984-07-25 JP JP15616184A patent/JPS6132752A/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5195777A (en) * | 1975-02-06 | 1976-08-21 | HANDO TAIYOKI | |
JPS5645318A (en) * | 1979-09-11 | 1981-04-25 | Hitachi Metals Ltd | Combined milling tool and preparation thereof |
JPS593077A (en) * | 1982-06-29 | 1984-01-09 | 株式会社東芝 | Method of bonding ceramic member and metal |
Also Published As
Publication number | Publication date |
---|---|
JPS6132752A (en) | 1986-02-15 |
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