JPH0465464U - - Google Patents

Info

Publication number
JPH0465464U
JPH0465464U JP1990109011U JP10901190U JPH0465464U JP H0465464 U JPH0465464 U JP H0465464U JP 1990109011 U JP1990109011 U JP 1990109011U JP 10901190 U JP10901190 U JP 10901190U JP H0465464 U JPH0465464 U JP H0465464U
Authority
JP
Japan
Prior art keywords
insulating substrate
conductive pattern
led chip
molded
view
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1990109011U
Other languages
English (en)
Other versions
JP2521021Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990109011U priority Critical patent/JP2521021Y2/ja
Publication of JPH0465464U publication Critical patent/JPH0465464U/ja
Application granted granted Critical
Publication of JP2521021Y2 publication Critical patent/JP2521021Y2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】
第１図は本考案に係るモジユールタイプＬＥＤ
のモールド構造の一実施例を示す第２図の−
線断面図、第２図は平面図、第３図は正面図、第
４図は第３図の−線断面図、第５図はモール
ド樹脂のモールド方法を示す断面図、第６図は本
考案の他の実施例を示す断面図、第７図は本考案
の更に他の実施例を示す断面図、第８図は従来の
モジユールタイプＬＥＤのモールド構造を示す第
９図の―線断面図、第９図は平面図、第１０
図は第９図のＸ―Ｘ線断面図である。 １……絶縁基板、２……光学反射用凹部、３…
…導電パターン、４……ＬＥＤチツプ、５……金
線、６……モールド樹脂、７……樹脂注入用孔、
１１……段差面、１２……モールド面、１４……
モールド金型、２０……電極取出し用孔。

Claims (1)

    【実用新案登録請求の範囲】
  1. 絶縁基板上に導電パターンを形成し、その上に
    ＬＥＤチツプを実装してワイヤボンデイングし、
    かつ前記ＬＥＤチツプを透明樹脂によつてモール
    ドしてなり、前記導電パターンのうち外部電極取
    出し部は前記樹脂から外部に突出する部分が前記
    絶縁基板のモールド面以外の面にまで延設されて
    いることを特徴とするモジユールタイプＬＥＤの
    モールド構造。
JP1990109011U 1990-10-19 1990-10-19 モジユールタイプｌｅｄのモールド構造 Expired - Fee Related JP2521021Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990109011U JP2521021Y2 (ja) 1990-10-19 1990-10-19 モジユールタイプｌｅｄのモールド構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990109011U JP2521021Y2 (ja) 1990-10-19 1990-10-19 モジユールタイプｌｅｄのモールド構造

Publications (2)

Publication Number Publication Date
JPH0465464U true JPH0465464U (ja) 1992-06-08
JP2521021Y2 JP2521021Y2 (ja) 1996-12-25

Family

ID=31856166

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990109011U Expired - Fee Related JP2521021Y2 (ja) 1990-10-19 1990-10-19 モジユールタイプｌｅｄのモールド構造

Country Status (1)

Country Link
JP (1) JP2521021Y2 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008544537A (ja) * 2005-06-24 2008-12-04 エルジー イノテック カンパニー リミテッド 発光素子パッケージ及び発光素子パッケージの製造方法
JP2009088520A (ja) * 2007-09-27 2009-04-23 Samsung Electro Mech Co Ltd 発光素子パッケージの製造方法
JP2017175024A (ja) * 2016-03-24 2017-09-28 パナソニックＩｐマネジメント株式会社 発光モジュール及び照明装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7763478B2 (en) * 2006-08-21 2010-07-27 Cree, Inc. Methods of forming semiconductor light emitting device packages by liquid injection molding

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5257731A (en) * 1975-11-06 1977-05-12 Matsushita Electric Ind Co Ltd Light source for information reading element
JPS5257730A (en) * 1975-11-06 1977-05-12 Matsushita Electric Ind Co Ltd Light source for information reading element

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5257731A (en) * 1975-11-06 1977-05-12 Matsushita Electric Ind Co Ltd Light source for information reading element
JPS5257730A (en) * 1975-11-06 1977-05-12 Matsushita Electric Ind Co Ltd Light source for information reading element

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008544537A (ja) * 2005-06-24 2008-12-04 エルジー イノテック カンパニー リミテッド 発光素子パッケージ及び発光素子パッケージの製造方法
US8178894B2 (en) 2005-06-24 2012-05-15 Lg Innotek Co., Ltd. Light emitting device package and method of fabricating the same
US8395178B2 (en) 2005-06-24 2013-03-12 Lg Innotek Co., Ltd. Light emitting device package and method of fabricating the same
US9564567B2 (en) 2005-06-24 2017-02-07 Lg Innotek Co., Ltd. Light emitting device package and method of fabricating the same
JP2009088520A (ja) * 2007-09-27 2009-04-23 Samsung Electro Mech Co Ltd 発光素子パッケージの製造方法
US8202746B2 (en) 2007-09-27 2012-06-19 Samsung Led Co., Ltd. Method of manufacturing LED package for formation of molding member
JP2017175024A (ja) * 2016-03-24 2017-09-28 パナソニックＩｐマネジメント株式会社 発光モジュール及び照明装置

Also Published As

Publication number Publication date
JP2521021Y2 (ja) 1996-12-25

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Legal Events

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LAPS Cancellation because of no payment of annual fees