JPH0465441U - - Google Patents

Info

Publication number
JPH0465441U
JPH0465441U JP10994390U JP10994390U JPH0465441U JP H0465441 U JPH0465441 U JP H0465441U JP 10994390 U JP10994390 U JP 10994390U JP 10994390 U JP10994390 U JP 10994390U JP H0465441 U JPH0465441 U JP H0465441U
Authority
JP
Japan
Prior art keywords
lead
semiconductor device
conductive adhesive
electrically connected
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10994390U
Other languages
Japanese (ja)
Other versions
JP2513872Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990109943U priority Critical patent/JP2513872Y2/en
Publication of JPH0465441U publication Critical patent/JPH0465441U/ja
Application granted granted Critical
Publication of JP2513872Y2 publication Critical patent/JP2513872Y2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はこの考案の実施例を示す半導体装置中
間構体平面図、第２図は第１図のＢ−Ｂ線に沿う
断面図、第３図はこの考案の他の実施例を示す要
部側断面図、第４図は従来の半導体装置中間構体
を示す平面図、第５図は第４図のＡ−Ａ線に沿う
断面図である。 １ｄ……リード、３……半導体ペレツト、３ａ
……電極、５……導電性接着材層。 FIG. 1 is a plan view of an intermediate structure of a semiconductor device showing an embodiment of this invention, FIG. 2 is a sectional view taken along line B-B in FIG. 1, and FIG. 3 is a main part showing another embodiment of this invention. 4 is a plan view showing a conventional semiconductor device intermediate structure, and FIG. 5 is a sectional view taken along line A--A in FIG. 4. 1d...Lead, 3...Semiconductor pellet, 3a
... Electrode, 5 ... Conductive adhesive layer.

Claims (1)

【実用新案登録請求の範囲】 (1) 半導体ペレツト上の電極とリードとを電気
的に接続した半導体装置において、上記リードの
電気的接続部に導電性接着材層を形成したことを
特徴とする半導体装置。 (2) 導電性接着材がベース樹脂に硬化剤を混合
した接着材に易酸化性金属と、脱酸素剤又は還元
剤とともに混練したものであることを特徴とする
実用新案登録請求の範囲第１項記載の半導体装置
。[Claims for Utility Model Registration] (1) A semiconductor device in which an electrode on a semiconductor pellet and a lead are electrically connected, characterized in that a conductive adhesive layer is formed at the electrically connected portion of the lead. Semiconductor equipment. (2) Utility model registration claim 1, characterized in that the conductive adhesive is a mixture of a base resin and a curing agent, an easily oxidizable metal, and an oxygen scavenger or a reducing agent. 1. Semiconductor device described in Section 1.
JP1990109943U 1990-10-19 1990-10-19 Semiconductor device Expired - Fee Related JP2513872Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990109943U JP2513872Y2 (en) 1990-10-19 1990-10-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990109943U JP2513872Y2 (en) 1990-10-19 1990-10-19 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0465441U true JPH0465441U (en) 1992-06-08
JP2513872Y2 JP2513872Y2 (en) 1996-10-09

Family

ID=31857210

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990109943U Expired - Fee Related JP2513872Y2 (en) 1990-10-19 1990-10-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2513872Y2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5577164A (en) * 1978-12-07 1980-06-10 Nec Corp Semiconductor device
JPS62256446A (en) * 1986-04-30 1987-11-09 Toshiba Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5577164A (en) * 1978-12-07 1980-06-10 Nec Corp Semiconductor device
JPS62256446A (en) * 1986-04-30 1987-11-09 Toshiba Corp Semiconductor device

Also Published As

Publication number Publication date
JP2513872Y2 (en) 1996-10-09

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