JPS62256446A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62256446A JPS62256446A JP9970686A JP9970686A JPS62256446A JP S62256446 A JPS62256446 A JP S62256446A JP 9970686 A JP9970686 A JP 9970686A JP 9970686 A JP9970686 A JP 9970686A JP S62256446 A JPS62256446 A JP S62256446A
- Authority
- JP
- Japan
- Prior art keywords
- conductive paste
- bumps
- leads
- bonding
- gold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 9
- 239000010931 gold Substances 0.000 abstract description 9
- 229910052737 gold Inorganic materials 0.000 abstract description 9
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 abstract description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 3
- 239000004020 conductor Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 239000010936 titanium Substances 0.000 abstract description 3
- 229910052719 titanium Inorganic materials 0.000 abstract description 3
- 229910052721 tungsten Inorganic materials 0.000 abstract description 3
- 239000010937 tungsten Substances 0.000 abstract description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 3
- 239000000853 adhesive Substances 0.000 abstract description 2
- 230000001070 adhesive effect Effects 0.000 abstract description 2
- 238000007747 plating Methods 0.000 abstract description 2
- 229910000831 Steel Inorganic materials 0.000 abstract 1
- 239000010959 steel Substances 0.000 abstract 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 235000008429 bread Nutrition 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000007761 roller coating Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は、半導体チップの上面にバンプを介してリード
基端を接合した半導体装置、特にバンプを蒸着させたパ
ッド下面に位置する半導体チップのクラックの発生を防
止するとと６に、大デツプ及び多ビン化に対応してリー
ドの接合の際の位置決めの容易化を図った半導体装置に
閏する。[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device in which a lead base end is bonded to the upper surface of a semiconductor chip via a bump, and particularly to a semiconductor device in which a lead base end is bonded to the upper surface of a semiconductor chip via a bump, and in particular to a lower surface of a pad on which a bump is vapor-deposited. In order to prevent the occurrence of cracks in the located semiconductor chip, the semiconductor device is designed to facilitate positioning when joining leads in response to a large depth and a large number of bins.
（従来の技術）
従来、半導体チップ上面にアルミニウム等の導電物質で
バットを形成し、このパッドの上面にクロム／銅／金又
はチタン／タングステン／金からなる三層バイメタルを
蒸着し、このバイメタル上に金メッキを施してバンプを
形成し、このバンプを介してこの上面にスズでメッキさ
れた銅製のリード基端を金−スズ接合で取付けることが
一般に行われていた。また、バンプを導電性ペーストで
構成し、この導電性ペーストを介して半導体チップとリ
ード基端とを直接接合することも一般に行われていた。(Prior art) Conventionally, a bat is formed on the upper surface of a semiconductor chip using a conductive material such as aluminum, and a three-layer bimetal consisting of chromium/copper/gold or titanium/tungsten/gold is deposited on the upper surface of this pad. It has been common practice to plate the lead with gold to form a bump, and to attach the base end of a copper lead plated with tin to the upper surface of the lead via the bump by gold-tin bonding. It has also been common practice to construct bumps with conductive paste and to directly bond the semiconductor chip and the base ends of the leads through the conductive paste.
（発明が解決しようとする問題点）
しかしながら、上記バンプによる金−スズ接合は、５０
０℃程度に加熱しつつ半導体チップ全面を上方から、１
バンプ当り４０ｇ程度の力で押圧する抑圧ツールを平行
に保持し、かつｆｆｌｆｉ分布を均一にしないと接合強
度にばらつきが生じるばかりでなく、加重が一部のバン
プに片当すして、パッド下面に当接づ゛る半導体チップ
にクラックが生じてしまうことがあった。更に、スズや
ケイ素等の屑が上記抑圧ツールに付着してしまい、この
クリーニングを頻繁に行う必要があり、しかも、この接
合は上記のように５００℃（２００℃〜５００℃）の高
温接合のため、高価な耐熱テープを使用する必要がある
ばかりでなく、各部に熱応力を発生し易く、これが上記
クラック発生の原因ともなっていた。(Problems to be Solved by the Invention) However, the gold-tin bonding using the bumps described above is
The entire surface of the semiconductor chip is heated from above to 1°C while being heated to about 0°C.
If the suppression tool, which presses with a force of about 40 g per bump, is held parallel and the fflfi distribution is not uniform, not only will the bonding strength vary, but the load will also be applied to some bumps unevenly, causing damage to the bottom surface of the pad. Cracks may occur in the semiconductor chips that are in contact with each other. Furthermore, debris such as tin and silicon adheres to the suppression tool, which requires frequent cleaning.Moreover, this bonding is performed at a high temperature of 500℃ (200℃ to 500℃) as described above. Therefore, not only is it necessary to use an expensive heat-resistant tape, but also thermal stress is likely to be generated in each part, which is a cause of the above-mentioned cracks.
また、導電性ペーストのみでバンプを構成する場合は、
小型化することができず、しかも不純物が半導体チップ
の表面を汚染してしまうことがあった。In addition, when constructing bumps using only conductive paste,
It is not possible to miniaturize the semiconductor chip, and impurities sometimes contaminate the surface of the semiconductor chip.
本発明は上記に鑑み、バンプを介して半導体チップにリ
ードを接合するものであって、この接合を低温かつ低加
重で行なうことができ、従ってキャリアテープのローコ
スト化、接合用機械の平行度出しの筒易化及びメンテナ
ンスの容易化等を図ることができ、更に大チップ多ビン
化に伴なう位置決めの困難性を排除したものを提供する
ことを目的としてなされたものである。In view of the above, the present invention is to bond leads to a semiconductor chip via bumps, and this bonding can be performed at low temperature and with low load, thereby reducing the cost of carrier tape and increasing the parallelism of bonding machines. The purpose of this design is to provide a device that can be easily cylindrical and maintainable, and also eliminates the difficulty in positioning that accompanies the increase in the number of large chips and multiple bins.
（発明の構成）
（問題点を解決するための手段）
本発明は上記に鑑み、通常の方法で半導体チップの上面
に形成したバンプの表面、或いはリード基端の下面に導
電性ペーストを吸着させ、この導電性ペーストの接着力
によって、バンプとリードとを接合させたものである。(Structure of the Invention) (Means for Solving the Problems) In view of the above, the present invention provides a method in which a conductive paste is adsorbed to the surface of a bump formed on the top surface of a semiconductor chip by a conventional method, or to the bottom surface of a lead base end. , the bump and the lead are bonded together by the adhesive force of this conductive paste.
（作 用）
而して、従来のような金−スズ接合を廃止し、導電位ペ
ーストを介してバンプとリード基端とを接合することに
より、接合の低温化及び低加重化を因るとともに、導電
性ペーストのもつ粘性によって接合歪の発生を極力防止
し、位置決めの容易化を図ったものである。(Function) Therefore, by abolishing the conventional gold-tin bonding and bonding the bump and the base end of the lead via conductive paste, the temperature and load of the bonding can be lowered and the load can be lowered. The viscosity of the conductive paste prevents the occurrence of bonding strain as much as possible and facilitates positioning.
（実施例）
図面は本発明の一実施例を示すもので、半導体チップ１
の両側縁上面にはアルミニウム等の導電物質で形成され
たパッド２が接着形成され、このバッド２の上面にはク
ロム／銅／金又はチタン／タングステン／金からなる三
層バイメタルが蒸着され、このバイメタル上には金メッ
キが施されてバンプ３が形成されている。(Embodiment) The drawing shows an embodiment of the present invention, in which a semiconductor chip 1
Pads 2 made of a conductive material such as aluminum are adhesively formed on the upper surfaces of both sides of the pads, and a three-layer bimetal consisting of chromium/copper/gold or titanium/tungsten/gold is deposited on the upper surface of the pads 2. Bumps 3 are formed on the bimetal by gold plating.
このバンプ３の表面とリード４の基端の下面との間には
通常の半導体に使用される半導体ペースト５が介在され
、この導電性ペースト５を介して両者３．４が接合され
ている。A semiconductor paste 5 used for ordinary semiconductors is interposed between the surface of the bump 3 and the lower surface of the base end of the lead 4, and the two 3.4 are bonded via the conductive paste 5.
この導電性ペースト５の浄さは、バンプ３の厚さと同程
度、すなわら、１０〜３０μ程度が好ましい。The purity of this conductive paste 5 is preferably about the same as the thickness of the bump 3, that is, about 10 to 30 microns.
而して、この接合は導電性ペースト５をバンプ３の表面
、或いはリード４の下面にデツピングローラーコート等
により塗布し、バンプ３とリード４との位置決めを行っ
た後、望ましくは、１００℃〜２００℃程度の低温の雰
囲気に数十分〜数時間置くことにより、導電性ペースト
５を熱硬化させ、両者３．４を接合させるのであり、こ
の時、リード４のずれを防止するため、１つのパン１当
り数グラム程度の加重をかけることが望ましい。For this bonding, the conductive paste 5 is applied to the surface of the bump 3 or the lower surface of the lead 4 using a dipping roller coating or the like, and the bump 3 and the lead 4 are positioned, preferably at 100°C. By leaving it in an atmosphere at a low temperature of ~200°C for several minutes to several hours, the conductive paste 5 is thermally cured and the two parts 3.4 are joined together. At this time, in order to prevent the leads 4 from shifting, It is desirable to apply a weight of several grams to each piece of bread.
また、導電性ペースト５の粘性によるセルフアラインメ
ント効果によって接合歪を最小限に止めることができる
。Further, bonding distortion can be minimized due to the self-alignment effect due to the viscosity of the conductive paste 5.
本発明は上記のような構成であるので、パッ゛ド下面に
位置する半導体チップにクラックが発生してしまうこと
を確実に防止することができるばかりでなく、大チップ
多ビンになっても信頼性が低下してしまうことがない。Since the present invention has the above-mentioned configuration, it is not only possible to reliably prevent cracks from occurring in the semiconductor chips located on the bottom surface of the pad, but also to ensure reliability even in the case of a large number of chip bins. There is no loss of sexuality.
更に、接合用機械の平坦化機構が簡単で済むため、コス
トダウンを図ることができるばかりでなく、ケイ素やリ
ンの屑等が発生しないため、メンテナンスが容易で、し
かも導電性ペーストが直接半導体チップに触れることが
ないので、不純物の心配はない。Furthermore, since the flattening mechanism of the bonding machine is simple, it is possible not only to reduce costs, but also because no silicon or phosphorus waste is generated, maintenance is easy, and the conductive paste can be applied directly to the semiconductor chip. There is no need to worry about impurities as there is no contact with the water.
また、接合工程における低温化を図ることができ、これ
によって１ａＩＩＩ服係数の差による歪の発生を防止し
て、バンプとリードとの接合を一定に保持することがで
き、しかも高価な耐熱デーブを使用する必要がないとい
った効果を奏する。In addition, it is possible to lower the temperature in the bonding process, thereby preventing the occurrence of distortion due to the difference in the 1aIII coefficient and maintaining the bond between the bump and the lead at a constant level. The effect is that there is no need to use it.
図面は本発明の一実施例を示？ｊ１ｇｉ面図である。
１・・・半導体チップ、３・・・バンプ、４・・・リー
ド、５・・・導電性ペースト。Does the drawing show an embodiment of the invention? It is a j1gi plane view. DESCRIPTION OF SYMBOLS 1... Semiconductor chip, 3... Bump, 4... Lead, 5... Conductive paste.
Claims (1)
電性ペーストを介して接合したことを特徴とする半導体
装置。A semiconductor device characterized in that bumps formed on the top surface of a semiconductor chip and base ends of leads are bonded via a conductive paste.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9970686A JPS62256446A (en) | 1986-04-30 | 1986-04-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9970686A JPS62256446A (en) | 1986-04-30 | 1986-04-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62256446A true JPS62256446A (en) | 1987-11-09 |
Family
ID=14254506
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9970686A Pending JPS62256446A (en) | 1986-04-30 | 1986-04-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62256446A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0465441U (en) * | 1990-10-19 | 1992-06-08 | ||
| US6646355B2 (en) | 1997-07-10 | 2003-11-11 | International Business Machines Corporation | Structure comprising beam leads bonded with electrically conductive adhesive |
-
1986
- 1986-04-30 JP JP9970686A patent/JPS62256446A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0465441U (en) * | 1990-10-19 | 1992-06-08 | ||
| US6646355B2 (en) | 1997-07-10 | 2003-11-11 | International Business Machines Corporation | Structure comprising beam leads bonded with electrically conductive adhesive |
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