JPH0462945A - Flip-chip mounting method - Google Patents
Flip-chip mounting methodInfo
- Publication number
- JPH0462945A JPH0462945A JP17258990A JP17258990A JPH0462945A JP H0462945 A JPH0462945 A JP H0462945A JP 17258990 A JP17258990 A JP 17258990A JP 17258990 A JP17258990 A JP 17258990A JP H0462945 A JPH0462945 A JP H0462945A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- chip
- flip
- ceramic substrate
- conductor pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000000919 ceramic Substances 0.000 abstract description 9
- 239000004020 conductor Substances 0.000 abstract description 8
- 229910000679 solder Inorganic materials 0.000 abstract description 7
- 238000007639 printing Methods 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 238000007740 vapor deposition Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/10165—Alignment aids
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/81139—Guiding structures on the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/8114—Guiding structures outside the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、ハンプつぶれ防止用の間隔規定物を使用した
フリップチップ実装方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a flip-chip mounting method using a distance defining member for preventing hump collapse.
（従来の技術）
従来、このような分野の技術としては、例えば実開昭５
９−２０６３３号、実開昭６０−７３２５０号等に記載
されるものがあった。(Prior art) Conventionally, as a technology in this field, for example,
There were those described in No. 9-20633, Utility Model Application Publication No. 60-73250, etc.
即ち、フリップチップボンディングによって、フリップ
チップボンディング用ＩＣと、対向接続される回路基板
との実装間隔を制御する方法としては、第２図及び第３
図に示すようなものがあった。That is, as a method of controlling the mounting distance between a flip-chip bonding IC and a circuit board that is connected facing each other by flip-chip bonding, the method shown in FIGS.
There was something like the one shown in the figure.
（１）第２図（ａ）に示すように、ＩＣチップ１上にバ
ンプ２を形成し、次いで、第２図（ｂ）に示すように、
間隔規定物３を形成する。次いで、第２図（ｃ）及び（
ｄ）に示すように、ＩＣチップ１をバンプ５が形成され
る基板４上に実装する（例えば、実開昭５９−２０６３
３号参照）。(1) As shown in FIG. 2(a), bumps 2 are formed on the IC chip 1, and then, as shown in FIG. 2(b),
A spacing defining object 3 is formed. Next, Fig. 2(c) and (
As shown in d), the IC chip 1 is mounted on the substrate 4 on which the bumps 5 are formed (for example, according to Utility Model Application Publication No. 59-2063
(See No. 3).
（２）第３図（ａ）に示すように、基板１１上に導体パ
ターン１２を形成し、次に、第３図（ｂ）及び（ｂ）′
に示すように、導体パターン１２上に間隔規定物１３を
形成する。次に、第３図（ｃ）に示すように、ＩＣチッ
プ１４を実装するようにしていた（例えば、実開昭６０
−７３２５０号参照）。(2) As shown in FIG. 3(a), a conductive pattern 12 is formed on the substrate 11, and then, as shown in FIG. 3(b) and (b)'
As shown in FIG. 2, a spacing defining member 13 is formed on the conductive pattern 12. Next, as shown in FIG. 3(c), the IC chip 14 was mounted (for example,
-73250).
（発明が解決しようとする課題）
しかしながら、第２図に示すように、ＩＣチップ１上に
、間隔規定物３を設ける方法は、ＩＣチップのコストが
高くなる。特に、サーマルヘッドのように、ＩＣを多数
実装する品物は、コストアップの大きな要因となってし
まう。従って、サーマルヘッドのようなものに実装する
とすれば、第３図に示すように、基板１１側に間隔規定
物１３を設ける方法が望ましい。しかし、基板１１上の
導体パターン１２を高密度化すると、第３図に示すよう
に、導体パターン１２上に間隔規定物１３を形成しなけ
ればならなくなる。ところが、この方法であると、基板
１１に導体パターン１２のパッド部を形成した後、更に
、間隔規定物１３を設ける工程が必要となり、パッド部
が間隔規定物１３を構成する物質によって汚され、歩留
まりの低下を招いてしまう。(Problems to be Solved by the Invention) However, as shown in FIG. 2, the method of providing the interval defining member 3 on the IC chip 1 increases the cost of the IC chip. In particular, products such as thermal heads in which a large number of ICs are mounted are a major factor in increasing costs. Therefore, if it is to be mounted on something like a thermal head, it is desirable to provide a distance defining member 13 on the substrate 11 side, as shown in FIG. However, if the density of the conductor pattern 12 on the substrate 11 is increased, it becomes necessary to form a space defining member 13 on the conductor pattern 12, as shown in FIG. However, with this method, after forming the pad portion of the conductive pattern 12 on the substrate 11, a further step of providing the spacing defining material 13 is required, and the pad portion is contaminated by the substance constituting the spacing defining material 13. This results in a decrease in yield.
本発明は、以上述べた高密度配線を施した基板に対して
、間隔規定物を作成する困難性を除去するために、予め
突起物を基板に形成し、その上にパターンを形成し絶縁
することによって、フリップチップの基板との適切な間
隔をとると共に、信顛性の高いフリップチップ実装方法
を提供することを目的とする。In order to eliminate the difficulty of creating interval defining objects for a substrate with high-density wiring as described above, the present invention forms protrusions on the substrate in advance, forms a pattern on the protrusions, and insulates the substrate. By doing so, it is an object of the present invention to provide a highly reliable flip-chip mounting method that provides an appropriate distance between the flip-chip and the substrate.
（課題を解決するための手段）
本発明は、上記目的を達成するために、基板上にフリッ
プチップを実装するフリップチップ実装方法において、
なだらかな傾斜面を有する突起部を形成した基板を用意
し、該基板に高密度配線を施し、該高密度配線上に絶縁
膜を形成し、前記突起部を基準位置にしてフリップチッ
プの高さを規定するようにしたものである。(Means for Solving the Problems) In order to achieve the above object, the present invention provides a flip chip mounting method for mounting a flip chip on a substrate.
A substrate on which a protrusion having a gently sloped surface is formed is prepared, high-density wiring is applied to the substrate, an insulating film is formed on the high-density wiring, and the height of the flip chip is determined using the protrusion as a reference position. It is designed to stipulate the following.
（作用）
本発明によれば、上記したように、予めなだらかな傾斜
面を有する突起部を基板に形成し、その上に高密度配線
を形成し、絶縁体被膜をオーバーコートし、絶縁する。(Function) According to the present invention, as described above, a protrusion having a gently sloped surface is formed in advance on a substrate, a high-density wiring is formed thereon, and an insulating film is overcoated to insulate the protrusion.
そこで、前記突起部を基準にしてフリップチップを実装
する。Therefore, a flip chip is mounted using the protrusion as a reference.
従って、基板とフリップチップ間は適切に間隔をとるこ
とができ、フリップチップのバンプつぷれを防止するこ
とができる。Therefore, it is possible to maintain an appropriate distance between the substrate and the flip chip, and it is possible to prevent the bumps from collapsing on the flip chip.
（実施例）
以下、本発明の実施例について図面を参照しながら詳細
に説明する。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は本発明の実施例を示すフリップチップ実装工程
断面図である。FIG. 1 is a sectional view of a flip chip mounting process showing an embodiment of the present invention.
まず、第１図（ａ）に示すように、セラミック基板２１
上になだらかな傾斜面を有する突起部としての部分グレ
ーズ２２を設ける。First, as shown in FIG. 1(a), a ceramic substrate 21
A partial glaze 22 as a protrusion having a gently sloped surface is provided on the top.
次に、第１図（ｂ）に示すように、セラミック基板２１
上に、スパッタ法、蒸着法、印刷焼成等で導体パターン
２３の膜付けを行い、その導体パターン２３上にソルダ
レジスト等の絶縁膜２４を形成する。Next, as shown in FIG. 1(b), the ceramic substrate 21
A conductor pattern 23 is formed on the conductor pattern 23 by sputtering, vapor deposition, printing and baking, etc., and an insulating film 24 such as a solder resist is formed on the conductor pattern 23.
次いで、第１図（ｃ）に示すように、セラミック基板２
１上に半田ハンプ２６が形成されたＩＣチップ２５を実
装する。Next, as shown in FIG. 1(c), the ceramic substrate 2
An IC chip 25 on which a solder hump 26 is formed is mounted.
このようにして、間隔を規定する部分グレーズ２２が形
成されたセラミック基板２１に対して半田バンプ２６を
形成したＩＣチップ２５を確実に実装することができる
。In this way, the IC chip 25 on which the solder bumps 26 are formed can be reliably mounted on the ceramic substrate 21 on which the partial glaze 22 defining the spacing is formed.
なお、本発明は上記実施例に限定されるものではなく、
本発明の趣旨に基づいて種々の変形が可能であり、これ
らを本発明の範囲から排除するものではない。Note that the present invention is not limited to the above embodiments,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.
（発明の効果）
以上、詳細に説明したように、本発明によれば、予め基
板に対してなだらかな傾斜面を有する突起部を形成する
ようにしたので、パターン形成後に間隔規定物を設ける
工程が不要となり、パッド部が汚れてバンプとの接合が
できなくなるということはなくなり、歩留まりの向上を
図ることができる。(Effects of the Invention) As described above in detail, according to the present invention, since the protrusion having a gently sloped surface is formed on the substrate in advance, the step of providing the interval defining object after pattern formation This eliminates the need for pads to become dirty and prevent bonding with bumps, thereby improving yield.
更に、なだらかな傾斜面を有する突起部が形成された基
板を用いるため、高密度な配線を形成することができる
。Furthermore, since a substrate on which protrusions having gently sloped surfaces are formed is used, high-density wiring can be formed.
第１図は本発明の実施例を示すフリップチップ実装工程
断面図、第２図は従来のフリップチップ実装工程断面図
、第３図は従来の他のフリップチップ実装工程断面図で
ある。
２１・・・セラミック基板、２２・・・部分グレーズ、
２３・・・導体パターン、２４・・・絶縁膜、２５・・
・ＩＣチップ、２６・・・半田ハンプ。FIG. 1 is a sectional view of a flip chip mounting process showing an embodiment of the present invention, FIG. 2 is a sectional view of a conventional flip chip mounting process, and FIG. 3 is a sectional view of another conventional flip chip mounting process. 21... Ceramic substrate, 22... Partial glaze,
23... Conductor pattern, 24... Insulating film, 25...
・IC chip, 26...Solder hump.
Claims (1)
装方法において、 （ａ）なだらかな傾斜面を有する突起部を形成した基板
を用意し、 （ｂ）該基板に高密度配線を施し、 （ｃ）該高密度配線上に絶縁膜を形成し、 （ｄ）前記突起部を基準位置にしてフリップチップの高
さを規定するようにフリップチップを実装することを特
徴とするフリップチップ実装方法。[Claims] In a flip-chip mounting method for mounting a flip chip on a substrate, (a) a substrate on which a protrusion having a gently sloped surface is formed, (b) high-density wiring is provided on the substrate; (c) forming an insulating film on the high-density wiring, and (d) mounting the flip chip so as to define the height of the flip chip using the protrusion as a reference position. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2172589A JP2605166B2 (en) | 1990-07-02 | 1990-07-02 | Flip chip mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2172589A JP2605166B2 (en) | 1990-07-02 | 1990-07-02 | Flip chip mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0462945A true JPH0462945A (en) | 1992-02-27 |
| JP2605166B2 JP2605166B2 (en) | 1997-04-30 |
Family
ID=15944650
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2172589A Expired - Lifetime JP2605166B2 (en) | 1990-07-02 | 1990-07-02 | Flip chip mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2605166B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5700715A (en) * | 1994-06-14 | 1997-12-23 | Lsi Logic Corporation | Process for mounting a semiconductor device to a circuit substrate |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5077862A (en) * | 1973-11-14 | 1975-06-25 | ||
| JPS5279872A (en) * | 1975-12-26 | 1977-07-05 | Seiko Epson Corp | Bonding substrate |
-
1990
- 1990-07-02 JP JP2172589A patent/JP2605166B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5077862A (en) * | 1973-11-14 | 1975-06-25 | ||
| JPS5279872A (en) * | 1975-12-26 | 1977-07-05 | Seiko Epson Corp | Bonding substrate |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5700715A (en) * | 1994-06-14 | 1997-12-23 | Lsi Logic Corporation | Process for mounting a semiconductor device to a circuit substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2605166B2 (en) | 1997-04-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6139741B2 (en) | ||
| JPH0462945A (en) | Flip-chip mounting method | |
| JPH08111578A (en) | Manufacture of board for mounting ball grid array package | |
| JPH10321651A (en) | Semiconductor device | |
| JP2924113B2 (en) | Electronic component bonding method | |
| JPH0685005A (en) | Mounting structure of semiconductor chip | |
| JP3835492B2 (en) | Electronic component having substrate and method of manufacturing the same | |
| JP3101000B2 (en) | Bonding bump forming method | |
| JP2000058588A (en) | Land-grid-array electronic component and printed board | |
| JPS6041728Y2 (en) | semiconductor equipment | |
| JPH04286392A (en) | Printed circuit board | |
| JPH0982750A (en) | Semiconductor device | |
| JPS6339974Y2 (en) | ||
| JPH0786330A (en) | Semiconductor device and semiconductor mounting device | |
| JPH06168949A (en) | Solder bump forming method | |
| JPS58191661U (en) | printed board | |
| JPH0563331A (en) | Printed circuit board | |
| JPH1197571A (en) | Conversion substrate and semiconductor device | |
| JPS63305523A (en) | Manufacture of semiconductor element | |
| JPH0669052B2 (en) | High-density mounting method for semiconductor devices | |
| JPS62140775U (en) | ||
| JPH01208874A (en) | Led head | |
| JPH02174183A (en) | Sensor and mounting construction of signal processing circuit therefor | |
| JPH02122477U (en) | ||
| JPH0311655A (en) | Semiconductor device |