JPH046291B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a data communication system, and particularly to a common data communication system.
A large number of terminal devices are connected to a transmission path, and these terminals are connected to each other.
Regarding the method of transmitting and receiving data in time division between
It is something to do. Recently, office systems aimed at improving clerical productivity have been
Automation (hereinafter abbreviated as OA) has been in the spotlight.
It's coming. Traditional OA is mainly individual and fixed
The mainstream is to execute tasks in batches.
However, in the future, for example, electronic files and e-mail
so-called data processing such as files, document editing, etc.
There is a growing demand for more sophisticated automation of office work.
Ru. On the other hand, based on optical fibers, light emitting diodes, etc.
With the rapid development of optical communication technology, high speed and low
Digital transmission of prices is a familiar network
There is an increasing possibility that it can be applied to Based on this technical background, facsimile
computers, telephones, word processors, personal computers
Common signal transmission between computers, various data terminals, etc.
connect to the Internet and freely communicate data between devices.
A comprehensive network system that enables
Attempts are being made to realize this. However, it is difficult to realize such a network.
In order to do so, we must solve the following problems.
No. In other words, in this kind of network system
connects many node devices to a common loop-shaped transmission path.
information between the terminal devices connected to the node device.
information is exchanged, but each node
There are multiple terminal devices connected to the device, and
When exchanging information between terminal devices,
Two channels of a loop-shaped transmission path are used for transmission and reception.
It is illegal to use a proprietary transmission path to transmit information.
It's always a waste. An object of the present invention is to address the problems mentioned above.
The objective is to provide a synchronization method. In order to achieve this purpose, the present invention
Multiple nodes each connected to multiple terminal devices
This method connects the board devices through a common loop-shaped transmission path.
Transmission frames consisting of multiple channels are unified on the transmission path.
At least one of the above transmission frames is rotated at a fixed period.
communication between the above terminal devices using one channel.
In the data communication method that is designed to
A terminal device pair is added to a node device that accommodates terminal devices.
A terminal control unit is installed according to the requirements, and communication between these terminal control units is established.
Connected via internal data bus and housed in the same node device
from the first terminal device to the second terminal device
Data transfer is performed via the internal data bus mentioned above.
from the second terminal device to the first terminal device.
Data transfer to other node equipment
Similar to the data transfer to the terminal device, the above loop transmission
It is now done via the transmission frame on the transmission path.
It is characterized by First, Figure 1 shows the overall system configuration of the method of the present invention.
Explain with reference to. In the figure, 1 is a loop-shaped common transmission line, for example
For example, optical fiber is used. 2 is on this transmission line
A connected node device, detailed later.
Describe. This node device is per loop, for example
32 to 64 connected, at least one of them
consists of a synchronization signal area and an information channel area.
It has the function of generating frames. 3 is the terminal device
For example, fax machines, word processors,
-Sonal computer, mini computer, telephone
This includes devices such as devices and various data terminal devices.
This terminal device is per node device, for example, 8
~32 are connected. Therefore, in the above example, 1 loop
256 to 2048 terminals can be connected per transmission path.
It becomes. Of course, the number of these devices is just an example
However, the method of the present invention is not limited to this.
Needless to say, there is no such thing. Next, the frame rate in the time division multiplex communication system of the present invention will be explained.
This section explains the system configuration. In the method of the present invention, the above-mentioned loop-shaped transmission
Bit string information is transmitted on channel 1, but only a certain number of bits are transmitted.
A group of consecutive bits is called a channel here.
A group with a certain number of consecutive channels is called a frame.
It is called a system. This frame maintains a constant transmission rate.
If so, it will occur at a constant repetition period. The frame in the method of the present invention is shown in FIG. 2A.
The synchronization area X and the information communication area Y are structured so that
will be accomplished. For example, 4 channels are the synchronization area X.
The remaining channels will be used as information communication area.
It is used as In this example, one channel is 10 bits.
It consists of The frame repetition period is
In the example, 125μs (8KHz) is selected. Therefore,
If the data speed is 10Mbps, one frame
Number of channels is 125 channels, 400 channels at 32Mbps
Become a le. Each channel in the sync area has 10 bits for synchronization.
bit pattern is inserted. This bit pattern
This phenomenon occurs infrequently in the information and communication area Y.
Preferably, it is a bit pattern. Information and communication area Y is used for packet switching during circuit switching function.
The frame structure will be different depending on when the card exchange function is used.
Figure 2B shows the frame structure when the circuit switching function is used.
Figure C and Figure 2D are frames during packet exchange function.
Configuration, Figure 2E is a frame when both are mixed.
It is the composition. Below are the frame configurations for each.
This will be explained in detail. Frame structure when switching circuits As is clear from Figure 2B, the flexibility when switching circuits is
The system consists of synchronization area X, connection control packet area A, and
and circuit switching area B. The beginning of the frame is the beginning of the frame.
Fixed synchronization characters for identification (one character is 10 bits)
In the synchronization region
Yes, it consists of multiple channels. The next area is
Connection control packet area A and circuit switching area B
However, if they are continuous areas, they are ordered
Either is fine. Also, the above inside the whole frame
Areas other than the three areas may be included. Connection control packet area A is the area where data should be sent.
address of the destination node device and terminal device,
address and data of the node device and terminal device on the receiving side.
Channels in circuit-switched area B used for transmitting and receiving data.
Packets of so-called connection control information such as channel number etc.
used for transmission. This connection control packet area A is illustrated in Figure 2F.
16 Channel A₀~A₁₅It consists of
Each channel is formed from 10 bits, initially
bit A₀₀is the empty block table of connection control packet area A
used for demonstration purposes. i.e. frame repetition
If the cycle is 125μs (8KHz), connection control information
transmits up to 8K pieces/sec of different connection information as
However, this connection control packet area A
If you are using A₀₀Set the bit to “1”,
Set to “0” if not used.
This indicates the empty status of this area.
Note that this connection control packet area A is used for communication between terminals.
When setting the channel for data transfer,
It is only used when canceling settings, etc.
Therefore, the period at which data is actually sent and received is
Only circuit switched channels are used. The second channel of connection control packet area A
Bit A₀₁is preliminarily provided in this embodiment.
Since it is not directly related to the present invention, the explanation will be omitted. A for each channel₀₂~A₀₉The 8 bits of
represents information. Figure 2G shows the connection control packet area.
Each channel of A₀~A₁₅and through that channel
An example of the relationship with the information transmitted is shown below. Channel A₀is a node device that sends data
A₁
connects one of the terminals connected to that node device.
Used to specify. A₂sends data
The address of the destination node device to be₃teeth
The data destination terminal connected to that node device
used to transmit information representing the address of
It will be done. Channel A₆Request to send data, end
Used to transmit connection control codes that indicate request differentiation.
It will be done. Channel A_Fiveis for data communication.
Specific channel number in circuit switching area B used for
It is used for transmitting information representing information. channel
A₆~A₁₃is used to transmit various parameters
However, since it is not directly related to this invention, the explanation will be omitted.
Ru. Multiple channels in circuit switching area B at the same time
When communicating using channel A,₆
~A₁₃be used to display the channel number.
You can also do it. Channel A₁₆Transmission of check code
used for. For example, channel A₆~A₁₃of
Check the results of performing certain calculations on the data.
The same data is transmitted on the receiving side.
The same calculation process is performed on the transmitted data.
Check whether the data is correct or incorrect. Channel A₁₅stay
Used for transmitting task information. For example, data
When the destination node device receives the data, it
Channel A₁₉sends information with predetermined information
Send it back. This causes the source node device to
Data delivery can be confirmed. On the other hand, in circuit switching area B, the connection control packet is
multiple channels through the channel specified in target area A.
To exchange information between terminal devices for the purpose
used for. This circuit-switched area B has an arbitrary number of channels B.₀，
B₁,B₂…B_nIt consists of It is shown in Figure 2H.
Each channel consists of 10 bits,
Place 8 bit B₀₂~B₀₀is allocated for data transmission.
It is. First bit B₀₀is that channel
Displays whether it is vacant or already used.
Used as a vacancy indicator bit. 2 number
Bit B₀₁is the 8-bit data of that channel.
Whether the data is valid or invalid
Used for display. Whether this information is valid or not
Effect bit B₀₁The data rate can be adjusted by
Yes, the reason is briefly explained below. As mentioned above, in the method of the present invention, the period of one frame is
For example, 125μs (8KHz) is selected, so 1
The amount of data that can be transmitted per second on a channel is 8 bits.
Bit x 8K = 64K bit. In the present invention, this chip
Handles data even at ultra-low speed using units of data
Even on the terminal, if there is a transmission request from the terminal, 1
We have decided to allocate a terminal channel. accordingly
If the data speed of your device is extremely slow, for example around 50bps,
In some cases, even if one channel is allocated, all transmission
The data is processed at a rate of about once every 64K/50 frames.
only occurs. That is, 8K frames per second.
Even if the frame is repeatedly generated,
The channel is used only once every 1000 frames.
This means that ultra-low-speed data can be transmitted in minutes. obey
If you focus on one channel, you can
Frames with data and frames with no data
This means that the frames are being generated repeatedly.
Therefore, in this invention, data is assigned to the assigned channel.
B if there is a₀₁Display bits as valid,
For example, if you set "1" and there is no data,
B₀₁Display bits as invalid, e.g. set to “0”
We are planning to do so. Therefore B₀₁Bit “1”
The period represents the speed of data.
In other words, each node device is B₀₁Use bits
This allows you to freely adjust data with different speeds.
Can send and receive. On the other hand, transmitting high-speed data of 64Kbps or more
In some cases, it is easier to assign multiple channels.
can be dealt with. For example, it handles high-speed data of 1Mbps.
It is sufficient to allocate 16 channels to the terminal. Next, we will discuss the data communication procedure using the circuit switching method.
This will be explained with reference to FIG. In response to a transmission request from the terminal, the node device
Logical address of the terminal (e.g. phone number)
Create a destination address from. of each node device
The address must be fixedly assigned in advance or otherwise known to the public.
Determined by law. Next, channel B in circuit switching area B₀~B_namong
Air block display bit (B₀₀,B_Ten,B₂₀…) is displayed empty
(e.g. “0”) and select that channel.
is displayed as a block (for example, "1"). Then the 2nd G
The connection control packet format as shown in the figure
Based on this, a connection control packet is created. this place
Channel A_FourA connection request is made to the area corresponding to
The code to display is stored in A_Fivearea equivalent to
contains data representing the hunted channel number.
Stored. Once the connection control packet has been created, it will be displayed as empty.
Find the connection control packet area A that is
packet (this is called the first packet)
do. The empty state of area A above is connected as described above.
First channel A of control packet area A₀empty block table
Indicator A₀₆It can be identified by looking at it. The above connection control packet is received by the receiving node.
It interprets the packet information and first requests a connection.
Check if the device you are using is not in use, and if it is
If not, use the given channel number (channel
Nell A_Fivedata) to the terminal of the above node device.
Set to Gobe. This is used to set the channel number.
data sent through this channel from now on.
data will be received by the terminal. After that, the reception
The channel setting process has been completed on the destination node device.
response packet information is created, which means that
This packet (this is called the second packet)
is sent to the sending node device. The sending node device confirms delivery of the first packet.
and then receive the second packet of response information.
wait. After receiving the second packet, a certain time
and sends a start instruction to the sending terminal. On the other hand, the destination node device displays the response information.
After confirming delivery of the second packet, it is immediately sent to the terminal.
Give a start instruction. Already sent at this point
Same usage for the terminal control section of the receiving side and the receiving side node equipment.
The channel number has been set, and from then on, termination requests will be made.
Information exchange between both terminals takes place at frame period intervals until
exchange through the specified channel in circuit-switched area B.
This is done continuously. at the timing when a certain frame is being generated.
and the data to be sent is still occurring on the device.
If not, the validity indicator bit in the channel (e.g.
For example B₀₁) to “0”, for example,
The frame data is sent to the receiving node device.
is invalid. Effectiveness table like this
Automatic adjustment of data by using indicator bits
As mentioned above, this can be done. When a request to end data transmission is generated from the sending terminal.
Then, in the same way as above, the format shown in Figure 2G is created.
Creates packet information representing a termination request based on the
to be accomplished. This packet information is sent to the receiving node device.
transmitted to. Both node devices are connected to the terminal.
sends a stop instruction signal and stops the channel in use.
to release. In other words, the sending side
Set the first bit to “0”, return it to the empty state, and send it to the receiving side.
cancels the set channel. The control described above is performed by the processing within the node device, which will be described later.
is executed based on instructions from the management device. Frame configuration during packet exchange The frame at the time of packet exchange is shown in Figure 2C, Figure 2.
As shown in Figure D, synchronization area
It is composed of area D. Synchronization area X is for identifying the beginning of the frame.
This is similar to the case of circuit-switched frames.
Ru. Packet exchange area D stores all information as shown in Figure 2D.
The communication area may be made into one packet switching area.
However, as shown in Figure 2C, multiple packet exchange areas
It can also be divided into areas and used. Each packet area D has multiple areas as shown in Figure 2J.
Channel D₀,D₁…D_lfor each channel.
The information to be transmitted is allocated in advance as shown in the figure.
There is. Of course, Figure 2J only shows one example.
First, packet format, address assignment method
The law is possible in other ways as well. In this example, the first two channels D₀,D₁through
The side that sends the packet, that is, the originating address information
is transmitted, and the next two channels D₂,D₃through the
The side receiving the packet, that is, the destination address information is transmitted.
sent. and channel D₀,D₂is equipped with a node
address is channel D₁,D₃terminal device
address has been assigned. Channel D_FourSubsequent consecutive channels D_Four~D_l-2
are allocated for data transmission. final chane
channel D before_l-1is channel D₀~D_l-2
Assigned for checking the information on the last
ItoD_lis assigned for status. Note that each channel has 10 bits as in the case of Figure 2F.
The first channel D₀the top of
Only 1 bit is used to indicate vacancy in the packet exchange area.
The lower 8 bits of each channel are
represents the content. Next, the operation of data communication using the packet switching method
I will explain about it. According to the transmission request from the sending terminal, the sending node
The device waits for free packet space to be received,
The area is marked as a block and the packet information is transferred to the transmission path.
Send to. Each node device uses the destination address in the packet information.
D₂and match with own node address
If not, transfer it as is to another node device.
Ru. Channel D₀destination address is self node
If the address matches, the node device
Start making. The receiving node device is the receiving terminal connected to it.
In addition to transmitting packet information to
Final channel of information D_l, a message indicating that it has been received
Contains status information and displays the next node along with other information.
sequentially transmitted to the coded devices. Packet information goes through a loop-shaped transmission path and is sent
When it returns to the node device, this sending node device
The location is channel D₀The originating address of is the own node
Since it matches the address, the packet information that circulated
Incorporate. At the same time, the empty table of the packet area
Indicator D₀₀is displayed as empty and transmission ends.
The transmitting node device receives the captured packets after the round trip.
Communicate by checking the status of information.
You can check the normality of the transmission. As described above, when switching lines and packets using the method of the present invention,
The frame structure during port exchange and each data communication
Although the communication method has been described, in the present invention, both
Data communication can also be performed by switching the exchange method as appropriate.
The circuit-switched area and the
Create both buttocks exchange areas at the same time and use both exchange methods
Data communication can also be performed using a mixture of expressions.
Ru. Figure 2E shows the circuit switching function and packet switching function.
This shows the frame configuration when realizing both at the same time.
This frame's synchronization area X, connection control area A, and
Each bit of line switching area B and packet switching area D
The format is the same as in Figures 2B to 2D.
Therefore, its explanation will be omitted. Furthermore, in Figure 2E
The order of each area A, B, D may be arbitrary, and
The exchange area D may be divided into a plurality of areas. Figure 3A realizes the data communication method according to the present invention.
An example of the overall configuration of a normal node device for
show. 100 is a frame synchronization section, 200 is a channel
300 is a processing device, 400 is a transfer control unit
500 is a terminal control unit, 600 is a link control unit
700 is a packet control unit, 800 is a packet control unit.
Interface section, 1000 is a terminal device, 110
0 is a packetization device, 1200 is an optical loop transmission
1300 is a terminal bus. In such a configuration, the frame synchronization unit 10
0, it is sent from the loop transmission line 1200
Identify the synchronization area at the beginning of the frame from the received signal
the beginning of the frame and each channel within the frame.
Create a clock timing signal that indicates the beginning of the
Send to the section. The channel control unit 200 controls the channels within the frame.
identify the channel address or circuit-switched area of the frame.
instructions, control node operations, and update status tables.
To make a presentation, etc. The processing device 300 includes a microcomputer, a
A unit that controls the storage program using a harpoon, etc.
Programs such as connection control processing and initial setting processing can be executed in minutes.
Performs ram control. The transfer control unit 400 is connected to the loop transmission line 1200.
A predetermined terminal device 1000
After exchanging the transmitted and received signals with etc.,
A transmission signal to the loop transmission line 1200 is created. The terminal control unit 500 controls the corresponding terminal device 100
0, and transfer control unit 400.
Controls the transfer of data sent and received between. Besides that
In order to
Do remembrance. The link control unit 600 performs connection control for circuit switching.
control, and performs packet transmission and reception processing. Packet system
The controller 700 has the basic functions necessary for sending and receiving packets.
address matching detection, empty channel search,
Create transmission/reception timing, etc. In the packet interface section 800, the packet
Packetization device 1100 when having a packet exchange area
control signals, control of transmitted and received data, packet area
Memorize areas, etc. A terminal bus 1300 connects these devices 100 to 80.
0 and controls mutual transmission and reception.
look at In such a configuration, the loop transmission line 120
When a received signal comes in from 0, the transfer control unit 40
0, it is received and demodulated, and the frame synchronization section 100
Then, the synchronization signal at the beginning of the frame is detected from the received signal.
of frames and intraframe channels.
Create the clock timing necessary for reception and use it for other
Send to part. In the channel control section 200, the frame synchronization section 1
00 to channel number signal depending on the timing.
Created and sent to the terminal bus 1300,
within the circuit-switched area from this channel number signal.
It is determined whether the
put out In addition, the link control unit 600
received from the channel number signal from the channel control unit 200.
The channel is located at the beginning and end of the connection control packet area.
The packet control unit 70 determines whether the packet has been completed.
Send to 0. Now, a transmission request is received from a certain terminal device 1000.
Then, the processing device 300 detects the
Issue a hunt request to 0. In the terminal control unit 500,
Each channel imported from the transfer control unit 400
The occupancy display bit and the channel control unit 200
A signal indicating that the area is within the circuit-switched area.
Locate an empty channel in the circuit-switched area and
is found, the current channel number signal is sent to the terminal.
It is captured and stored in the control unit 500, and also transferred.
Sends a signal to the control unit 400 and selects the corresponding channel.
The loop transmission line 1 is set to the empty block indication bit to indicate the block block.
200. The processing device 300 inputs the destination address to the terminal device.
receiving information from the station 1000 or predetermined
created using a fixed address, and the destination address
address, own address, from the terminal control unit 500
Read the imported empty channel number and create a connection.
Connection control packet format including connection request code, etc.
Edit and create a connection control packet based on the
It is sent to the link control unit 600. And with that
Then, the data is sent from the processing device 300 to the link control unit 600.
When a connection request is issued, the packet control unit 700
Empty display bit for the first channel in the control packet area
If it is empty, the transfer control unit 400
Send a signal to block the empty block indication bit of the first channel.
It is displayed and sent to the loop transmission line 1200. So
At the same time, a signal is sent to the link control unit 600.
transfer the connection control packet that has already been set.
It is sent to the control unit 400 and routed as packet transmission information.
1200 on the loop transmission line 1200. In this way, it is sent to the loop transmission line 1200.
The received connection control packet is received by each node device.
It will be done. The operation is performed by the transfer control unit 400
data is sent to the packet control unit 700, where it is
, check whether the destination address matches your own address.
When a match is detected, the link control unit 6
00 and receives the received connection control packet data.
The link control unit 600 takes in the data, and further processes the data.
The device 300 reads it. The processing device 300 receives the read connection control packet.
The terminal that requested the connection is
Check if the device 1000 is not in use, and
If not in use, send the sending node device to the destination address.
Creates a connection control packet containing clear response information
and sends it to the link control unit 600 along with the transmission request.
Ru. Hereinafter, similar to the sending node device described above,
Find an empty connection control packet area and fill it with
The displayed bits are turned off and the created connections are
The connection control packet is inserted into that area and the packet is
It is sent to transmission line 1200. In addition, the processing device 30
0 indicates a connection request for the empty channel number sent.
set in the terminal control unit 500 of the terminal device 1000
do. On the other hand, the sending node device sends the
The packet goes around the loop transmission path 1200 and returns.
When the data is received by the transfer control unit 400,
The originating address in the data source matches your own address.
The packet control unit 700 determines that
A connection control packet is sent by sending a signal to the transmission control unit 400.
Set the empty block display bit of the first channel of the area to empty display.
do. On the other hand, on the sending side node equipment, the receiving side node equipment
Connection control packet indicating the response sent from the device
When the packet control unit 700 receives the
Detects that the destination address matches the self address.
and retry the connection control packet as described above.
is connected to the processing device 300 via the link control unit 600.
It's crowded. The processing device 300 checks the response information and processes the terminal.
A start command is issued to the terminal device 1000. Ma
In addition, if the information sent by the receiving node device is
I know that I have gone around the loop transmission line 1200 once.
And, as mentioned above, in the connection control packet area
Set the empty block display bit of the first channel to empty,
A start command is issued to the terminal device 1000. In the sending node device, the data from the processing device 300 is
Based on the start command, the data is sent from the terminal device 1000.
The communication data is sent to the terminal control section 500. The terminal control unit 500 sets the channel number.
The number is the channel number from the channel control unit 200.
Detects if a match is found and if a match is detected.
Then, the data sent from the terminal device 1000 is transferred.
The corresponding channel is sent to the control unit 400.
Insert the transmission data into the loop transmission line 1200.
Send to. On the other hand, on the receiving side node device, the received
The data is received by the transfer control unit 400, and the terminal control unit
Send to 500. In the terminal control unit 500, the
The channel number received from the channel control unit 200 is
Determine whether it matches the channel number signal and
When a signal is detected, the received data is captured and the terminal equipment
Send to 1000. In addition, using the same channel
At the same time, from the receiving node device to the sending node device
You can also send data in the same way to
Wear. In addition, from the receiving side node device to the sending side node device
Transmit using different channels for
You can also make it look like this. Next, in the sending node device, the terminal device 1
A transmission end request is issued to the processing device 300 from 000.
Then, the processing device 300 issues a connection control command to instruct disconnection.
Create a packet and send it to the receiver as described above.
Send to node device and stop at that terminal device 1000
Give instructions. At the same time, the processing
Channel resolution from the management device 300 to the terminal control unit 500
issue a release request and check the number of the occupied channel.
When the channel number signals match, the transfer control unit 400
to set the occupancy indication bit for that channel.
Empty it and release the channel. Note that the terminal control unit 500
When the channel number matches the received channel number signal,
Data is still coming in from terminal device 1000.
If not, the validity display bit was disabled.
send data and inform the other party that the data is invalid.
What kind of processing should be performed on the terminal device 1000 side?
They are also able to handle speed. Further, in the transfer control unit 400, link control is performed.
The first connection control packet sent from the controller 600
~ Perform the specified calculation on the data of the 14th channel.
Create a check code and send that code to the packet.
Ability to insert and forward within the 15th channel of
and the 1st to 15th of the received connection control packets
Performs predetermined calculations on the channel data and receives it.
Check the data for errors and post the results in the 16th
Insert it as status information into the channel and forward it.
It has the function of On the other hand, when performing packet exchange, the sender node
to the packet interface section 800 of the card device.
and detects the first channel in the packet exchange area.
and sends it to the packet control section 700. Packet control section
At 700, the occupancy display bit from the transfer control unit 400 is displayed.
If an empty channel is displayed, transfer control is performed.
Send a signal to section 400 to block the leading channel.
Set the display bit to black. At the same time, package
packet interface.
Transfer the packet information set in the ace section 800.
Send from the transmission control unit 400 to the loop transmission path 1200
do. On the receiving side node equipment, the first check of the packet is
Check Yanel at packet interface section 1100.
Detected by channel number signal, packet control unit 7
Start 00. The packet control unit 700 transfers
Packet data sent from the transmission control unit 400
Detects that the destination address is its own address.
and sends the result to the packet interface section 11.
Notify 00. At the interface section 1100
receives the sent packet data and processes it.
Send to location 300. Packet interface section 80
Detect end channel of packet exchange area with 0
and performs the termination action. Each node device transmits the packet data sent by itself.
The data goes around the loop transmission line 1200 and returns again.
Then, the packet control unit 700 transfers the packet in the same way.
Receives packet data from the control unit and sends the originating address.
Check that the address matches your address.
If they match, a signal is sent to the transfer control unit 400.
Then, the empty block indication bit at the beginning of the corresponding packet
Displays empty and frees the packet area. Figure 3B realizes the data communication method according to the present invention.
Because it is a node device, it has a frame generation function.
An example of the overall configuration of a node device having
The difference from FIG. 3A is that the transfer control unit 400
It is divided into a transmitting/receiving section 400A and a transfer section 400B.
and the frame generation control section between these
900 is provided. This node device is the normal node device mentioned above.
It also serves as a loop transmission line 1200.
The role is to generate frames with a constant period of rotation.
It is something that The frame generation control unit 900 completes the loop.
The transmitted frame information is sent to the transmission/reception unit of the transfer control unit 400.
Memo in frame generation control unit 900 via 400A
One frame is stored in the memory, and the clock for transmission is
is generated, and based on the clock, the pattern of the synchronization area is
Create the turn first, and then sequentially write the above memory.
Read out and form a frame. Transfer the information
The data is sent to the transfer unit 400B of the control unit. From then on, the same as others
The information to the next node is transferred to the transfer control unit.
It is sent via the transmitting/receiving section 400A. The frame generation control unit 900 also performs abnormality monitoring.
It has the function of vision. In other words, the line
in each of the exchange area and packet exchange area.
Then, all the blockage display bits of each channel will display blockage.
The indicated event continues for a certain number of times or more.
When this is detected, the vacancy display bit for each channel is
The function is to force the display to be empty. Other operations are the same as in Figure 3A.
The explanation will be omitted. Below, details are given for specific configuration examples of each part in Figure 3A.
Explain in detail. (1) Frame synchronization unit 100 FIG. 4 shows the specific configuration of the frame synchronization section 100.
This shows an example of this. In the figure, the signals TIM and SROUT are shown in Figure 7.
by the receiver and shift register as detailed.
This is a signal created by Loop transmission line 120
The serial data sent from 0 to the transfer control unit 400
The received information is demodulated by the receiver, and
Extracting the timing of the bit interval of the communication information
50% duty timing signal
TIM is created. This timing signal TIM
The serially received information is sequentially transferred to the shift register by
Store. The parallel output of that shift register is
The number is SROUT. The frame synchronizer 100 generates a synchronization pattern.
Frame synchronization area set in the generator 101
The synchronization pattern within the area and the system of the transfer control unit 400
The information stored in the foot register SROUT and
Each time one bit is received in the matching circuit 102,
Compare and if a match is found, match flip-flop
Set the block 103 through the AND gate 104.
to By setting this flip-flop 103,
and the synchronous counter through AND gate 105.
106 and count the number of received bits thereafter.
Start. The value of the synchronization counter 106 is per channel.
(10 in this example)
When detected by the decoder 107, the AND gate
108, the shift register of the transfer control unit 400
The contents of the data SROUT match the synchronization pattern again.
If there is a mismatch,
If there is, OR is determined by the output of AND gate 108.
Coincident flip-flop 1 through gate 109
03 and the synchronization counter 106.
Then, again, each bit is received.
Finds a match between the contents of the foot register and the synchronization pattern.
Search. Shift register contents and synchronization pattern continue
If there is a match, one flip-flop 10
3 remains set, at which time the synchronization counter
A signal is sent from the counter 106 to the synchronous character counter 110.
issue and add 1 to the synchronization character counter 110.
Ru. In this way, channels that match the synchronization pattern
When consecutive channels are received, the sync character count
The number of characters is counted in data 110. mentioned above
Assuming that the number of channels in the synchronization area is 4,
For example, if the value of counter 110 becomes 3 and the synchronization
The contents of counter 106 are the same as those of the next fourth channel.
For example, when the value after detecting the period character becomes 3,
In other words, a match is obtained for 4 channels consecutively.
This is detected by the decoders 111 and 107,
And at the timing of the timing signal TIM
Causes AND gate 112 to produce an output and synchronizes
Set the flip-flop 113 and perform synchronous synchronization.
Indicates that the set has been established, and the set output indicates that the
Matched flip-flop through Agate 109
103, synchronous counter 106, synchronous character counter
All the controllers 110 are reset, and
The output of gate 104 is prohibited. Thereby,
Match detection operation is stopped and subsequent information channels
to prevent the contents of the
Stop. On the other hand, the clock counter 114
It is driven and shifted by the timing signal TIM.
Information for one channel of register output SROUT
Create a clock that tells you when to
It is for the purpose of For that purpose, synchronization is possible with AND Gate 112
is detected, the contents of clock counter 114
, the value of the synchronization counter 106, that is, 3
, and the value of the synchronization counter 106 and the clock
By making the values of the counter 114 the same,
Perform phase alignment. On the other hand, clock counter 1
The output of 14 is input to the decoder 115, and the output of
When the value of counter 114 is 0.1, decoder 1
15 outputs the clock signal CLK, and
When the value of the clock counter 115 is 5 or 6,
Outputs clock signal CLK. Also, special
For various purposes, the value of clock counter 115 is
At 4, the clock signal CLK is output. this
The shift register is controlled by CLK as described below.
The output of each channel is transferred to the receive register.
Subsequent processing is possible in units of information for each file. one
On the other hand, this CLK~ is not synchronized.
However, the clock counter 114 is always operating.
Since the
Processing will not be interrupted. The synchronizing flip-flop 113 is set.
When the frame synchronization unit 100
Send channel act signal CHACT to control section 200.
Channel counter in channel control section 200
Start the clock signal CLK timing
Start counting with
That is, the number of channels in the frame (in the synchronization region
Excludes the number of channels. ) is counted. channel
The contents of the counter are the information communication area within the frame.
(Figure 2A Y) reaches a number equivalent to the number of channels.
Then, the end channel signal from the decoder
Sends END CH back to the frame synchronization unit 100,
Synchronous flip through AND gate 116
Reset flop 113. Thereby,
The synchronization detection operation as described above is started and the transfer control is started.
One bit is received in the shift register of the control section 400.
Check if it is a synchronous character pattern every time
Do it again. That will cause the same result in the next frame.
If the current region is successfully received following the end of the previous frame.
A check is made to see if it is believed. Bit extraction of transmission information of loop transmission line 1200
The next step is caused by bits gushing out due to noise, etc.
No synchronization pattern is detected in the synchronization area of the frame.
There may be cases where this is not possible. In this case, within the frame
channel information is not recognized correctly, so
While the synchronization is immediately resumed, processing in the meantime is canceled.
Some kind of action is necessary, such as
Therefore, this synchronization must be detected immediately.
No. Detection of this out-of-synchronization is the end of the previous frame.
Synchronized by end channel signal ENDCH indicating
Matching flip-flop 113 has been reset.
After that, the value of clock counter 114 became 0.
timing, i.e. the synchronization area of the next frame.
All information on the synchronization channel at the beginning of the area is transfer controlled.
The timing input to the shift register of section 400
, no match is found with the synchronization pattern,
That is, the coincidence flip-flop 103 is reset.
If it is, it will generate an output from AND gate 117.
Similarly, set the out-of-sync flip-flop 118.
do. Set of out-of-sync flip-flops 118
Channel the out-of-sync signal STOUT, which is the
It is sent to the control unit 200. This flip flop
The flip-flop 118 is activated when synchronization is achieved.
It is reset by the output of pin 113. (2) Channel control section 200 FIG. 5A shows the specific structure of the channel control section 200.
This shows an example of the structure. As mentioned above, in the frame synchronization section 100,
Synchronization is established and channel act signal CH
When ACT is output, the channel control unit 200
Now, similarly, the clock from the frame synchronization section 100 is
The AND game is activated at the timing of the CLK signal.
Open the port 201 and check the channel counter 202.
Start number. Contents of channel counter 202
is the number of channels in the information communication area within the frame.
When the corresponding value is reached, the decoder 203 sends an end.
Outputs channel signal END CH. flame
Channel act signal CH from synchronization section 100
Impart gate 204 when ACT is turned off
reset the channel counter 202 through
Ru. The output of the channel counter 202 will be described later.
As such, the node act flip-flop 205
is set, AND gate 206
Channel number signal through terminal as CHNO
It is sent to bus 1300. On the other hand, the interface circuit 207 is a processing device.
Write data to the register selected from 300
circuit for reading data
The specific configuration is shown in FIG. 5B, for example.
It seems that In the interface circuit 207 shown in FIG. 5B,
is transmitted from the processing device 300 through the terminal bus 1300.
the synchronization signal SYNC, terminal number TMNO, and recorder.
Register number REGNO, read, write control signal
R/, data D are input, and the matching circuit
In 208, synchronization signal SYNC is included.
At the same time, the terminal number TMNO is sent to the terminal number generator 20.
Compare with the terminal number assigned to you from 9
The read/write control signal is sent when both match.
ANDGATE 210 or
211 produces an output, and the light decoder 2
12 or read decoder 213.
The register number from the processing device 300
Write select to register corresponding to REGNO
Outputs signal WS or read select signal RS.
Ru. At the same time, transmitting gate 214 or receiving gate
215 is also selected, and the data D from the processing device is
Register selected by write select signal WS
or within the selected register.
or send it to a processing device. In addition, the cash register
The register specified by the star number REGNO
However, it also has memory functions such as flip-flops.
It may be something you have. In Figure 5A, the line head channel register
data 216, line termination channel register 217,
Out-of-sync flip-flop 218 and
The node act flip-flop 205 is a processing unit.
It is selected by the register number REGNO from the location.
It is. Line head channel register 216 and line
The end channel register 217 contains information from the processing device.
is sent through the interface circuit 207.
The light select signal WS or RS allows the
First channel number in the circuit-switched area of the frame
and the final channel number are pre-stored.
Ru. Furthermore, the flip-flop 205 is connected to the node
When operating the device, write select signal
Set with data D at the timing of WS
It's becoming like that. Then, the contents of the channel counter 202 are
Must match the line head channel register 216.
When the matching circuit 219 detects
The area flip-flop 220 is set. Also
The contents of the channel counter 202 are
It is the matching time that matches the Janel register 217.
When detected by the circuit 221, the detection signal is sent to the delay circuit 2.
After a certain time delay at 22, the flip-flop
220. flipflop 22
When set to 0, node act fritz
If the flop 205 is in the set state, the AND
Open gate 223 and send line gate signal LING
is generated and sent to the terminal bus 1300. In the processing device 300, an out-of-synchronization state flag is detected.
In order to know the state of lip-flop 218,
Read select through interface circuit 207
Sends signal RS to open buffer gate 224.
and reads the contents of flip-flop 218.
At the same time, the signal is delayed for a certain period of time by the delay circuit 225.
Reset flip-flop 218 by signal
do. In addition, the lead from the interface circuit 207
The register 216 or
or the contents of 217 are Batsufuagate 226 or
is now read through 227.
Ru. (3) Processing device 300 FIG. 6 is an example of a specific configuration of the processing device 300.
This shows that. The processing device 300 includes a processing section 300A and a replacement section.
300B, and the processing section 300A is small.
Kumo processor 301, memory 302 and
It is closer to bus 303. Then, the processor 301 and the memory 30
The bus 303 connected to
drive signal ASYNC, address signal ADRS,
Has read/write control signal R/W and data D.
These signals enter the converter 300B.
Powered. In the conversion unit 300B, the processing unit 300
The upper bits of the address signal ADRS from A are
Address strobe signal
At the ASYNC timing, the upper bits of the address
is set in the address generator 305.
Address indicating access to interface circuit
Checks whether it is a spa pattern and if it matches.
If so, create a synchronization signal SYNC. Also, add
The lower bits of the response ADRS are the terminal number TMNO and
and register number REGNO.
be done. Also, the read/write control signal R/W is
At the timing of the period signal SYNC, AND gate 3
06 and the AND gate.
By 306 and 307, Batsufua Gate 3
Open 08 or 309 to send data D or
performs reception. The various signals created in this way are
Interface of the channel control unit 200 described above
Not only the circuit, but also the terminal control unit 500, link
Control unit 600 and packet interface unit
It is also sent to the 800 interface circuit.
Ru. (4) Transfer control unit 400 FIG. 7 shows a specific configuration of the transfer control unit 400.
This is an example of the transmission/reception unit 400A and the transfer unit
It consists of 00B. In the transmitting/receiving section 400A, the loop transmission path 1
Receiver 401 receives information from 200, and
While demodulating the information, the received information is
Extract the bit timing signal TIM and use this
Shifts information at the timing of timing signal TIM
The data are sequentially stored in the register 402. Next, from the frame synchronization section 100 described above,
At the rising edge of clock signal CLK, the shift register is
The 10-bit output of the star 402 is sent to the receiving register 4.
03 in parallel. On the other hand, in the transfer unit 400B, the reception register 4
Valid display bit and empty table in output of 03
Receive the 2 bits of the indication as is in register 4.
04 and also notes the vacancy indication bit.
The air occupancy indication signal IDLE is sent through gate 405.
and sends it to the terminal bus 1300. receive register
Remaining 8-bit data information of output of 403
as the signal ADDR for address verification.
In addition to sending the packet to the packet control unit 700,
to one input of the task selector 406. Ma
In addition, the other input of the status selector 406
is the status signal from the packet control unit 700.
No. STATB and indicates the presence or absence of errors described below.
A status signal is being input. This stay
In the task selector 406, the packet control unit 70
Responds to status select STATSEL from 0.
Select the transmission data according to the That is, the signal
If not, select the output of receive register 403
When this signal is present, the other input, the step
Select the status signal STAB etc. On the other hand, the status select STATSEL signal is
For example, while receiving the connection control packet area,
It is necessary to send the status back to the 16th channel.
status signals STATB and
and zero detector 417 output. stator
The selected output of the selector 406 is the receive register 4.
Sent to 04. In the receiving register 404, the flag
With the clock CLK from the frame synchronizer 100
Set input data. Receive register 404
The busy control circuit sets the vacancy indication bit in the output of the
407 and other remaining 9-bit received data.
When the data is sent to the terminal bus 1300 as RD,
Also, if input to one side of mode selector 408,
Ru. In addition, data information 8 of the reception register 404
The registers that make up the bit output FIFO memory 409
Input to register 1. In the FIFO memory 409,
The output of the reception register 404 is sent to the register 409-
At CLK timing at 1,409-2,
409-3 has sequential cases at CLK timing.
pay. Therefore, the output from the FIFO memory 409 is
The received data is delayed by two channels.
and link as packet reception data PAKD.
It is sent to the control section 600. Here FIFO memory
409 was used in the connection control packet.
The destination address is the third channel, and the destination
Determine that the address is your own address
This is because it is necessary to import the received data.
Ru. The other input of mode selector 408 has an
Transmission data SD from terminal bus 1300 is input.
This selector 408 selects the
Mode select signal from control unit 700
When MODSEL is turned on, the transmit data SD is selected.
mode select signal MODSEL is turned off.
Then, select the output from the receive register 404.
do. The busy control circuit 407
Busy on signal BUSYON from 00 is on.
At some point, the block indication bit in the received information is blocked.
Set the busy off signal to force
When BUSYOFF is on, the vacancy display bit
The default setting is forcibly set to display empty. other than that
At this time, the busy control circuit 407
The function to output the signal from the controller 404 as is.
I have it. Next, busy control circuit 407 and mode
The output of the clock 408 is tied to the clock CLK.
It is set in the transmission register 412 at the timing. sending
Among the outputs of the communication register 412, the occupancy display bit
The two valid display bits are sent and received as is.
input to the transmission register 413 of the transmission section 400A.
Ru. On the other hand, the remaining 8-bit data information is
Input to selector 414 and arithmetic unit 415
be done. The check register 416 is a packet control section.
0 due to reset signal BCC RST from 700
After the initial settings are made, the packet control unit 700
By the check operation start signal BCC ACT,
Operate the arithmetic unit 415 and check the check register.
The output of 416 and the output of transmission register 412 are
Performs the calculation and sends the result to the clock CLK.
Set in check register 416 at timing
do. This operation is a division by a specific constant, and the transmission
This is a method commonly used to check transmission information.
be. These operations are performed by, for example, connection control packets.
Sends data information for channels 1 to 14 in the target area.
repeated for a period of time. A packet is sent to the 15th channel.
Check select signal from control unit 700
BCCSEL is sent to selector 414 and select
At that timing, the arithmetic unit 414
Select the output of 5 and send it to the transmission register 413
do. The zero detector 417 detects all bits of the arithmetic unit 415.
is a predetermined value, for example, 0.
The output can be used as a status signal.
Along with STATB, status selector 406
is being entered. In short, zero detector 417
is 1 to 15 channels in the connection control packet area
The calculation results for each bit of data information are all examples.
For example, there is an error in the data information depending on whether it becomes zero or not.
It detects whether there is a
16th channel status chart in the butt area
It is designed to be placed on a flannel. In the transmission register 413 of the transmission/reception section 400A
is the clock from the frame synchronizer 100
At the timing of CLK, the transmit register 412
and set the output of check selector 414.
Then, the contents are set to 1 using the timing signal TIM.
The signal is shifted bit by bit and sent via transmitter 418.
transmission line 1200. Furthermore, as described above, the frame synchronization unit 10
When set to 0, the clock will start even if frame synchronization is not established.
Since the lock timing is generated, it is not possible to receive it.
Information can now be transferred at any time. (5) Terminal control unit 500 8A and 8B show the terminal control unit 500
Fig. 8A shows an example of a specific configuration of
Its basic part, Figure 8B, shows the empty channel selection section.
are doing. In the basic part of Figure 8A, the interface
The circuit 501 is composed of a circuit similar to that shown in FIG. 5B.
and transmits and receives data to and from the processing device 300.
Let's do it. The transmission channel register 502 indicates the times to be transmitted.
This stores the channel number within the line switching area.
Yes, the reception channel register 503
Store the channel number in the circuit-switched area
It is something. Also, the contents of the mode register 504
The content consists of 4 bits of information, of which 2 bits
ports 504-1 and 504-2 are bus connections during transmission.
This shows how to continue. 504-1 is terminal bus 1
Loop transmission line 12 via transmission bus within 300
Indicate when to send data to 00, 504
-2 is an end to another terminal control unit in the same node device.
Data is transferred via the internal bus within the terminal bus 1300.
Indicates when to send. Also, the remaining 2 bits of the mode register 504
504-3 and 504-4 are bus connections during reception.
bit 504-3 indicates the loop
From the transmission path 1200 to the reception bus of the terminal bus 1300
Indicates that the data is received via the
504-4 controls other terminals within the same node device.
via an internal bus within terminal bus 1300 from
This shows the case of receiving data. These transmission channel registers 502 and reception channels
Janel register 503 and mode register 5
04, the signal from the interface circuit 501 is
Data D is set by the write select signal WS.
In addition, these cash registers
Reads the outputs of stars 502, 503 and 504.
Buffage is determined by the select signal RS.
via ports 505, 506 and 507.
It is now being incorporated into the Tough Ace circuit 501.
Ru. Also, transmit and receive channel registers 50
2 and 503, as detailed in FIG. 8B.
The clock after a hunt request is
CLK timing HTCLK-S and R
Register and update your channel number CHNO, and then
When an empty channel occurs in the line switching area, the channel
It is now possible to finally register your Janel number.
It's on. Transmission of mode register 504
Either 504-1 or 504-2 which is an instruction
OR gate 5 that detects that is set
Transmit channel register only when there is 24 output
Output of 502 is matched by AND gate 508
It is output to circuit 510. Similarly, the transmission mode is set by the OR gate 525.
504-3, 504-4 of the register 504
detects that one of the
The output of the Yarnel register 503 is passed through the AND gate 5
09, it is output to the matching circuit 511. Note that registers 502 and 203 have interfaces.
The processing device 300 via the phase circuit 501
For example, whether the other party sets the data
Receives connection control packets from
This is the case when a channel number is specified. Data is set in registers 502 to 504.
After the transmit channel register 502 and
The contents of the communication channel register 503 and the channel
The match circuit 510 detects a match with the number signal CHNO.
and 511 for detection. Channel number signal and send channel register
A match with 502 is detected in match circuit 510.
and bit 504-1 of mode register 504.
If the content of is 1, the AND gate 512 is opened.
and transmits the mode signal MODE to terminal bus 1300.
At the same time, it is sent to
to open the buffer gate 514 and send the buffer
Sends the contents of address 515 to terminal bus 1300
Ru. On the other hand, in the terminal device 1000, the transmission data is
When all is completed, the transmission request signal SREQ is turned on.
8-bit transmission data is sent to the transmission buffer 515.
At the same time as setting the data SD,
Set the flop 516 and read the output of the 516.
The signal is used as a valid display bit, and the buffer gate
Terminal with data information when 514 is opened.
Transfer control as send data SD to bus 1300
400. In the transfer control unit 400,
As mentioned above, the mode corresponding to the mode signal MODE
Mode selection is performed by the mode selection signal MODSEL.
to send data SD to other nodes.
Send to device. The coincidence output of the coincidence circuit 510 is delayed by the delay circuit 517.
OK to send delayed signal to terminal device 1000
While it is sent as a signal SOK, it is also sent as a transmission request free.
Reset flip-flop 516. Therefore,
Transmission data from terminal device 1000 is not collected
If a channel number match is detected before, the device
Before sending the data, the transmission request flip-flop 51
6 has been reset, the transmission data SD
The valid display bit becomes 0, and the transmitted data
is displayed as invalid. In short, the end
The processing speed on the terminal device 1000 side is slow and the sending data is slow.
If the data is not aligned, it will be displayed as invalid.
Therefore, there is no limit to the processing speed on the terminal device 1000 side.
It disappears. Next, the match circuit 510 detects a match.
bit 504-2 of mode register 504
If is 1, the AND gate 518
Open the firegate 519 and check the transmission data mentioned above.
data to the internal bus as internal bus data IND.
put out On the other hand, the output of the receiving channel register 503 is
Can match the channel number from the terminal bus
When detected by the matching circuit 511, the mode register
Bits 504-3 and 504-4 of data 504
Perform the following actions depending on the situation. In other words, the reception selector 520 has a reception bus
Receive data RD from
communication data IND has been input, and this select
In the mode register 504, the bits in the mode register 504 are
When 504-3 is 1, select receive data RD
However, when bit 504-4 is 1, the internal bus
Data IND is now selected. this
Among the data selected in this way, data information
input into the reception buffer 521 and check the valid display bit.
is applied to AND gate 522. Valid display
The valid indication signal of the bit and one of the matching circuits 511
The output of the AND gate 522 is
on, and the output of the receive selector 520 is set to the receive bar.
In addition to setting the data to the buffer 521, the reception request is
Set flip-flop 523. This frame
Request to receive set output of lip-flop 523
Send to terminal device 1000 as signal RREQ
At the same time, the contents of the reception buffer 521 are transferred to the reception data.
The data is sent to the terminal device 1000 as data RD.
The terminal device 1000 receives the reception request signal RREQ.
When received, sends back the reception OK signal ROK and requests reception.
Reset flip-flop 523. In this way, the AND gate 522 enables
Reception is only possible when the display bit is valid.
The data is now imported to the terminal device 1000.
data, so the sending terminal device can receive the complete data.
It will only be received when sent as a data.
data without being limited by the speed of the terminal device.
can be sent and received. Next, according to FIG. 8B, the empty channel selection function
I will explain about it. In addition, Figure 8B shows the transmission or
Empty channel selection function when either receiving or receiving
Only the relevant circuits are shown, but in practice
The circuit of FIG. 8B corresponds to transmission and reception.
There will be two. In such a configuration, the processing device 300
Hunt via the interface circuit 501.
When a request is sent, the clock CLK is
Open and gate 531 at timing and hunt
Set request flip-flop 532. C
The client request flip-flop 532 is set.
, hunts and displays circuits indicating receipt of circuit-switched areas.
Line gate signal LING and channel of received data
Empty indication signal indicating that is an empty channel
IDLE and hunt request flip-flop 532
The output is input to the AND gate 533, and the above-mentioned
When the hunt conditions are met, AND gate 53
3, the output signal is delayed by a predetermined time by a delay circuit 534.
After delay, get empty channel flip-flop 5
35 and hunt request fritz.
Reset flop 532. On the other hand, Han
request flip-flop 532 is set.
AND gate by clock CLK while
536 to get the signal HTCLK and this signal
Channel register 502 or 50 of FIG. 8A
3, and at that timing, enter the channel number.
The signal signal CHNO is sent to the channel register 502 one after another.
Or import it into 503 and update it. mentioned above
so that an empty channel is detected and the hunt request flow is
When the lip flop 532 is reset, the reset
Since the register import operation is stopped, the final
The channel number corresponding to the empty channel is
It will be stored in the register. The output signal of the delay circuit 534 is sent to the OR gate 53.
7 to the delay circuit 538, where the
The packet is sent as a busy signal BUSY after a fixed time delay.
A busy-on signal is sent to the control unit 700.
Convert to BUSYON. Thereby, transfer control
The blockage display screen of the corresponding channel being transferred by the section 400
Set the hunt to block and hunt on other terminal devices.
prohibit. From then on, even after the hunt was established, the figure 8A
Coincidence output COIN− of matching circuit 510 or 511
S or R and gate 539 and orage
is input to the delay circuit 538 through the gate 537,
After a predetermined time delay in the delay circuit 538, the same
Sends as busy signal BUSY and
Turn the button into a closed position. Note that the delay circuit 538
is provided to maintain proper timing.
There is. Flip-flop 535 is set and the handle is
After the set is established, the set output
Closes the end gate 531 and prevents future hunt requests.
prohibited and prevents double channel hunting. On the other hand, when the data transmission or reception is finished,
When releasing the occupied channel, the processing device 3
According to instructions from 00, interface circuit 5
Send the write select signal WS from 01 and select
AND gate 5 at the timing of lock CLK
Open 40 to request release flip-flop 541
Set. And the channelle in Figure 8A
Contents of register 502 or 503 and channel number
Wait until a match with the signal CHNO is detected,
A match is detected in match circuit 510 or 511
Signal COIN-S or COIN-R is output.
Then, the output from AND gate 542 is
A delay circuit 543 for adjusting the timing is delayed for a predetermined time.
After that, packet control of empty display OK signal IDLEOK is performed.
A busy off signal BUSYOFF is sent to section 70.
is sent to the transfer control unit 400 and the occupied channel is
Forcibly set the empty block display bit to empty. At the same time, release request flip-flop 5
41 and empty channel acquisition flip-flop 5
35 to complete the release operation. Additionally, multiple terminals within the same node device may be controlled.
so as not to put the hunt request state on all the parts at the same time.
Under program control within the processing unit, only one
empty channel.
Prevent multiple terminal control units from hunting for
are doing. In the embodiment described above, one channel per terminal device.
When transmitting or receiving by exclusively occupying
As explained above, multiple channels per terminal device
You may also assign it. Figure 8C shows this
Configuration of an example of the main part of the basic part of the terminal control part in case
This shows that. In the figure, channel registers 551, 552
is used for both sending and receiving, and these
Contents set in register and channel number signal
Matching with CHNO is detected by matching circuits 555 and 556.
and when a match is detected in any matching circuit,
It is output from the OR gate 557. On the other hand, speed adjustment of the terminal interface for sending and receiving
FIFO for transmit and receive respectively
Memories 558 and 559 are provided. This FIFO memory 558 contains terminal equipment 100
Timing of transmission request signal SREQ sent from 0
The data is valid, along with the sent data SD.
A valid display bit is stored to indicate that the Once a match is found as described above, the detection
The signal is delayed for a predetermined time by the delay circuit 560, and then
Stored in FIFO memory 558 at the timing of the delayed signal.
Read the stored transmission data. At this time, the data
When transmitting
depending on the contents of the fields 504-1 and 504-2.
Perform the same operation as described in Figure 8A. On the other hand, when receiving data, the mode register
Bits 504-3 and 504-4 of star 504
As mentioned in Figure 8A, depending on the content of the received
Select data RD or internal bus data IND
520 and the selected data is valid.
Sometimes, the data is sequentially stored in the IFFO memory 559.
Store and read the contents at a predetermined timing
Send as received data RD to terminal device 1000
Ru. Also, corresponding to the channel register 551, the
It has an empty channel selection function as shown in Figure 8B.
circuit is provided, in which case the andgame
Output signal of port 536 HTCLK-1 to HTCLK-
Apply n to channel registers 551-552,
At that timing, check the channel number CHNO one after another.
Import and update into Janel registers 551-552
do. Also, each bit of the mode register 504
The OR gate 563 takes the logical sum of the outputs and selects the mode.
Any bit in register 504 is set to 1.
Channel registers 551-5 only when
The output of 52 passes through AND gates 553 and 554.
and output to matching circuits 553-554. Also,
Coincidence output COIN-1 of coincidence circuits 555 to 556
COIN-n to each AND gate 539 and
and 542. Also, the logical sum of the outputs of each delay circuit 538
The output taken by the OR gate is the busy signal BUSY.
and each delay circuit 5
43 outputs in the same way, and the output is
The empty display OK signal is now sent as IDLEOK.
It's on. In addition, the lead from the interface circuit 501
Buffer gate 561 is activated by select signal RS.
and 562 to open the channel register 551
It is also possible to import the contents of ~552 into the processing device.
Ru. In the embodiment described above, the mode register 50
4 and an internal bus, the same node
between any two terminal control units in the terminal device
It has become possible to communicate with
This will be explained in detail with reference to the drawings. The figure shows a transfer control unit 400 and a plurality of terminal control units 5.
This shows the connection relationship with 00A and 500B.
The terminal bus 1300 is the bus necessary for connection between them.
bus 13 for the mode signal MODE.
01, transmission bus 1302 for transmission data SD, reception
Reception bus 1303 for communication data RD, internal bus de- vice
Internal bus 1304 and channel for data IND
It has a bus 1305 for the number signal CHNO. Terminal control unit 500A in the same node device and
When communicating between 500B and 500B, the terminal control unit 5
Transmit channel registers in 00A and 500B
502 and receive channel register 503, respectively.
Set the same channel number. Below is an example of how to set the channel number.
I will explain. One terminal control unit on the sending side, for example
For example, at 500A, find an empty channel and
When a channel is found, the channel number is sent to the outgoing channel.
channel register 502. Processing device 300
Now, the channel number set in this register 502
load the same channel number, and connect the same channel number to the same end.
Reception channel register 50 in end control unit 500A
3, and other terminal control unit 500
Transmit and receive channel registers 502 and
and 503 as well. In addition, the processing device 30
0, the mode register in the terminal control unit 500A
At 504, the receiving side connects the receiving bus 1303,
The receiving side instructs connection to internal bus 1304.
In this case, set bits 504-2 and 504-3 to 1.
At the same time, the mode register in the terminal control unit 500B
In star 504, the receiving side is connected to internal bus 130.
4. The sending side instructs connection to the sending bus 1302.
Set bits 504-1 and 504-4 so that
Leave it at 1. As a result, the transmitter 59 of the terminal controller 500B
The transmission information from 0B is shown in the bold line in Figure 8D.
Then, the transfer control unit 40 via the transmission bus 1302
0 and similarly sends a mode signal to bus 13
01 to the transfer control unit 400. The transfer control unit 400 determines the mode of the bus 1301.
Transmission information is set by turning on the signal.
loop transmission line 1200 on the channel numbered
Send to. In this way, the loop transmission line 120
The transfer control unit 400 takes in the information that circulated around 0.
and the terminal control unit 500 via the reception bus 1303.
A's receiving unit 591A. On the other hand, from the terminal control unit 500A to the terminal control unit 50
When sending information to 0B, the thick line in Figure 8D
The transmission unit 590A of the terminal control unit 500A
The transmission information is sent to the internal bus 1304 from
The data on the internal bus 1304 of the terminal control unit 500
The receiving unit 591B of B receives the received information. Also, the dotted line in the figure is the signal for the opposite case as described above.
The route is shown. Link control unit 600 The link control unit 600 performs
The packet data of connection control packet area A (hereinafter
Transmission and reception processing of (abbreviated as "downlink packet data")
It is something to do. The structure of this link control section 600
The configuration and operation are based on data during packet switching function.
The configuration and operation of the equipment that sends and receives data, and the terminal interface.
Other than the face, they are almost the same. FIG. 9 shows the configuration of the link control section 600.
This is an example. In the same figure, 602 and 603 are registers.
from the processing device 300 described above to the interface section.
601, the connection control packet area A (hereinafter referred to as link
(abbreviated as link packet area)
The number and end channel number are respectively initialized.
Ru. Therefore, for example, a frame structure as shown in FIG. 2B
In this case, the link head channel register 602 contains
Channel number 5, link end channel register 6
03 shall be set to the value of channel number 20.
become. Channel numbers are stored in each register 602 and 603.
When setting the data representing the number, set each register.
A line that specifies a pre-assigned address for the
Set select signal WS and channel number to be set
Applying data D representing the number to the register.
This is realized by Also, each register 602, 60
Read select signal RS specifying address 3
is applied, the chip stored in each register is
The data representing the Janel number is
It is read out via gates 608 and 609. The outputs of both registers 602 and 603 are channel
Sent from the control unit 200 through the terminal bus
Match each with channel number information CHNO
It is added to detection circuits 604 and 605. Match detection
Circuit 604 stores the contents of register 602 and the channel.
Output signal when number information CHNO matches
This causes the start timing circuit 606 to start.
be moved. This timing circuit 606
Tie synchronized with clock CLK in Yanel
Outputs signal STCH to timing. On the other hand, match detection
The circuit 605 stores the contents of the register 605 and the channel.
Output signal when the number information matches CHNO
This causes the end timing circuit 607 to
will be activated. This timing circuit 607 ends
synchronized with the clock signal CLK in the channel.
The signal TECH is output at the specified timing. By activating the top timing circuit 606,
After the first channel signal STCH passes through the terminal bus
The packet data is sent to the packet control unit 700 described above.
Start data transmission/reception control. Also, due to the activation of the termination timing circuit 607,
Similarly, the end channel signal TECH is packet-based.
The packet is sent to the control section 700 and the packet transmission/reception control is completed.
let 631 is output when channel number CHNO is zero
It is a zero detection circuit that outputs
The output of the match detection circuits 604 and 605 is prohibited.
Ru. This circuit 631 is provided in the
If packet area A is not specified at all, register
In order for the contents of stars 602 and 603 to become 0, the previous
The first channel number 0 of the synchronization area
Detected and false timing signal STCH,
This is to prevent TECH from appearing. Next, we will explain the packet data transmission operation.
Ru. A packet to be transmitted is created by the processing device 300.
is created and sent via the interface section 601.
FIFO buffer memory circuit (hereinafter abbreviated as FIFO) for
)612. this write
As mentioned above, is allocated in advance to the transmit FIFO 612.
Write select signal that specifies the address
WS and packet data D to the above transmission FIFO 61
This is achieved by applying 2. After writing the packet data is completed, the processing
A transmission request signal is sent from the device 300, and this
via the interface section 601
applied to loop 610. This flip flop
The AND gate 623 is opened by the output Q of the output. The contents of the first channel register 602 and the channel
The number CHNO matches the first timing circuit.
When the 606 starts, its output becomes the first channel signal.
At the same time, it is sent out to the terminal bus as a number STCH.
It is applied to the AND gate 623. This Ann
The AND output of the gate 623 is the OR gate 625
sent as status signal STATA via
It will be done. This status signal STATA is packet based.
It is sent to the control section 700 and connected with the timing signal STCH.
I learned that I had to take the product and that there was a transmission request.
let Also, the output of the first timing circuit 606
The flip-flop 611 is set and its output is
Force Q is applied to AND gates 626 and 628
Ru. As a result, the
It becomes possible to receive the transmission gate signal SG. On the other hand, in the packet control unit 700, the link packet
Look at the first bit of area A and see if it is an empty area.
When this is confirmed, the transmission gate signal SG is sent out.
This transmission gate signal SG is the AND gate 62
6 to an AND gate 620.
Therefore, while the transmission gate signal SG is on, the clock
The signal CLK enters the transmit FIFO 612 and this clock
The data is stored in the transmit FIFO 612 in synchronization with the
The packet data is sequentially transferred to the interface section 627.
sent through. This sending data SD is sent
The mode of the above-mentioned transfer control unit 400 via the bus
is added to selector 408. Also, transmission gate
Send request flip-flop 610 by signal SG
Reset. This will wait for the next send request.
becomes the state of The contents of the link end channel register 603,
If the channel number CHNO matches, the above
The timing circuit 607 outputs the end channel signal.
Send out TECH. This exit channel signal
TECH is connected to the packet control unit 7 via the terminal bus.
Enters 00. The packet control unit 700 will be described later.
Complete the packet data transfer process and send it.
Turn off the gate signal SG. This allows you to send
Gates 620, 627 connected to FIFO 612
is closed and the packet data of link packet area A is
Terminates the sending operation. Next, the packet sent from the other party's node device is
The operation of receiving the cut data will be explained. The above also applies to node devices that receive data.
Similarly, based on instructions from the processing device 300, the link
Start channel and end channel number of packet area A
Set the numbers in registers 602 and 603 respectively.
Ru. First channel number set in the same way as above
and the channel number sent via the terminal bus.
When the number CHNO matches, the first channel signal
STCH is sent to the packet control unit 700. Pake
The destination control unit 700 inputs the destination address as described below.
Detects a match between the address of the host and its own node device.
Then, the reception gate signal RG is turned on. The above reception gate signal RG is sent to the link control section 700.
is added to the gate 628 of the transfer control unit 400.
Their packet data PAKD is stored in the reception FIFO 613.
Added. Flip-flop 611 is the first chip
Since it is set at the timing of the
Output Q causes AND gate 628 to be open.
Therefore, the receive gate signal RG passes through gate 628.
is applied to the AND gate 621. This reception game
While the clock signal RG is on, the clock signal CLK
enters the receive FIFO 613, and the packet is synchronized with this.
The data PAKD is imported. Receive FIFO6
The packet data stored in 13 is processed by processing device 30.
Read by 0. That is, this receive FIFO
Read select signal that specifies the address of 613
When RS is applied, packet data is gated
Sequentially read out to the processing device 300 via the front panel 617
be done. On the other hand, if there is an overflow in the receive FIFO 613,
The signal representing nothing is sent to the end timing circuit 607.
is added to the AND gate 624 along with the output.
Ru. Timing to send end channel signal TECH
When the data stored in the receive FIFO 613 exceeds the
-When you are in a flow state, the above AND gate 6
24 produces an output, which is the status signal.
It is sent to the packet control unit 700 as STATA.
Ru. End of link packet area A (see Figure 2B)
When a channel is detected, the termination timing circuit 6
The flip-flop 611 is activated by the output signal of 07.
The gate 627 is reset, and as a result, the gate 627 is closed.
Data reception processing is completed. The output of AND gate 628 turned on and off.
The change causes one bit in status register 615 to change.
is set to on. The processing device 300 is
Assigned in advance to the status register 615
The read select signal RS that specifies the address
The contents of the register 615 are gate-crossed.
By reading the data through the
You can know when reception has ended. This reception is complete
is notified to the processing device 300 by interrupt processing etc.
You can also Resetting the status register 615
The mode select signal RS is passed through the delay circuit 616.
applied to the reset terminal of that register 615.
Ru. Therefore, the contents of register 615 are read out.
After that, it will be automatically reset. Next, the packet data sent from the sending node device is
The data travels around the loop-shaped common transmission line and then returns to its own state.
Remove this when you return to your node device.
We will explain the process of importing. The packet control unit 700 is the link control unit 600.
When the first channel signal STCH is received from
The originating address of the channel and the own node device
Find a match with an address. Both addresses match
This means that the received data is
The data sent from the card device goes around and comes back.
It means that it is something that Both addresses match
The packet control unit 700 then completes the process as described below.
sends out the completion gate signal TEG, which connects the terminal bus.
It is added to the link control unit 600 via the link control unit 600. child
The end gate signal TEG is the OR gate 629, and
and the AND gate 62 through the AND gate 630
Enter 2. Therefore, the clock signal CLK is
Add the AND gate 622 to the transmit end FIFO 614.
packet data from the transfer control unit 400
PAKD is sequentially taken into the transmission end FIFO 614.
Ru. As described later, this termination gate signal TEG
On and off during the entire period of link packet area A.
At least the address information is not familiar.
channel period (A in the example in Figure 2G)₀From A₃of
channel period).
On the other hand, the status gate signal STATG is
channel period of information (A in the example in Figure 2G)₁₅of
channel period).
Therefore the termination gate signal TEG and the status gate
The packet is turned on only while one of the signals STATG is on.
A transmitter that operates to capture data PAKD.
The signal end FIFO 614 is A₀~A₃and A₁₅Chiyane of
This will import data from the file. This is the end of transmission.
This function allows you to selectively receive only the information you need at the time of completion.
Ru. Of course, the end FIFO sends information other than the above
614. The processing device 300 is
Displays the address assigned to the sending end FIFO 614.
By sending the wasu lead select signal,
Buffer the data stored in this FIFO614.
It can be read out through gate 618. Packet control unit 700 The packet control unit 700 controls the link packet area.
Sending packet data of A and packet exchange area D
Also used to generate timing signals necessary for reception.
It is. For convenience of explanation, the link packet below is
The case of sending and receiving data in an area will be described. FIG. 10 shows an embodiment of the packet control section 700.
The circuit configuration is shown. The first channel sent from the link control unit 600
The channel signal STCH and the end channel signal TECH are
Head timing circuit 70 of packet control unit 700
1 and end timing circuit 702, respectively.
It will be done. These timing circuits 701 and 702 are
Start channel and end channel of link packet area
Signal synchronized to the channel and any channel
This is also used to create a timing signal that is delayed by the amount of time.
It is. Based on these timing signals
Timing required for sending and receiving data as explained below
A signal is created. First, let's talk about the operation when transmitting packet data.
I will explain. As mentioned above, the information sent from the link control unit 600
The status signal STATA that comes is packet data.
means a request to send. If this request is made,
The packet control unit 700 hunts for empty packet areas.
Start operation. First, the first channel of link packet area A
A₀vacancy display bit A₀₀(See Figures 2F and 2G)
check), that is, check the contents of the idle signal IDLE.
do. Idle signal IDLE is on (or “1”)
, check that the link packet area is free.
When it is off (“0”), it means it is closed.
shows. When the idle signal IDLE is off, the
The gate 713 is closed and the transmission operation has started.
Wait until the first channel comes again. If the idle signal IDLE is on, the
The transmission flip-flop is activated by the output of the gate 713.
705 is set, and its output Q is connected to the transmitting gate.
is sent to the link control unit 600 as a signal SG.
Ru. The link control unit 600 uses this transmission gate signal.
When SG is received, the transmission FIFO 612 is
Send the stored data sequentially to the transfer control unit 400
Ru. At the same time, the output Q of the flip-flop 705
passes through the OR gate 720 and outputs the mode select signal.
It is added to the transfer control unit 400 as MODSEL.
The transfer control unit 400 receives a mode select signal.
When MODSEL is input, the link control unit 600 sends
Sends the incoming transmission data SD. Also, the output Q of the flip-flop 705 is
Busy-on signal via OR gate 719
It is sent to the transfer control unit 400 as BUSYON.
Ru. This signal is a busy signal in the transfer control unit 400.
is applied to the control circuit 407, and the link packet area
A's blockage display bit A₀₀is displayed as blocked. On the other hand, the signal generated from the leading timing circuit 701
First channel A₀Check the signal synchronized with
It is sent to the transfer control unit 400 as a switch signal BCCRST.
put out Transfer control unit 4 uses this signal BCCRST.
Contents of block check register at 00
BCCR is initialized to zero. On the other hand, the signal at the next timing causes frizz.
Pflop 703 is set and its output Q
The transfer control unit 40 uses the transfer operation signal BCCACT.
Sent to 0. When this signal BCCACT is input,
Block check calculator 41 of transfer control unit 400
5 output to block check register 416 in order.
The next setting operation starts. After that, it notifies the end of link packet area A.
The end channel signal TECH is sent to the link controller 60.
When it is sent from 0, the end timing circuit 70
2 is activated. This circuit 702 is in the data area.
Later check bite (channel A in Figure 2G)₁₄)
Create a timing signal that should be transferred and apply this to
Block check selection via command gate 718
is sent to the transfer control unit 400 as a block signal BCCSEL.
put out When this signal BCCSEL is input, the block is
The check selector 414 stores the check calculation results.
The contents of the block check register 416
Check code channel of link packet area A
Le A₁₄(See Figure 2G) and send it to the common transmission line.
put out Also, the timing from the end timing circuit 702
Flip-flop 705 transmits by timing signal
is reset and its output Q is turned off, so
Transmission gate SG, busy-on signal BUSYON and
All mode select signals MODSEL are turned off,
The sending operation ends. Next, the link packet sent from the originating node device
data goes around the loop transmission path and returns to its own node.
The operation when returning to the device will be explained. As in the case of transmission, the link control unit 600 sends a message to the terminal.
The first channel signal STCH is sent as a packet via the bus.
input to the start timing circuit 701 of the start control section 700.
This circuit 701 is activated. Also, the transfer control unit
The address which is the output of the receive register 403 of 400
The packet control unit 700 matches the packet control unit 700 with the matching signal ADDR.
It enters the output circuit 710. The coincidence detection circuit 710
First channel A of link packet area A₀of Thailand
At the timing, the address signal ADDR and the address
Address of own node device generated from generator 711
Detect whether the response signal matches the response signal. Main implementation
In the example, as is clear from Figure 2G, the first channel
Nell A₀has an originating node address assigned to
Therefore, this channel A₀and the address
This means that the address of the source generator 711 matches.
is the packet data sent from its own node device.
that the data has gone around the loop transmission path and returned.
means. Therefore, at this time, the received data is automatically
Import it into your own node device and complete the process of completing the transmission.
Ru. First, if the above two addresses match, the andgame
The output of the gate 714 causes the flip-flop to terminate the transmission.
706 is set. This flip flop
The output Q of 706 passes through the OR gate 721 and
Transfer control unit 40 as g-off signal BUSYOFF
0 busy control circuit 407. busy
The control circuit 407 controls the start of the link packet area A.
Bit A₀₀is set to “0” (displayed empty), and other nodes
Enable the device to use the above packet area A.
Ru. On the other hand, the timing circuit 701
Address information of target area A (A₁~A₃channel)
is sent from the transfer control unit 400 to the link control unit 600.
Flip-flop 70 ends at the timing when it is issued.
Create a timing signal that turns on 7.
This timing signal is connected to the set terminal S of 707 and
Apply to reset terminal R. Also status buy
(Channel A)₁₅information) is the transfer control unit 400?
At the timing when the data is sent to the link control unit 600
Turn on status flip-flop 708
The flip-flop 72 outputs a timing signal such as
3. Create with AND gate 716 etc., and use this as
Apply to set terminal S and reset terminal R of 708
do. And both flip-flops 707, 7
The outputs of 08 and 08 are respectively the termination gate signals TEG and ST.
Link control unit as status gate signal STATG
600. The link control unit 600 controls the game as described above.
The period when the output signals TEG and STATG are on, that is,
Channel A₀~A₃and A₁₅Send information on end FIFO
It operates to import into. In addition, as mentioned above, the flip-flop 707,
708 is turned on only for a predetermined period.
The timing circuit 70 generates the timing signal.
1,702 as a counter or shift register
This can be easily achieved by using
Ru. Next, the packet sent from the originating node device
The operation when receiving data will be explained. In this embodiment, the third channel of link packet area A is
Nell A₂(See Figure 2G) has the destination node address.
If you want to receive data, please use the channel.
Nell A₂address information and its own node device.
A match with the address must be detected. child
First, the timing circuit 701
Yanel A₂Create a timing signal that synchronizes with
This is applied to AND gate 717. On the other hand, an answer sent from the transfer control unit 400
Address signal ADDR and own node device address
The match detection circuit 710 compares the
Nell A₂If both addresses match at the timing of
The output passes through the AND gate 717 and receives the reception signal.
Applied to the set terminal of flip-flop 709.
Both addresses must match at the above timing
In this case, the sent packet data is sent to the own node.
This means that the information is addressed to the device. therefore received
To start operation, the packet control unit 700 resets
For the link control section 600, the flip-flop 70
Sends the output Q of 9 as the reception gate signal RG.
Ru. The problem here is that each node device
It is only in the third stage that it is determined whether or not to receive the
When channel destination node address information is received
However, if it is determined that it should be received,
1st channel A₀the source node address and the second
Channel A₁It is necessary to capture the source terminal address of
The point is that there is a point. For this purpose, the first,
2 channel A₀,A₁information is also temporarily stored.
It is needed. FIFO of the aforementioned transfer control unit 400
Memory 409 delays packet data by two channels.
This is used to spread the first
Channel A₀allows receiving data from
Ru. In other words, the packet control unit 700
When the route signal RG enters the link control section 600, this
In synchronization with this, the transfer control unit 400 transmits the first channel.
A₀From 16th channel A₁₅is the packet data PAKD
It enters the link control unit 600 as
It will be incorporated into the 13th. On the other hand, the timing circuit 702
Channel A of status byte of target area A₁₅same as
Create a specific timing signal and use it as an andgame.
applied to gate 722. Receive flip-flop 7
After 09 is turned on, the above channel A₁₅of Thailand
AND gate 722 opens at timing, and its output becomes
Transferred as status select signal STATSEL
It is sent to the control section 400. In the transfer control unit 400
receives the status select signal STATSEL
Then, status information STATB indicating the reception status is displayed.
The above channel A₁₅Receives packet data on
It is sent to the communication register 404. The above status message
No. STATB is a separate stage as seen in Figure 10.
status signal STATA and end channel signal TECH
The delay circuit 704 outputs the logical product with
Created by delaying. Also, stay
As can be seen from Figure 9, the status signal STATA is
When performing logical AND with TECH, receive FIFO 613 is turned on.
- indicates whether the bar has flowed or not.
Ru. The above explanation is based on the data in link packet area A.
Described timing control for transmission and reception.
However, in the case of sending and receiving data in the packet switching area,
Since they are exactly the same, their explanation will be omitted. Packet interface section 800 The packet interface section 800 converts into packets.
Configuring the interface between device 1100 and other devices
packet exchange area D (Figure 2C,
(see 2D diagram)
cormorant. Configuration and operation of this interface section 800
is the same as that of the link control unit 600 (see FIG. 9).
Since they are almost the same, only the different parts are explained below.
explain. Figure 11 shows the packet interface section 800.
This figure shows the frame configuration control section of the
The parts are the same as in Figure 9. The packet exchange area D is clear from Figure 2C.
In the case of this example, a maximum of 4 areas can be placed in a frame.
It is possible to set. Therefore the leading channel
For each 4 sets of registers and end channel registers
need to be considered. Therefore, here we will introduce the 4-word register.
A stuff aisle memory 822 is used. First chi
Structure of channel portion 810 and end channel portion 820
The structure is the same, and here we will use the first channel as a representative example.
The register portion 810 will now be explained. First channel number of each of the four packet exchange areas
are stored in the register file memory 82 in order from the youngest
Initialize to 2. This setting can be changed from the processing device to the
Write select to specify address of memory 822
Signal WS and data D indicating each leading channel number
This is achieved by sending the . Processing device 30
The signal from 0 is sent to the data via interface section 801.
After entering the coder 811 and being decoded here, the cashier
It is set in the stuff file memory 822. maximum
If the area is not divided up to the number of divisions 4, the remaining
Set the register contents to 0. The decoder 811 includes a channel control section 200
The node act signal NODEACT sent from
The channel level is applied only when it is off.
Register numbers can be read and written. child
The node act signal NODEACT is as mentioned above.
Activate or stop the operation of the node device.
It is used to perform control to stop the operation. Read the contents of the register file memory 822 above.
When reading the lead selector from the processing device 300,
The access select signal RS is sent, and this is the access select signal RS.
826. This access selector 8
26 is when the node act signal NODEACT is off.
Read select signal RS to selector 82
Add to 3. Data read from memory 822
The data passes through the selector 823 and the buffer gate 827.
The data enters the processing device 300 through the process. After the initial configuration is completed, the node act signal NODEACT is turned on and packet data
Control of transmission and reception begins. First, the channel control unit 200 sends
A circuit that detects when the signal CHNO representing the channel number is zero
Added to 825. This zero detection circuit 825 is
If a channel number of zero is detected, a match check is performed.
The output of the output circuit 824 is prohibited. This has been mentioned before
As shown above, when no packet area is specified at all
The contents of register file memory 822 are
It is “0”, and the channel number of the synchronization area is 0.
The coincidence detection circuit 824 outputs an output at the timing of
This is to prevent this from happening. On the other hand, the output of the zero detection circuit 825 is
Enters the reset terminal of the counter 828, and the counter 8
Reset the contents of 28. In other words, the access
The counter 828 has a period of 0 for the synchronization area X of the frame.
maintain the state of This access counter 828
The contents of are added to access selector 826.
The access selector 826 has a node door in the on state.
Since the act signal NODEACT is applied,
The signal (“0”) input from the dress counter 828
Output as is. This access selector 826
The output of
This becomes a selection signal for the aisle memory 822. follow lever
The 0th word of the register file memory 822 is read.
detected and printed on one input of the match detection circuit 824.
added. Channel number signal on the other input
CHNO is applied. Both input signals match.
Then, the start time is determined by the output of the coincidence detection circuit 824.
The ringing circuit 802 is activated and the subsequent operation is
The operation is the same as that of the link control section 600. The access clock is determined by the output of the timing circuit 802.
The value of counter 828 is counted up and becomes “1”.
becomes. Therefore, this time register file memory 8
The first word of 22 is read and the second packet
Preparations begin to detect the first channel of the exchange area. The above is an explanation of the detection of the first channel.
However, the same is true for the end channel.
The details will be omitted. Frame generation control unit 900 An example of the configuration of the frame generation control unit 900
will be explained with reference to FIG. This frame generation control unit 900 is a loop-like common controller.
One of the node devices connected to the communication path
Node device (this is called frame control node device)
), and the transfer system shown in Figure 7
Transmission/reception section 400A and transfer section 400B of control section 400
connected between. The transmitting clock oscillator 901 is a data transmitter of the present invention.
It serves as the primary oscillator for the transmission clock in communication systems.
Only the frame control node device is
The above transmitting clock is used as the transmitting clock of the transmitting/receiving section.
The output of the clock oscillator 901 is used. Output pulse of the above transmission clock oscillator 901
is first applied to the decimal clock counter 902.
Ru. The present invention uses a decimal clock counter.
In this example, one channel consists of 10 bits.
This is because This clock counter 902
The output of is further applied to clock decoder 903.
Here, the clock used in the frame control node device is
Lock signal CLK₀,CLK₀and the synchronization described later.
Accessing circuit 906 and frame memory 912
A timing signal is generated for the The clock above
signal CLK₀, is in a normal node device
Similarly to the clock signal CLK, for example, one channel
Of the 10 bits of Yanel, 0 bit to 1 bit
and between 5 and 6 bits.
"1" for each, "0" for the other
It's a clock. On the other hand, the receiver 401 of the transfer control unit 400 generates
frame synchronizer based on the timing signal
Clock signal CLK, which is generated by 100
and the signal RR sent from the reception register 403
is synchronized with the receive clock and the transmit clock mentioned above.
It is asynchronous with the output of lock oscillator 901. subordinate
Therefore, in this frame generation control section, the above clock
Captures signals CLK, RR signals, etc. and transmits clock signals.
Lock CLK₀, and phase alignment is performed. For this phase adjustment, first the synchronization circuit 906
, the clock signal from the frame synchronizer 100
CLK, and the signal from the clock decoder 903.
signal is applied, and here the reception clock CLK,
The timing before and after the rise of , and the transmission clock
CLK₀The timing before and after the rise of
A signal is created that occurs at appropriate timing. On the other hand, receive clock CLK and channel
The signal CHACT is applied to the AND gate 930.
The output of this gate 930 is the receive channel counter.
is added to the printer 908. This allows the receiving channel to
Channel counter 908 counts the predetermined number of channels.
When the decoder 907 decodes this, the end
Generate channel signal ENDCH. Count value and reception of reception channel counter 908
The content RR of register 403 is the output of synchronization circuit 906.
Synchronous buffer registers with power timing, respectively
909 and 917. Furthermore, the buffer registers 909 and 917
The contents stored in the transmit clock CLK₀Nota
receive registers 910 and 91, respectively, at the timing.
It is set to 8. The clock decoder 903 is a transmitting clock.
CLK₀From the falling edge of I, CLK₀on until the falling edge of
signal, that is, only 1/2 the time of one channel
Create a signal that turns on, and this is the address select
data 911 and write gate 914.
As a result, the address selector 911 has two inputs.
Select the output of the receive register 910 from among the
In addition to the frame memory address input terminal 912
Ru. At the same time, the light gate 914 opens and the reception register is opened.
The output of the star 918 is the input of the frame memory 912.
Enter the data terminal. Therefore frame memory 912
is the address indicated by the reception channel register 910.
The contents of receive register 918 are written to
It turns out. The frame memory 912 has 10 bits per word.
and the number of words equal to the total number of channels in one frame.
It has the capacity to store information. In other words, 1 frame
It has the capacity to store all the information for frames. The other 1/2 time in one channel, that is, the transmit clock
Lock CLK₀From the falling edge of CLK₀falling of
During this time, there are two address selectors 911.
Select the output of channel counter 904 from among the inputs of
Select the frame memory 912 address input terminal
Add to. The above channel counter 904 is sent
clock CLK₀is being applied, and the transmitting chip is
Counting the number of yarns. Frame memory 9 above
12, the address indicated by the value of the channel counter 909
The address information is read and the transmission clock CKL₀
In the transmission register 913 at the rising edge of
is set. The count value of the channel counter 904 described above is predetermined.
When the value (final channel number) is reached, the decoder 9
The value is reset by the output of 05. On the other hand, the data read to the transmission register 913 is
The information is transmitted along with the output of the synchronization pattern generator 915.
is added to transmit selector 916. Send selection
The channel counter 916 indicates that the channel counter 904 is
(channel 0 to channel 3 in this example)
output from the synchronization pattern generator 915.
When sending out force and indicating other areas
The contents of the transmission register 913 are sent. This send
The output RR of the selector 916 is the output of the transfer control unit 400.
Sent to the transfer unit. That is, receive register 4
The information RR received by 03 undergoes the above operation.
The phase is aligned with the timing of the transmit clock.
After that, it is sent to the transfer unit. The frame generation control unit 900 performs the phase matching described above.
In addition to this function, it also has an abnormality monitoring function. Sunawa
In other words, all the occupancy display bits of all channels indicate occupancy.
If this state continues for a certain period of time,
It is determined that there is an abnormality in the system, and the air block display is displayed.
This is a function that forcibly changes the display to an empty display. This function is applicable to the circuits 919 to 919 of the circuit shown in FIG.
This is realized by 929 components. In the following explanation, the above-mentioned abnormal visual perception function will be
Anomaly detection in the exchange area and packet exchange area
This will be explained separately. Timing of circuit switching area B (see Figure 2B)
The detection is performed in the channel control unit 200,
Line gate signal that is on during the period of circuit switching area B
The number LING is sent. This line gate signal is
AND gate 923 with lock signal CLK
and its output is a delay type flip-flop 91.
It is added to the C terminal of 9. On the other hand, transmission register 9
Busy information for one channel read on 13
The information of the bit, that is, the first bit, is transferred to the above flip.
It is applied to the D terminal of flop 919. As a result
If the busy bit is on, flip-flop 9
19 is set, and its output Q is input to the AND gate 9.
25 and the line gate signal LING is turned off.
Busy counter through gate 925
Enter 921. In this way, all channels in one frame
The first bit of the file remains on for several frames.
, the contents of the busy counter 921 above correspond to that frame.
The count is increased by the number of games. If 1st
Even one channel in the frame is empty.
If there is, flip-flop 919 is turned off,
The output resets the busy counter 921.
will be played. The busy counter 921 has a count value of
When the specified value is exceeded, that is, all channels are busy.
Occurs when the state continues for a predetermined number of frames.
Show power. This output signal is the line gate signal LING
It was added to ANDGATE 927 with
The output of gate 927 is sent through OR gate 929.
Enter the communication selector. This allows all channels to be
The frame is sent only when the specified frame continues.
Among the information sent from the communication selector 916,
Force the busy bit of the exchange area to turn off.
I can do it. Next, we will explain abnormality detection in the packet exchange area.
do. First channel signal STCH of packet exchange area
is an AND gate with clock signal CLK.
924 and its output is a delayed flip-flop
is applied to the C terminal of pin 920. This flippuff
As before, each channel is connected to the D terminal of the loop 920.
The information of the first bit of the channel is added. flip
The flop 920 outputs the terminal of the first channel signal STCH.
If the busy bit is on during timing, it is set.
The output Q becomes "1". Output Q is “1”
If the AND gate 926 is the end channel signal
An output is generated at the timing of TECH, and this
- enters the counter 922. If one frame of chi
Even one channel in the channel is displayed as empty.
If there is, the flip-flop 920 will be reset.
The value of the busy counter 922 is determined by its output.
will also be reset. What is the status of all channels busy?
The frame continues, and the count value of the counter 922 is a predetermined value.
If the value is exceeded, the alarm will be reset at the timing of the first channel.
A busy off signal is issued from the end gate 928,
This enters the transmit selector 916. This will send
Packet exchange signal sent from communication selector 916
The busy bit in the area is forcibly turned off. In the embodiment described above, 8 bits of data +
Data validity display bit + channel empty display bit
When one channel is configured with a total of 10 bits (below)
Abbreviated as lower 10-bit method. ). However, when connecting only the following terminals,
8 bits is sufficient for one channel. (1) Voice (telephone) information 7-bit PCM + channel
Air block display bit (2) 6 bits of data + data valid display bit + channel
Yarnel Air Force Display Bit (3) The packet only contains 1 bit of the first channel.
is used to indicate the blockage of the entire packet, and its channel is
The data part of the file is 7 bits. 2nd channel
After that, all 8 bits can be used as data.
Ru. Configure one channel with 8 bits using methods (1) to (3).
This method will be abbreviated as the 8-bit method below. 10 in Figure 13
1-channel video using bit method and 8-bit method
Indicates the allocation of points. In the figure, B is the chain
A is the data valid indication bit,
v indicates an unused bit. The method described so far in this example is for 8-bit
Even if a method is adopted, it can be applied without any essential changes.
be. The following describes the 10-bit method and 8-bit method in this example.
By switching between the two methods, one type of
Regarding the switching means to be realized with the hardware of
I will explain. Adopt 10-bit method or 8-bit method
The network system shown in Figure 1 determines whether
Determined by what kind of terminal is connected
Ru. Switch or process at system startup
Which method is selected depending on the signal from the device 300
stipulate. The above-mentioned distinction between the 10-bit method and the 8-bit method
To realize the conversion, replace the frame synchronization part in Figure 4 with the following
Change it as follows. Synchronous pattern generator 101, matching circuit 102,
Period counter 106, decoder 107, clock counter
counter 114 and decoder 115 to the existing 10-bit
In addition to the 8-bit version, we have created a new version for the 8-bit version.
Bit/10 bit switching signal (hereinafter referred to as signal OCTET)
Name omitted. ) to switch. Signal OCTET
When starting up the system, the switch or processing
300. Output clock of decoder 115
In the case of the 8-bit system, the lock signal CLK is
1 when the value of clock counter 114 reaches 4.5
This is a signal that becomes . Or, either the 8-bit method or the 10-bit method.
By adopting a circuit system that can be shared, for example,
Synchronous counter 106 and clock counter 114
Turn on and off the signal OCTET with one each
Performs both 8-bit and 10-bit operations.
It is also possible to make it possible to do so. Furthermore, the entire circuit shown in Figure 4 is constructed using an 8-bit system.
It may also be provided separately for use. Figure 14 shows the addition of 8-bit/10-bit switching function.
An example of a transfer control unit is shown below. The operation in the case of the 8-bit system will be explained below. Clock signal CLK from shift register 402
It is captured in the reception register 403 at the timing of
Among the 8-bit data, empty block display bit A02
is set together with empty block indication bit A00 in 10-bit system.
Enter Rector 1400. If signal OCTET is on
If so, bit A02 is output as A00'. wife
In both 8-bit and 10-bit systems, bit
A00′ is the vacancy display bit for that channel.
will appear. Signal given to busy control circuit 407 Set or reset by BUSYON and BUSYOFF.
sky that is set or does not change at all
The error indicator bit A00″ is clocked into the transmit register 412.
After being captured at the timing of the clock signal CLK,
Selector 1401 displays empty status when using 8-bit method.
Enters with bit A02''.Selector 1401 is
No. OCTET is on and 2 channels of packet
If it is not after the channel number, set bit A00″ to A02.
and output it. After the second channel of this packet
As a signal indicating that there is no
The second channel obtained from the timing circuit 701
An inverted version of the signal CHN2 is used.
When the signal OCTET is off, i.e. 10-bit system
and two channels of packets in the 8-bit method.
From the first point onward, use bit A02″ as A02.
Output. When using the 8-bit method, 2 channels of the packet
After Yanel, bit A02″ is used as A02.
The reason for passing the data is 8 from the second channel onward.
This is to secure the amount of bits. In the end, I added two selectors 1400 and 1401.
In addition, by using 8 bits, transfer control is possible.
Processing of busy control, sending and receiving data, etc.
It is the same regardless of the difference between 8 bits and 10 bits.
So it's a good thing. 8-bit signal with empty block indication bit A02
is transmitted through check selector 414.
The clock signal CLK timing is set in register 413.
be taken in by ng. In the case of 8-bit system, 10-bit
10-bit shift register prepared for the
Serial output from the 8th bit terminal in the middle of data 413
Take out. Selector 1402 selects the signal OCTET.
When on, 8 bits of transmit shift register 413
The output of the eye is selected and becomes the output of the selector 1402.
and is sent to transmitter 418 in FIG. signal
When OCTET is off, the 10th bit output is selected.
and is similarly sent to transmitter 418. Figure 15 shows the 8-bit/10-bit switching function.
This shows an example of the configuration of part of the terminal control unit.
8A shows a portion added to FIG. 8A. First, when transmitting data from a terminal device,
When the signal OCTET is on, the eighth
Flipper set by signal SREQ in figure A
The output signal SD01 from the loop 516 is
As the data valid display bit SD03' in the
It functions to output. This selector 1500
Therefore, regardless of whether the terminal device is 8 bits or 10 bits, the device
Output the data valid display signal as signal SREQ.
For example, bits depending on the method being used at the time.
A data valid display signal is output at the position. Next, when the terminal device receives data, the reception
The signal RD selected by the director 520 or
Data valid display when using 8-bit method in IND
Bit RD03 is selected by selector 1501.
It is output as RD01'. This results in
The terminal device side is independent of the 8-bit/10-bit format.
If you detect RD01', you know the validity of the data.
be able to. In the end, using selectors 1500 and 1501
Therefore, the terminal device can use 8 bits/10 bits.
In both cases, the data valid indication signal is sent to the same bit position.
This means that you can input and output numbers. As described above, according to the present invention, the internal bus
and connect the terminal device of the same node device via it.
By exchanging information between
Exchanging information between end devices using only one transmission channel
It can be transmitted using

[Brief explanation of drawings]

Figure 1 is a schematic diagram for explaining the overall system configuration of the system of the present invention, Figures 2A, 2B, and 2C.
Figure, Figure 2D, Figure 2E, Figure 2F, Figure 2G,
Figures 2H and 2J are schematic diagrams for explaining the frame structure in the system of the present invention, Figure 2I is an explanatory diagram for explaining the operation of the system of the present invention during the circuit switching function, and Figures 3A and 3B. is a block diagram showing an embodiment of a node device in the method of the present invention, FIG. 4 is a block diagram showing an embodiment of the frame synchronization section in the method of the present invention, and FIGS. 5A and 5B are channel control diagrams in the method of the present invention. FIG. 6 is a block diagram showing an embodiment of the processing device section in the present invention; FIG. 7 is a block diagram showing an embodiment of the transfer control section in the system of the present invention; Figure 8A, Figure 8B
8C and 8D are block diagrams showing an embodiment of the terminal control unit in the system of the present invention, FIG. 9 is a block diagram showing an embodiment of the link control unit in the scheme of the present invention, and FIG. 11 is a block diagram showing an embodiment of the packet control section in the method of the present invention, FIG. 12 is a block diagram showing an embodiment of the packet control section in the method of the present invention, and FIG. Configuration diagram showing one embodiment, Fig. 13~
Figure 15 shows the 10-bit method/
This shows the case where an 8-bit system switching function is added. Fig. 13 is an explanatory diagram showing an example of channel bit allocation in the 10-bit system and 8-bit system, and Fig. 14 shows an example of the transfer control section. FIG. 15 is a block diagram showing one embodiment of the terminal control section. 100... Frame synchronization unit, 200... Channel control unit, 300... Processing device, 400... Transfer control unit,
500...terminal control unit, 600...link control unit, 7
00...Packet control unit, 800...Packet interface unit, 900...Frame generation control unit, 10
00...Terminal device.

Claims (1)

[Scope of Claims] 1. A plurality of node devices each containing at least one terminal device are coupled through a common loop-shaped transmission path, and a transmission frame consisting of a plurality of channels is circulated at a constant period on the transmission path, In a data communication method in which the terminal devices communicate using at least one channel in a transmission frame, a node device accommodating a plurality of terminal devices is provided with a terminal control unit corresponding to the terminal devices, and these terminal devices are The terminal control units are connected by an internal data bus, data is transferred from the first terminal device to the second terminal device accommodated in the same node device via the internal data bus, and the second terminal Data transfer from the device to the first terminal device is performed via a transmission frame on the transmission path, similar to data transfer to a terminal device accommodated in another node device. Communication method. 2. In the data communication system according to claim 1, the node device includes a transfer control unit connected to the transmission path for exchanging transmitted and received signals, and a data communication system that receives signals via the transfer control unit. A channel control unit for generating a signal indicating a channel number in a transmission frame, and a common bus for coupling these control units and the terminal control unit, wherein the common bus is connected to the channel number. a first bus 1305 for transmitting the number of the receiving channel output from the control unit to each of the terminal control units; and a transmission for transmitting transmission data output from each of the terminal control units to the transfer control unit. Data bus 1302
and a reception data bus 1303 for transmitting received data from the transfer control unit to each terminal control unit.
, the internal data bus 1304 for transmitting and receiving data between the terminal control units, and the mode signal bus 13 for transmitting a signal indicating the transmission data transfer mode from each terminal control unit to the transfer control unit.
01, and each terminal control unit has a first register 502 for storing the data transmission channel number, a second register 503 for storing the data reception channel number, and these first and second registers. Coincidence detection means 510, 511 for respectively checking the relationship between the contents of the registers and the number of the receiving channel inputted from the first bus, and a mode register for storing the transfer mode of transmission data and reception data. 504, and when a match is detected by the match detecting means, the transmit data and receive data are selected as one of the transmit data bus, receive data bus, and internal data bus according to the state of the mode register. control means 512 to 514, 518 to 520 for sending or taking in
and the transfer control unit selects either the received data from the transmit data bus or the receive data from the loop-shaped transmission path, depending on the state of the transfer mode signal of the transmit data appearing on the mode signal bus. A data communication method, characterized in that the data communication method operates to output the data to the loop-shaped transmission path.