JPH0322742B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a data communication system, and particularly to a common transmission method.
A large number of terminal devices are connected to the transmission route, and communication between these terminals is
Regarding the method of transmitting and receiving data on a time-sharing basis
It is something that In recent years, office software aimed at improving clerical productivity has
Automation (hereinafter abbreviated as OA) has been in the spotlight.
It's coming. Traditional OA is mainly individual and fixed
The mainstream is to execute various tasks in batches.
However, in the future, for example, electronic files and electronic
so-called data processing such as tools, document editing, etc.
There is a growing demand for more advanced automation of office work with
There is. On the other hand, based on optical fibers, light emitting diodes, etc.
With the rapid development of optical communication technology, high speed and low
Digital transmission of prices is a familiar network
There is an increasing possibility that it can be applied to Based on this technical background, facsimile
computers, telephones, word processors, personal computers
Common signal transmission between computers, various data terminals, etc.
connect to the Internet and freely communicate data between devices.
A comprehensive network system that enables
Attempts are being made to realize this. However, it is difficult to realize such a network.
In order to do so, we must solve the following problems.
No. Some current terminal equipment uses circuit-switched
One that performs data communication and one that uses the bucket exchange method.
There are devices that perform data communication, and each exchange
The point is that the net exists independently. Therefore, data can be exchanged using these different exchange methods.
Many types of terminals configured to communicate with each other
Connect devices to a common transmission path and communicate between terminals
In order to do this, both exchange methods require data
It is necessary to enable communication. Especially when performing such data communication.
The receiving data channel is
It is necessary to identify whether the
Ru. The object of the present invention is to meet the above requirements.
The purpose is to provide a data communication method. In order to achieve such an objective, the present invention
Connect multiple communication node devices to a common signal transmission path
and at least one of the communication node devices is
A transmission consisting of multiple channels circulating around a signal transmission path.
Generates a transmission frame at one regular cycle and sends it to each communication node.
The connected communication terminal equipment
communicate with each other using at least one channel
In data communication systems that perform
multiple channels of the system are configured with the same size,
These channels are packet-switched and circuit-switched.
It is divided into two types of communication areas:
If the communication area for the above circuit switching is low,
The first channel number is also used to remember the first channel number.
The storage means and the communication area for packet exchange are small.
The second channel number is used to remember the first channel number.
and the channel of the transmission frame being received.
number and the chip stored in the first and second storage means.
Compare the channel number to determine the line switching operation system and packet
a means for selectively activating an exchange operating system;
Set the channel number in the first and second storage means above.
and a means for setting the first value by the setting means.
1. Enter the channel number set in the second storage means.
Through the transmission frame by changing
Change the ratio of packet switching to circuit switching that takes place.
It is characterized by being able to be changed. First, Figure 1 shows the overall system configuration of the method of the present invention.
Refer to and explain. In the figure, 1 is a loop-shaped common transmission line, for example
For example, optical fiber is used. 2 is on this transmission line
A connected node device, detailed later.
Describe. This node device is per loop, e.g.
32 to 64 are connected, at least one of which is
A frame consisting of a synchronization signal area and an information channel area.
It has the function to generate a game. 3 is a terminal device,
For example, facsimile, word processor, personal computer
Null computers, mini computers, telephones,
This includes various data terminal devices. this
There are 8 to 32 terminal devices per node device, for example.
connected. Therefore, in the above example, one loop transmission
256 to 2048 terminals will be connected per route
Become. Of course, the number of these devices is just an example.
However, the method of the present invention is not limited to this.
Needless to say. Next, the frame rate in the time division multiplex communication system of the present invention will be explained.
This section explains the system configuration. In the method of the present invention, the above-mentioned loop-shaped transmission
Bit string information is transmitted on channel 1, but only a certain number of bits are transmitted.
A group of consecutive bits is called a channel here.
The group with a certain number of consecutive channels is called a frame.
It is called mu. This frame maintains a constant transmission rate.
This will occur at a constant repeating period. The frame in the method of the present invention is shown in FIG. 2A.
The synchronization area X and the information communication area Y are structured so that
will be accomplished. For example, 4 channels are the synchronization area X.
The remaining channels will be used as information communication area.
It is used as In this example, one channel is 10 bits.
It consists of The frame repetition period is
In the example, 125μs (8KHz) is selected. Therefore,
If the data speed is 10Mbps, one frame
Number of channels is 125 channels, 400 channels at 32Mbps
Become a le. Each channel in the synchronization area has 10 bits for synchronization.
A bit pattern is inserted. This bit putter
is a business that appears in the information and communication area Y with a small degree of territory.
It is desirable that the pattern be a tuft pattern. Information and communication area Y is used for circuit switching functions and packet
The frame structure will be different depending on when the card exchange function is used.
Figure 2B shows the frame structure when the circuit switching function is used.
Figure C and Figure 2D are frames during packet exchange function.
Configuration, Figure 2E is a frame when both are mixed.
It is the composition. Below are the frame configurations for each.
This will be explained in detail. Frame structure when switching circuits As is clear from Figure 2B, the flexibility when switching circuits is
The system consists of synchronization area X, connection control packet area A, and
and circuit switching area B. The beginning of the frame is the beginning of the frame.
Fixed synchronization characters for identification (one character is 10 bits)
In the synchronization region
Yes, it consists of multiple channels. The next area is
Connection control packet area A and circuit switching area B
However, if they are continuous areas, they are ordered
Either is fine. Also, the above inside the whole frame
Areas other than the three areas may be included. Connection control packet area A is the area where data should be sent.
address of the destination node device and terminal device,
address and data of the node device and terminal device on the receiving side.
Channels in circuit-switched area B used for transmitting and receiving data.
Packets of so-called connection control information such as channel number etc.
used for transmission. This connection control packet area A is illustrated in Figure 2F.
16 Channel A₀~A₁₅It consists of
Each channel is formed from 10 bits, initially
bit A₀₀is the empty block table of connection control packet area A
used for demonstration purposes. i.e. frame repetition
If the cycle is 125μs (8KHz), connection control information
transmits up to 8K pieces/sec of different connection information as
However, this connection control packet area A
If you are using A₀₀Set the bit to “1”,
Set to “0” if not used.
This indicates the empty status of this area.
Note that this connection control packet area A is used for communication between terminals.
When setting the channel for data transfer,
It is only used when canceling the
The period during which data is actually sent and received is
Only circuit channels are used. The second channel of connection control packet area A
Bit A₀₁is preliminarily provided in this embodiment.
Since it is not directly related to the present invention, the explanation will be omitted. A for each channel₀₂~A₀₉The 8 bits are data information.
represents information. Figure 2G shows connection control packet area A.
Each channel A₀~A₁₅and its channels.
An example of the relationship with the information to be sent is shown. Channel A₀is a node device that sends data
A₁
is one of the terminals connected to that node device
Used to specify. A₂sends data
The address of the node device to be trusted is A.₃
is the data destination end connected to that node device.
used to transmit information representing the end address.
It will be done. Channel A_Fouris a request to send data,
Used to transmit a connection control code that indicates the type of request.
I can stay. Channel A_Fiveis used for data communication.
Specific channel number in circuit switching area B used for
It is used for transmitting information representing a number. channel
A₆~A₁₃is used to transmit various parameters
However, since it is not directly related to this invention, the explanation will be omitted.
Ru. Multiple channels at the same time in circuit switching area B
When communicating using channel A,₆
~A₁₃be used to display the channel number.
You can also do it. Channel A₁₄Transmission of check code
used for. For example, channel A₀~A₁₃of
Check the results of performing certain calculations on the data.
The same data is transmitted on the receiving side.
The same calculation process is performed on the transmitted data.
Check whether the data is correct or incorrect. Channel A₁₅stay
Used for transmitting task information. For example, data
When the destination node device receives the data, it
Channel A₁₅sends information with predetermined information
Send it back. This causes the source node device to
Data delivery can be confirmed. On the other hand, in circuit switching area B, the connection control packet is
multiple channels through the channel specified in target area A.
To exchange information between terminal devices for the purpose
used for. This circuit-switched area B has an arbitrary number of channels B.₀，
B₁,B₂…B_nIt consists of It is shown in Figure 2H.
Each channel consists of 10 bits,
Place 8 bit B₀₂~B₀₉is allocated for data transmission.
It is. First bit B₀₀is that channel
Displays whether it is vacant or already used.
Used as a vacancy indicator bit. second
Bit B₀₁is the 8-bit data of that channel.
Whether the data is valid or invalid
Used for display. Whether this information is valid or not
Effect bit B₀₁The data rate can be adjusted by
Yes, the reason is briefly explained below. As mentioned above, in the method of the present invention, the period of one frame is
For example, 125μs (8KHz) is selected, so 1
The amount of data that can be transmitted per second on a channel is 8 bits.
Bit x 8K = 64K bit. In the present invention, this chip
Handles data even at ultra-low speed using units of data
Even on the terminal, if there is a transmission request from the terminal, 1
One channel will be assigned to each terminal. obey
The data speed of the terminal is extremely slow, for example around 50bps.
In this case, even if one channel is allocated, all transmission
The data to be used is approximately once every 64K/50 frames.
It only occurs in That is, 8K times per second.
Even if the frame is repeatedly generated,
I use Yanel about once every 1000 frames.
This means that extremely low-speed data can be transmitted. subordinate
If you use it multiple times in one channel, it will appear in that channel.
Frames with data and frames with no data at all
This means that the frame is repeatedly generated.
Therefore, in the present invention, the assigned channel
B if there is data₀₁Enable bit table
For example, if you set “1” and there is no data
B₀₁Display bits as invalid, e.g. set to “0”
We plan to do so. Therefore B₀₁bit's
The period of “1” represents the data speed
become. In other words, each node device is B₀₁bits
By using it, you can freely use data at different speeds.
It can be adjusted and sent and received. On the other hand, transmitting high-speed data of 64Kbps or more
In some cases, it is easier to assign multiple channels.
can be dealt with. For example, it handles high-speed data of 1Mbps.
It is sufficient to allocate 16 channels to the terminal. Next, we will discuss the data communication procedure using the circuit switching method.
This will be explained with reference to FIG. 2I. The node device sends a transmission request from the terminal to the other party.
Is it the logical address of the device (e.g. phone number)?
Create a destination address. Access for each node device
Dresses are assigned in a fixed manner in advance, etc. by a known method.
Determined by Next, channel B in circuit switching area B₀~B_namong
Air block display bit (B₀₀,B_Ten,B₂₀…) is displayed empty
(e.g. “0”) and select that channel.
is displayed as closed (for example, "1"). Then the 2nd G
The connection control packet format as shown in the figure
Based on this, a connection control packet is created. this place
Channel A_FourA connection request is made to the area corresponding to
The code to display is stored in A_Fivearea equivalent to
contains data representing the hunted channel number.
Stored. Once the connection control packet has been created, it will be displayed as empty.
Find the connection control packet area A that is
packet (this is called the first packet)
do. The empty state of area A above is connected as described above.
First channel A of control packet area A₀empty block table
Indicator A₀₀It can be identified by looking at it. The above connection control packet is received by the receiving node.
The packet information is interpreted, and the connection request is first determined.
Check if the requested device is not in use and try using it.
Used channel number given when not in use
(Channel A_Fivedata) to the terminal of the above node device.
to the control unit. Setting this channel number
will be sent through this channel from now on.
The data will be received by the terminal. the
After that, the channel settings are processed on the receiving node device.
Response packet information indicating completion is created.
This packet (this is called the second packet)
) is sent to the sending node device. The sending node device confirms delivery of the first packet.
and then receive the second packet of response information.
wait. After receiving the second packet, a certain time
and sends a start instruction to the sending terminal. On the other hand, the destination node device displays the response information.
After confirming delivery of the second packet, it is immediately sent to the terminal.
Give a start instruction. Already sent at this point
Same usage for the terminal control section of the receiving side and the receiving side node equipment.
The channel number has been set, and from then on, termination requests will be made.
Information exchange between both terminals takes place at frame period intervals until
exchange through the specified channel in circuit-switched area B.
This is done continuously. at the timing when a certain frame is being generated.
and the data to be sent is still occurring on the device.
If not, the validity indicator bit in the channel (e.g.
For example B₀₁) to “0”, for example,
The frame data is sent to the receiving node device.
is invalid. Effectiveness table like this
Automatic adjustment of data by using indicator bits
As mentioned above, this can be done. When a request to end data transmission is generated from the sending terminal.
Then, in the same way as above, the format shown in Figure 2G is created.
Creates packet information representing a termination request based on the
to be accomplished. This packet information is sent to the receiving node device.
transmitted to. Both node devices are connected to the terminal.
sends a stop instruction signal and stops the channel in use.
to release. In other words, the sending side
Set the first bit to “0”, return it to the empty state, and send it to the receiving side.
cancels the set channel. The control described above is performed by the processing within the node device, which will be described later.
It is executed based on instructions from the management device. Frame configuration during packet exchange The frame at the time of packet exchange is shown in Figure 2C, Figure 2.
As shown in Figure D, synchronization area
It is composed of area D. Synchronization area X is for identifying the beginning of the frame.
This is similar to the case of circuit-switched frames.
Ru. Packet exchange area D stores all information as shown in Figure 2D.
The communication area may be made into one packet switching area.
However, as shown in Figure 2C, multiple packet exchange areas
It can also be divided into areas and used. Each packet area D has multiple areas as shown in Figure 2J.
Channel D₀,D₁...Dl, and each channel
The information to be transmitted is allocated in advance as shown in the figure.
There is. Of course, Figure 2J only shows one example.
First, packet format, address assignment method
The law is possible in other ways as well. In this example, the first two channels D₀,D₁through
The side that sends the packet, that is, the sending address information
is transmitted, and the next two channels D₂,D₃through
The side receiving the packet, that is, the destination address information is
transmitted. and channel D₀,D₂has a node
The device address is channel D₁,D₃is equipped with a terminal
address has been assigned. Channel D_FourSubsequent consecutive channels D_Four~D_l-2
are allocated for data transmission. final chane
channel D before_l-1is channel D₀~D_l-2
Assigned for checking the information on the last
The site DL is allocated for status. Note that each channel has 10 bits as in the case of Figure 2F.
The first channel D₀the top of
Only 1 bit is used to indicate vacancy in the packet exchange area.
The lower 8 bits of each channel are
represents the content. Next, the operation of data communication using the packet switching method
I will explain about it. According to the transmission request from the sending terminal, the sending node
The device waits for free packet space to be received,
The area is marked as a block and the packet information is transferred to the transmission path.
Send to. Each node device uses the destination address in the packet information.
D₂and match with own node address
If not, transfer it as is to another node device.
Ru. Channel D₀destination address is self node
If the address matches, the node device
Start making. The receiving node device is the receiving terminal connected to it.
In addition to transmitting packet information to
The final channel Dl of the notification indicates that it has been received.
Contains status information and displays the next note along with other information.
sequentially transmitted to the card devices. Packet information goes through a loop-shaped transmission path and is sent
When it returns to the node device, this sending node device
The location is channel D₀The originating address of is the own node
Since it matches the address, the packet information that circulated
Incorporate. At the same time, the empty table of the packet area
Indicator D₀₀is displayed as empty and transmission ends.
The transmitting node device receives the captured packets after the round trip.
Communicate by checking the status of information.
You can check the normality of the transmission. As described above, when switching lines and packets using the method of the present invention,
The frame structure during port exchange and each data communication
Although the communication method has been described, in the present invention, both
Data communication can also be performed by switching the exchange method as appropriate.
The circuit-switched area and the
Create both buttocks exchange areas at the same time and use both exchange methods
Data communication can also be performed using a mixture of expressions.
Ru. Figure 2E shows the circuit switching function and packet switching function.
This shows the frame configuration when realizing both at the same time.
This frame's synchronization area X, connection control area A, and
Each bit of line switching area B and packet switching area D
The format is the same as in Figures 2B to 2D.
Therefore, its explanation will be omitted. Furthermore, in Figure 2E
The order of each area A, B, D may be arbitrary, and
The exchange area D may be divided into a plurality of areas. Figure 3A realizes the data communication method according to the present invention.
An example of the overall configuration of a normal node device for
show. 100 is a frame synchronization section, 200 is a channel
300 is a processing device, 400 is a transfer control unit
500 is a terminal control unit, 600 is a link control unit
700 is a packet control unit, 800 is a packet control unit.
Interface section, 1000, terminal device, 110
0 is a packetization device, 1200 is an optical loop transmission
1300 is a terminal bus. In such a configuration, the frame synchronization unit 10
0, it is sent from the loop transmission line 1200
Identify the synchronization area at the beginning of the frame from the received signal
the beginning of the frame and each channel within the frame.
Create a clock timing signal that indicates the beginning of the
Send to the section. The channel control unit 200 controls the channels within the frame.
identify the channel address or circuit-switched area of the frame.
instructions, control node operations, and update status tables.
To make a presentation, etc. The processing device 300 includes a microcomputer, a
A unit that controls the storage program using a harpoon, etc.
Programs such as connection control processing and initial setting processing can be executed in minutes.
Performs ram control. The transfer control unit 400 is connected to the loop transmission line 1200.
A predetermined terminal device 1000
After exchanging the transmitted and received signals with etc.,
A transmission signal to the loop transmission line 1200 is created. The terminal control unit 500 controls the corresponding terminal device 100
0, and transfer control unit 400.
Controls the transfer of data sent and received between. Besides that
In order to record the channel number in the frame to be transmitted.
Do remembrance. The link control unit 600 performs connection control for circuit switching.
control, and performs packet transmission and reception processing. Packet system
The controller 700 has the basic functions necessary for sending and receiving packets.
address matching detection, empty channel search,
Create transmission/reception timing, etc. In the packet interface section 800, the packet
Packetization device 1100 when having a packet exchange area
control signals, control of transmitted and received data, packet area
Memorize areas, etc. A terminal bus 1300 connects these devices 100 to 80.
0 and controls mutual transmission and reception.
look at In such a configuration, the loop transmission line 120
When a received signal comes in from 0, the transfer control unit 40
0, it is received and demodulated, and the frame synchronization section 100
Then, the synchronization signal at the beginning of the frame is detected from the received signal.
of frames and intraframe channels.
Create the clock timing necessary for reception and use other
Send to part. In the channel control section 200, the frame synchronization section 1
Depending on the timing from 00, the channel number signal
and sends it to the terminal bus 1300.
from this channel number signal within the rotational exchange area.
It is determined whether there is a terminal bus 1300.
Send to. In addition, the link control unit 600
From the channel number signal from channel control unit 200
If the receiving channel is at the beginning of the connection control packet area or
The packet control unit determines whether or not the packet has ended.
Send to 700. Now, a transmission request is received from a certain terminal device 1000.
Then, the processing device 300 detects the
Issue a hunt request to 0. In the terminal control unit 500,
Each channel imported from the transfer control unit 400
The occupancy display bit and the channel control unit 200
A signal indicating that the area is within the circuit-switched area.
Locate an empty channel in the circuit-switched area and
is found, the current channel number signal is sent to the terminal.
It is captured and stored in the control unit 500, and also transferred.
Sends a signal to the control unit 400 and selects the corresponding channel.
The loop transmission line 1 is set to the empty block indication bit to indicate the block block.
200. The processing device 300 inputs the destination address to the terminal device.
receiving information from the station 1000 or predetermined
created using a fixed address, and the destination address
address, own address, from the terminal control unit 500
Read the imported empty channel number and create a connection.
Connection control packet format including connection request code, etc.
Create a connection control packet by editing it based on the
It is sent to the link control unit 600. Along with that
A transmission request is sent from the processing device 300 to the link control unit 600.
When a request is issued, the packet control unit 700 performs connection control.
The empty display bit of the first channel in the packet area
If the display is empty, a signal is sent to the transfer control unit 400.
Send and display the empty block display bit of the first channel.
and sends it to the loop transmission line 1200. And that
Both send signals to the link control unit 600 and
The transfer control unit transfers the connection control packet set to
400 and loop transmission as packet transmission information.
Place it on the feed path 1200. In this way, it is sent to the loop transmission line 1200.
The received connection control packet is received by each node device.
It will be done. The operation is performed by the transfer control unit 400
data is sent to the packet control unit 700, where it is
, check whether the destination address matches your own address.
When a match is detected, the link control unit 6
00 and receives the received connection control packet data.
The link control unit 600 takes in the data, and further processes the data.
The device 300 reads it. The processing device 300 receives the read connection control packet.
The terminal that requested the connection is
Check if the device 1000 is not in use, and
If not in use, send the sending node device to the destination address.
Creates a connection control packet that includes a clear response.
and sends it to the link control unit 600 along with the transmission request.
Ru. Hereinafter, similar to the sending node device described above,
Find the empty connection control packet area and create its empty table.
The connection you created will be
Insert control packets into that area and transmit the packets.
It is sent to the sending path 1200. In addition, the processing device 300
Then you will be asked to connect the empty channel number that was sent to you.
settings in the terminal control unit 500 of the terminal device 1000.
Ru. On the other hand, the sending node device sends the
The packet goes around the loop transmission line 1200 and returns.
When the data is received by the transfer control unit 400,
The originating address in the data source matches your own address.
The packet control unit 700 determines that
A connection control packet is sent by sending a signal to the transmission control unit 400.
Set the empty block display bit of the first channel of the area to empty display.
do. On the other hand, the sending node equipment
Connection control packet indicating the response sent from the device
When the packet control unit 700 receives the
Detects that the destination address matches the self address.
and link the connection control packet as described above.
The data is imported into the processing device 300 via the network control unit 600.
nothing. The processing device 300 checks the response information and processes the terminal.
A start command is issued to the terminal device 1000. Ma
In addition, if the information sent by the receiving node device is
I know that I have gone around the loop transmission line 1200 once.
And, as mentioned above, in the connection control packet area
Set the empty block display bit of the first channel to empty,
A start command is issued to the terminal device 1000. In the sending node device, the data from the processing device 300 is
Based on the start command, the data is sent from the terminal device 1000.
The communication data is sent to the terminal control unit 500. In the terminal control unit 500, the set channel number
The number is the channel number from the channel control unit 200.
Detects if a match is found and if a match is detected.
Then, the data sent from the terminal device 1000 is transferred.
The corresponding channel is sent to the control unit 400.
Insert transmission data into the loop transmission line 1200.
Send to. On the other hand, on the receiving side node device, the received
The data is received by the transfer control unit 400, and the terminal control unit
Send to 500. In the terminal control unit 500, the
The channel number received from the channel control unit 200 is
Determine whether it matches the channel number signal and
When a signal is detected, the received data is captured and the terminal device
Send to 1000. In addition, using the same channel
At the same time, from the receiving node device to the sending node device
You can also send data in the same way to
Wear. In addition, from the receiving side node device to the sending side node device
Transmit using different channels for
You can also make it look like this. Next, in the sending node device, the terminal device 1
A transmission end request is issued to the processing device 300 from 000.
Then, the processing device 300 issues a connection control command to instruct disconnection.
Create a packet and send it to the receiver as described above.
Send to node device and stop at that terminal device 1000
Give instructions. At the same time, the processing
Channel resolution from the management device 300 to the terminal control unit 500
issue a release request and check the number of the occupied channel.
When the channel number signals match, the transfer control unit 400
to set the occupancy indication bit for that channel.
Empty it and release the channel. Note that the terminal control unit 500
When the channel number matches the channel number signal, the terminal
No data has been received from device 1000 yet.
In this case, the data with the validity display bit disabled
data and inform the other party that the data is invalid.
What is the processing speed of the terminal device 1000?
It is now possible to respond to Further, in the transfer control unit 400, link control is performed.
The first connection control packet sent from the controller 600
~ Performs the specified calculation on the data of the 14th channel.
to create a check code, and then paste that code into the package.
A machine that can be inserted into the 15th channel of Tsuto and transferred.
functions and numbers 1 to 15 of the received connection control packets.
Performs specified calculations on the data of the eye channel and receives the data.
Check the transmission data for errors and send the results to number 16.
Insert it as status information in the eye channel and forward it.
It has the function to send. On the other hand, when performing packet exchange, the sender node
to the packet interface section 800 of the card device.
and detects the first channel in the packet exchange area.
and sends it to the packet control section 700. Packet control section
At 700, the occupancy display bit from the transfer control unit 400 is displayed.
If an empty channel is displayed, transfer control is performed.
Send a signal to section 400 to block the leading channel.
Set the display bit to black. At the same time, package
packet interface.
Transfers the packet information set in the ace section 800.
Send from the transmission control unit 400 to the loop transmission path 1200
do. On the receiving side node equipment, the first check of the packet is
Check Yanel at packet interface section 1100.
Detected by channel number signal, packet control unit 7
Start 00. The packet control unit 700 transfers
Packet data sent from the transmission control unit 400
Detects that the destination address is its own address.
and sends the result to packet interface section 1.
Inform 100. At the interface section 1100
receives the sent packet data and processes it
Send to 300. Packet interface section 800
Detect the end channel of the packet switching area with
and performs the termination action. Each node device transmits the packet data sent by itself.
The data goes around the loop transmission line 1200 and returns again.
Then, the packet control unit 700 transfers the packet in the same way.
Receives packet data from the control unit and sends the originating address.
Check that the address matches your address.
If they match, a signal is sent to the transfer control unit 400.
Then, the empty block indication bit at the beginning of the corresponding packet
Displays empty and frees up the packet area. Figure 3B realizes the data communication method according to the present invention.
Because it is a node device, it has a frame generation function.
An example of the overall configuration of a node device having
The difference from FIG. 3A is that the transfer control unit 400
It is divided into a transmitter/receiver section 400A and a transfer section 400B.
and the frame generation control section between these
900 is provided. This node device is the normal node device mentioned above.
It also serves as a loop transmission line 1200.
The role is to generate frames with a constant period of rotation.
It is something that The frame generation control unit 900 completes the loop.
The transmitted and received frame information is sent to the transmitting/receiving unit 4 of the transfer control unit 400.
Memory in frame generation control unit 900 via 00A
One frame is stored in the memory, and the clock for transmission is
The pattern of the synchronous region is generated based on the clock.
create the memory first, and then read the above memory sequentially.
Let it protrude and form a frame. Transfer of the information
The data is sent to the transfer unit 400B of the control department. From then on, the same behavior as others
The transfer control unit sends the information to the next node.
It is sent via the receiving section 400A. Also,
The system generation control unit 900 has a function for monitoring abnormalities.
have the ability. i.e. circuit-switched areas and
In each packet exchange area, each channel
All block indication bits on the block indicate block indication.
continues for a certain number of times or more consecutively.
Forces the empty block display bit of each channel to be empty.
It serves the purpose of showing. Other operations are the same as in Figure 3A.
The explanation will be omitted. Below are specific configuration examples of each part in Figures 3A and B.
This will be explained in detail. (1) Frame synchronization unit 100 FIG. 4 shows the specific configuration of the frame synchronization section 100.
This shows one example. In the figure, the signals TIM and SROUT are detailed in Figure 1.
produced by the receiver and shift register as described above.
This is the signal that is generated. Loop transmission line 1200?
Serial reception information sent to the transfer control unit 400 from
The received information is demodulated by the receiver, and the received information is
By extracting the timing of bit intervals,
Utility 50% timing signal TIM is created
Ru. This timing signal TIM allows serial reception.
Store information sequentially in shift registers. that schiff
The parallel output of the register is the signal SROUT. The frame synchronization unit 100 generates a synchronization pattern.
It is set in the device 101. Inside the frame synchronization area
synchronization pattern and transfer control unit 400 shift register
The information SR and OUT stored in the star are connected to a matching circuit.
At 102, each bit is compared and one bit is received.
When a match is detected, the match flip-flop 103 is activated.
Set through AND gate 104. By setting this flip-flop 103,
Synchronous counter 106 through AND gate 105
to start counting the number of received bits.
Ru. The value of the synchronization counter 106 is
The data corresponds to the number of bits (10 in this example).
When detected by the coder 107, the AND gate 108
The contents of the shift register of the transfer control unit 400 are
Does SROUT match the sync pattern again?
If there is a discrepancy, undo the
OR gate 109 is activated by the output of gate 108.
Coincident flip-flop 103 and synchronous capacitor
I reset the counter 106 and the 1-bit error occurs again.
The contents of the shift register and
Search for sync pattern matches. Shift register contents and synchronization pattern continue
If there is a match, the matching flip-flop 103
remains set, and at that time, the synchronization counter
106 outputs a signal to the synchronous character counter 110.
Then, the synchronous character counter 110 is incremented by 1. This way
In other words, channels that match the synchronization pattern are consecutive.
When the synchronous character counter 110 receives the
The number of characters is counted. As mentioned above, the synchronization area
If the number of channels is 4, the counter 110
becomes 3, and the contents of the synchronization counter 106
The value after detecting the next 4th channel sync character
For example, when it becomes 3, that is, 4 channels in a row
The decoders 111 and 107 confirm that a match has been obtained.
and the timing signal TIM.
produces an output in the AND gate 112 when
and set the synchronizing flip-flop 113.
indicates that synchronization has been achieved, and the set output
By force, match flippuff through or gate 109
Loop 103, synchronous counter 106, synchronous character counter
In addition to resetting all counters 110,
The output of the gate 104 is prohibited. Thereby,
The match detection operation is stopped and subsequent information channels are
To prevent content from being mistakenly considered a synchronous channel.
Ru. On the other hand, the clock counter 114
The shift lever is driven by the shifting signal TIM.
Register output SROUT shows information for one channel
to create a clock that dictates timing.
It is something. For that purpose, we use ANDGATE 112 to
When period OK is detected, the clock counter 114
, the value of the synchronization counter 106, i.e.
3, and the value of the synchronization counter 106 and the clock
By making the values of the counters 114 the same,
Make combinations. On the other hand, the clock counter 114
The output of
When the value of the decoder 114 is 0 or 1, the decoder 115
outputs the clock signal CLKI from the
When the value of the counter 115 is 5 or 6, the clock signal is
Outputs the number CLK. Also, for special purposes
When the value of the clock counter 115 is 4, the clock
Outputs signal CLK. This CLK allows the shift register to be activated as described later.
The output of the star is transferred to the receive register and
Subsequent processing is possible in units of information for each channel. one
On the other hand, even when this CLK~ is not synchronized,
Since the clock counter 114 is always operating,
It is output all the time and interrupts the processing of other parts of the node device.
It won't cut it off. The synchronizing flip-flop 113 is set.
Then, from the frame synchronization unit 100 to the channel control unit
Send channel act signal CH ACT to 200,
Activates the channel counter in the channel control unit 200.
counting at the timing of the clock signal CLK.
and the number of clock signals CLK, i.e.
Number of channels in the frame (channels in the sync region
Excluding numbers. ) is counted. Inside the channel counter
The content is the information communication area within the frame (Fig. 2A Y)
When a number corresponding to the number of channels is reached, the decoder
Frame synchronizes the end channel signal END CH from
Send it back to the period section 100 and pass it through the AND gate 116.
to reset the synchronization flip-flop 113.
do. As a result, the synchronization detection operation as described above
is started and transferred to the shift register of the transfer control unit 400.
Whether it is a synchronous character pattern or not each time one bit is received.
Perform that check again. Then the next frame
The synchronized region of the frame continues after the end of the previous frame.
A check is made to see if it is received correctly. Bit extraction of transmission information of loop transmission line 1200
However, due to bits gushing out due to noise, the next frame is
If no synchronization pattern is detected in the synchronization area of the
There may be cases. In this case, the channel in the frame
The channel information is not recognized correctly, so please synchronize immediately.
While restarting the process, the process may be canceled in the meantime.
Some action is required and this same
Delays must be detected immediately. This out-of-sync detection detects the end of the previous frame.
Synchronization is performed using the end channel signal ENDCH, which indicates
After flip-flop 113 is reset, the
The timing when the value of the lock counter 114 becomes 0
i.e. at the beginning of the synchronization area of the next frame.
All synchronization channel information is stored in the transfer control unit 400's system.
The synchronization pattern is input at the timing input to the shift register.
No match with turn is detected, i.e. match flip
If flop 103 has been reset, the AND
An output is generated from gate 117 and the out-of-sync flip
Set flop 118. Out-of-sync flip
Out-of-sync signal which is the set output of flop 118
ST OUT is sent to the channel control unit 200.
This flip-flop 118 was able to synchronize.
It is reset by the output of flip-flop 113 when
It will be done. (2) Channel control section 200 FIG. 5A shows a specific configuration of the channel control section 200.
This is an example. As mentioned above, the frame synchronization unit 100
When synchronization is established, channel act signal CH ACT is sent.
is output, the channel control unit 200 outputs the same
Clock signal from frame synchronization unit 100
Open AND gate 201 at CLK timing.
Then, the channel counter 202 starts counting.
If the contents of the channel counter 202 are in the frame,
When the value corresponds to the number of channels in the information and communication field,
End channel signal END from decoder 203
Output CH. Chi from frame synchronization unit 100
When the Yanel act signal CH ACT is turned off, the input
Channel counter through converter gate 204
202. The output of the channel counter 202 will be described later.
uni, node act flip flop 205
is set, through AND gate 206.
and channel number signal CHNO as terminal bus 1
300. On the other hand, the interface circuit 207
Write data to the register selected from 300
A circuit for reading data.
Its specific configuration is, for example, as shown in Figure 5B.
It is. In the interface circuit 207 shown in FIG. 5B,
is transmitted from the processing device 300 through the terminal bus 1300.
, synchronization signal SYNC, terminal number TMNO, register
data number REGNO, read/write control signal R/
W, data D are input, and the matching circuit 208
, when the synchronization signal SYNC is input, the terminal
The terminal number TMNO is automatically generated from the terminal number generator 209.
Compare it with the terminal number assigned to you and confirm that both parties are on the same page.
According to the read/write control signal R/W when
to generate output from AND gate 210 or 211.
Write decoder 212 or read decoder 212
The coder 213 is selected and the processing device 300
The register corresponding to the register number REGNO is loaded.
Write select signal WS or read selector signal
Output RS. At the same time, the transmitting gate 214 also
also selects the receiving gate 215 and receives the data from the processing device.
The data D is set to the record selected by the write select signal WS.
write to register or select register
The contents of the file are read out and sent to the processing device. In addition,
The register specified by register number REGNO is
, but also has memory functions such as flip-flops.
It may be something you have. In Figure 5A, the line head channel register
216, line end channel register 217, synchronization
Off state flip-flop 218 and node
act flip-flop 205 from the processing unit.
It is selected by the register number REGNO of
Ru. Line start channel register 216 and line end
The completion channel register 217 contains input from the processing device.
Light sent through interface circuit 207
The frame is set in advance by the select signal WS or WS.
The first and last channel numbers in the circuit-switched area of the system.
The final channel number is stored in advance. Also,
The lip-flop 205 operates the node device.
The timing of the write select signal WS when
Then, it is set with data D.
Then, the contents of the channel counter 202 are
Match the head channel register 216
When detected by circuit 219, circuit switched area flip
Set flop 220. Also, Chanelka
The contents of counter 202 are the line end channel register.
The matching circuit 221 detects that the data matches the data 217.
When the signal is detected, the delay circuit 222 outputs the detection signal for a certain period of time.
Reset flip-flop 220 after delay
do. Flip-flop 220 is set
When node act flip-flop 205 is set
If it is in the ON state, open the AND gate 223.
Generates line gate signal LING and terminal bus 13
Send to 00. In the processing device 300, the out-of-synchronization state
In order to know the state of the pop-flop 218,
Read select signal through phase circuit 207
Send RS, open buffer gate 224, and
In addition to importing the contents of the lip-flop 218,
A signal delayed for a certain period of time by the delay circuit 225 causes a fuse.
Reset the lip flop 218. In addition, the lead from the interface circuit 207
Select signal RS selects register 216 or
The content of 217 is buffer gate 226 or 22
7 to be read out. (3) Processing device 300 FIG. 6 shows an example of a specific configuration of the processing device 300.
It shows. The processing device 300 includes a processing section 300A and a conversion section 3.
00B, and the processing section 300A has at least
Also processor 301, memory 302 and bus 3
It is more familiar than 03. Then, the processor 301 and the memory 302
The address strobe is connected to the bus 303 connected to
Signal ASYNC, address signal ADRS, read label
It has a light control signal R/W and data D.
and those signals are input to the converter 300B.
Ru. In the conversion unit 300B, the data from the processing unit 300A is
The high-order bit of the address signal ADRS is matched by the matching circuit 30.
4 and set the address strobe signal ASYNC.
The upper bits of the address at the timing
It is set to the generator 305. interface times
whether the address pattern indicates access to the
Check and if they match, synchronization signal SYNC
Create. Also, the lower bits of address ADRS
is the terminal number TMNO and register number REGNO
It is sent as is. In addition, the read/write control signal R/W is synchronized.
AND gate 306 is activated at the timing of signal SYNC.
and gate 306.
and 307, buffer gate 308 or
309 to send or receive data D.
cormorant. The various signals created in this way are described above.
Interface circuit of the channel control unit 200
Not only the terminal control unit 500, the link control unit
600 and packet interface section 800.
It is also sent to the interface circuit. (4) Transfer control unit 400 FIG. 7 is an example of a specific configuration of the transfer control unit 400.
This shows the transmitting/receiving section 400A and the transfer section 400.
It consists of B. In the transmitter/receiver 400A, the loop transmission line 12
The receiver 401 receives information from 00, and the information is
While demodulating the bits of the received information,
Extract the timing signal TIM and use this timing
Shift register information at the timing of signal TIM
402 sequentially. Next, the clock from the frame synchronization section 100 described above is
At the rising edge of lock signal CLKI, shift register 4
The 10-bit output of 02 is arranged in the receiving register 403.
Set to column. On the other hand, in the transfer unit 400B, the reception register 40
The valid display bit and empty display bit of the output of 3.
The 2 bits of the
At the same time, the vacancy display bit is sent to Not Gate 4.
Terminal bus as occupancy indication signal IDLE through 05
1300. Output of reception register 403
Address verification is performed using the remaining 8 bits of data information.
Packet controller 70 as signal ADDR for
0 in the status selector 406.
Send to one input. Also, status selector 4
The other input of 06 is the packet control unit 700 or
status signal STATB and the error described below.
A status signal indicating the presence or absence of
Ru. In this status selector 406, the packet
Status selection from the gate control unit 700
Select sending data according to STATSEL. vinegar
That is, when there is no signal, the reception register 403
selects the output of the other input when the corresponding signal is present.
Select the status signal STAB etc. On the other hand, the status select STATSEL signal is an example
For example, while receiving the connection control packet area, the 16th channel
When you need to send the status back to the network, etc.
sent, status signal STATB and zero detector
417 output is selected. Status selector 4
The selection output of 06 is sent to the receiving register 404.
Ru. In the reception register 404, the frame synchronization unit 1
Set input data with clock CLK from 00.
to Empty table in the output of the receive register 404
The indication bit is input to the busy control circuit 407, and other
The remaining 9 bits are sent to the terminal bus as received data RD.
1300 and mode selector 4.
08. In addition, the reception register 40
The 8-bit data information of 4 is output to FIFO memory 4.
09 is input to register 1. FIFO
The memory 409 records the output of the reception register 404.
CLKI timing on registers 409-1 and 409-2
In addition, 409-3 has the timing of CLK.
Store sequentially using Therefore, the output from the FIFO memory 409 is
The received data is delayed by two channels,
Link control unit as packet reception data PAKD
Sent to 600. Here, FIFO memory 409
I used the destination address in the connection control packet.
is the third channel, and its destination address is
Determine that it is the own address and send the received data.
This is because it is necessary to incorporate it. The other input of mode selector 408 has a terminal
Transmission data SD from bus 1300 is input
In this selector 408, the packet control unit
The mode selector signal MODSEL from 700 is turned on.
When the mode is selected, select the transmission data SD and select the mode.
When the receive register signal MODSEL turns off, the receive register
Select the output from the star 404. The busy control circuit 407
Busy on signal BUSYON from 0 is on
Sometimes the air block indication bit in the received information is changed to block indication.
The busy off signal BUSYOFF is turned on.
Forces the vacancy display bit to display empty when the
It is set to . At other times, the busy control
A path 407 receives the signal from the receive register 404.
It has a function to output as is. Next, busy control circuit 407 and mode select
The output of the vector 408 is clocked by the timing of CLKI.
is set in the transmission register 412. sending regis
Among the outputs of the controller 412, the occupancy display bit and the valid display
The two bits are directly transmitted by the transmitter 400A.
The signal is input to the communication register 413. Meanwhile, the remaining 8
Bit data information is available from the check selector 414.
and is input to the arithmetic unit 415. The check register 416 is connected to the packet control unit 70.
Initialized to 0 by reset signal BCC RST from 0
After setting, check from packet control unit 700
In response to the operation start signal BCC ACT, the arithmetic unit 41
5 to operate the output of the check register 416.
and the output of the transmission register 412,
Check the result at the clock CLK timing.
set in the check register 416. This operation is specific
This is a division by a constant, and can be used as a transmission information check.
This is a commonly used method. These actions are
For example, channels 1 to 14 in the connection control packet area.
Repeated while transmitting data information. 15 chiane
Check select from packet control unit 700
The set signal BCCSEL is sent to selector 414, and
In the rector 414, at that timing, the arithmetic unit 4
Select output 15 and send to transmit register 413
do. The zero detector 417 indicates that all bits of the arithmetic unit 415 are
Has a function to detect a predetermined value, for example 0.
The output is used as the status signal STATB.
Both are input to the status selector 406.
Ru. In short, the zero detector 417
Each bit of data information for channels 1 to 15 in the
Whether all the results of the calculation are zero, for example.
Detect if there are errors in data information with
The results are divided into 16 channels in the packet area.
It has started to be put on the eye status channel.
Ru. In the transmission register 413 of the transmission/reception section 400A,
The clock CLK from the frame synchronizer 100
Transmit register 412 and check at timing
Set the output of selector 414, and then
Shift the data bit by bit using the timing signal TIM.
loop transmission line 1200 via transmitter 418
Send to. Furthermore, as described above, the frame synchronization unit 100
In this case, even if frame synchronization is not established, the
Since the timing is generated, the received information
It has become possible to carry out light transport at all times. (5) Terminal control unit 500 8A and 8B show the terminal control unit 500.
Figure 8A shows an example of a specific configuration.
Basic part, Figure 8B shows the empty channel selection part.
Ru. In the basic part of Figure 8A, the interface
The circuit 501 is composed of a circuit similar to that shown in FIG.
It sends and receives data to and from the management device 300. Transmission channel, register 502 indicates the times to be transmitted.
This stores the channel number within the line switching area.
The reception channel register 503 stores the information to be received.
It stores the channel number in the circuit switching area.
be. Also, the contents of the mode register 504 are 4 bits.
of which 2 bits 504-
1,504-2 indicates the bus connection method during transmission.
ing. 504-1 is the transmission within the terminal bus 1300
Send data to loop transmission line 1200 via bus
504-2 is the same node equipment.
internally within the terminal bus 130 to other terminal control units within the equipment.
Indicates when to send data over the bus.
Ru. In addition, the remaining 2 bits of the mode register 504
504-3 and 504-4 are bus connection methods when receiving
bit 504-3 indicates the loop transmission line.
1200 through the receiving bus of the terminal bus 1300.
bit 504-
4 is a terminal switch from another terminal control unit in the same node device.
Receives data via the internal bus within the bus 1300.
This shows the case where These transmit channel registers 502, receive channels
channel register 503 and mode register 504
The write set from the interface circuit 501 is
Data D can be set by the rect signal WS.
Also, these registers 50
Read select output of 2,503 and 504
Buffer gate 505, respectively, by signal RS.
Interface circuit through 506 and 507
501. Also, transmit and receive channel registers 502
and 503, as detailed in FIG. 8B.
Uni, the clock CLKI after a hunt request is made.
Channel number with timing HTCLK-S and R
Go to update and register the number CHNO, within the circuit switching area
When an empty channel occurs, change that channel number to the highest
It is finally possible to register. mode
504-, which is a transmission instruction in the register 504;
1,504-2 must be set.
Only when there is an output of OR gate 524 that detects
The output of the transmit channel register 502 is
output 508 to matching circuit 510. same
Similarly, the transmission mode register is set by the OR gate 525.
Any of 504-3 and 504-4 out of 504
is set, and the channel register is set.
The output of the star 503 is unified by the AND gate 509.
It is output to the match circuit 511. Note that registers 502 and 503 have an interface.
from the processing device 300 via the ace circuit 501
Setting the data is, for example, when connecting from the other party.
Receive control packets and include transmit/receive channel numbers.
This is the case when a number is specified. Data is set in registers 502 to 504.
transmission channel register 502 and reception channel register 502.
The contents of the channel register 503 and the channel number
The matching circuits 510 and 51 match the number CHNO.
1 to detect. Channel number signal and transmit channel register 50
2 is detected by the matching circuit 510, the motor
The contents of bit 504-1 of the code register 504 are
If it is 1, open the AND gate 512 and
When the mode signal MODE is sent to the terminal bus 1300,
Both, Batsufuage via AND gate 513
Open the port 514 and read the contents of the sending buffer 515.
Send to terminal bus 1300. On the other hand, terminal device 1
At 000, the transmission data is complete and a transmission request signal is sent.
By turning on SREQ, the transmit buffer 5
When setting the 8-bit transmission data SD to 15,
Both set the transmission request flip-flop 516.
and the output signal of said 516 is used as a valid display bit.
So, when buffer gate 514 is opened, the data
Send data SD to terminal bus 1300 with information
It is sent to the transfer control unit 400 as a. Transfer control unit
400, as mentioned above, the mode signal MODE
The mode is selected by the corresponding mode select signal MODSEL.
Operate the code selector to transfer the transmitted data SD to another
Send to node device. The coincidence output of the coincidence circuit 510 is outputted by the delay circuit 517.
OK signal to send delayed signal to terminal device 1000
While sending as SOK, send request flip-flop
Reset loop 516. Therefore, the terminal device
Before the transmission data from 1000 is completed, the channel
When a channel number match is detected, before sending the data
The transmit request flip-flop 516 is reset to
Therefore, the valid display bit of the transmitted data SD
becomes 0, indicating that the transmitted data is invalid.
it's shown. In short, the processing on the terminal device 1000 side
If the processing speed is slow and the transmitted data is not collected,
By displaying invalidity, the terminal device 1000 side
There will be no limit to the processing speed. Next, when a match is detected in match circuit 510, the motor
Bit 504-2 of code register 504 is 1.
If so, the AND gate 518 causes a buffer gate.
519 to send the above-mentioned transmission data to the internal bus.
Send it to the internal bus as data IND. On the other hand, the output of the receiving channel register 503 is
If the channel number from the last bus matches the match times
When detected in the mode register 504
According to the contents of bits 504-3 and 504-4 of
Perform the following actions. That is, the reception selector 520 has a reception bus
Receive data RD from RD and internal bus receive data
This selector 520
Then, bit 504-3 of mode register 504
When is 1, select receive data RD and set bit 5.
When 04-4 is 1, select internal bus data IND.
People are starting to choose. selected in this way
Of the received data, the data information is received through the buffer 52.
1, and input the valid display bit to AND gate 52.
2. Valid display signal of valid display bit
and the coincidence output of the coincidence circuit 511, the AND
The output of the gate 522 is turned on, and the reception selector 5
When the output of 20 is set to the receiving buffer 521,
In both cases, the receive request flip-flop 523 is set.
to The set output of this flip-flop 523
The terminal device 1000 receives the power as a reception request signal RREQ.
At the same time, the contents of the receiving buffer 521 are sent to
is sent to the terminal device 1000 as received data RD.
do. The terminal device 1000 receives the reception request signal RREQ.
When received, it sends back the reception OK signal ROK and indicates the reception request.
The request flip-flop 523 is reset. In this way, the valid table is
Only when the indicator bit is valid is the received data
data is being imported into the terminal device 1000.
data, so the sending terminal device can process it as complete data.
It will be received only when it is sent, and the terminal equipment
Send and receive data regardless of the speed of the receiving device.
can become. Next, according to Figure 8B, the empty channel selection function is activated.
explain about. In addition, FIG. 8B shows the transmission or
Related to the empty channel selection function when receiving one
Although only the circuit that transmits
and two circuits shown in Figure 8B are provided for reception.
It will be done. In such a configuration, from the processing device 300
Hunt request via interface circuit 501
is sent, the clock CLKI timing
Open the AND gate 531 and request a hunt.
Set flop 532. Hunt request pretend
When pop-flop 532 is set, circuit switching
Line gate signal LING indicating reception of area and reception
Indicates that the data channel is an empty channel
Empty indication signal IDLE and hunt request flip-flop
532 output to the AND gate 533,
When the above hunt conditions are met, AND gate
The output signal from 533 is sent to the delay circuit 534 for a predetermined time.
After delay, get empty channel flip-flop 5
35 and hunt request fritz.
Reset flop 532. On the other hand, Hunt
Request flip-flop 532 is set
In the meantime, AND gate 536 is activated by clock CLKI.
Open to get the signal HTCLK and pass this signal as shown in Figure 8A.
Input to channel register 502 or 503
At that timing, the channel number signal
CHNO one after another in channel register 502 or 5
03 and update it. As mentioned above, empty
Channel detected, hunt request flip-flops
When the pin 532 is reset, the register is loaded.
will eventually stop working, resulting in an empty channel.
The channel number corresponding to is stored in the register.
There will be. The output signal of the delay circuit 534 is sent to the OR gate 537.
is input to the delay circuit 538 through the
packet control as a busy signal BUSY with a delay
Busy on signal BUSYON is sent to control section 700.
Convert to As a result, the transfer control unit 400 transfers
Sets the blockage display bit of the corresponding channel during transmission to blockage display.
and prohibits hunting on other terminal devices. onwards,
Even after the hunt is established, the matching circuit 510 in FIG.
AND 511 coincidence output COIN-S or R
through gate 539 and or gate 537.
input to the delay circuit 538 and output at a predetermined time by the delay circuit 538.
After a delay, the same busy signal BUSY
Send and set the occupancy indication bit to occupancy. In addition,
Delay circuit 538 is used to maintain proper timing.
It is set in. Flip-flop 535 is set and hunt
After the set output is established, the AND
Close gate 531 and prohibit future hunt requests
This prevents double channel hunting. On the other hand, when data transmission or reception is completed and
When releasing the channel, the processing device 300
The interface circuit 501
Sends the write select signal WS from the clock
Open AND gate 540 at the timing of CLKI
to set the release request flip-flop 541.
Ru. and channel register 502 in FIG. 8A.
or the contents of 503 and channel number signal CHNO
The match circuit 510 waits for a match to be detected.
Or if a match is detected in 511, the signal COIN-S is
Or when COIN-S is output, the AND gate
The output from 542 is a delay circuit for timing adjustment.
After a predetermined time delay with 543, the empty display OK signal is displayed.
IDLEOK is sent to the packet control unit 700 and the bit
G-off signal BUSYOFF to transfer control unit 400
Force the empty display bit of the channel that was sent and occupied
Display empty. At the same time, the release request flip-flop 54
1 and empty channel acquisition flip-flop 535
and complete the release operation. Note that multiple terminal control units in the same node device
process so that they do not enter the hunt request state at the same time.
Under program control within the control equipment, only one unit is always operating.
the empty channel.
This prevents multiple terminal control units from hunting. In the embodiment described above, one channel per terminal device.
When transmitting or receiving by exclusively occupying
As explained above, multiple channels per terminal device
You may also assign it. Figure 8C shows this
Configuration of an example of the main part of the basic part of the terminal control part in case
This shows that. In the figure, channel registers 551, 552
is used for both sending and receiving, and these
Contents set in register and channel number signal
Matching with CHNO is detected by matching circuits 555 and 556.
and when a match is detected in any matching circuit,
It is output from the OR gate 557. On the other hand, speed adjustment of the terminal interface for sending and receiving
FIFO for transmit and receive respectively
Memories 558 and 559 are provided. This FIFO memory 558 is
Timing of transmission request signal SREQ sent from
The data is valid, along with the sent data SD.
A valid display bit is stored to indicate that the Once a match is found as described above, the detection
The signal is delayed for a predetermined time by the delay circuit 560, and then
Stored in FIFO memory 558 at the timing of the delayed signal.
Read the stored transmission data. At this time, the data
When transmitting
Depending on the contents of 504-1 and 504-2
The same operation as described in FIG. 8A is performed. On the other hand, if you also want to receive data, use the mode register.
Bits 504-3 and 504-4 of star 504
Depending on the content of the received
Select data RD or internal bus data IND
520 and the selected data is valid.
Sometimes, the data is sequentially stored in the FIFO memory 559.
Store and read the contents at a predetermined timing
Send as received data RD to terminal device 1000
Ru. Also, corresponding to the channel register 551, an eighth
A circuit with an empty channel selection function as shown in Figure B
In that case, and
536 output signals HTCLK-1 to HTCLK-n
is applied to channel registers 551-552, and
Channel number OHNO one after another at the timing of
Import and update the channel registers 551 to 552.
Ru. Also, the output of each bit of the mode register 504
The logical sum of the forces is taken by the OR gate 563, and the mode
If any bit in register 504 is set to 1.
Channel registers 551 to 55 only when
The output of 2 is passed through AND gates 553-554.
It is output to matching circuits 553-554. Also, one
Coincidence output COIN-1 of matching circuits 555 to 556
COIN-n to AND gate 539 and
542. Also, the logic of the output of each delay circuit 538
The output obtained by taking the sum with the OR gate is the busy signal.
BUSY and sends each delay.
Similarly, the logical sum of the outputs of the extension circuit 543 is taken and
Send the output as the empty display OK signal IDLEOK
It's becoming like that. In addition, the lead from the interface circuit 501
Buffer gate 561 is activated by select signal RS.
and 562 to open the channel register 551
It is also possible to import the contents of ~552 into the processing device.
Ru. In the embodiment described above, the mode register 50
4 and an internal bus, the same node
between any two within multiple terminal controls within a host device
Communication is now possible, but this can be seen in Figure 8D.
This will be explained in more detail below. The figure shows a transfer control unit 400 and a plurality of terminal control units 5.
This shows the connection relationship with 00A and 500B.
The terminal bus 1300 is the bus necessary for connection between them.
i.e. bus 13 for mode signal MOOE.
01, transmission bus 1302 for transmission data SD, reception
Reception bus 1303 for communication data RD, internal bus de- vice
Internal bus 1304 and channel for data IND
It has a bus 1305 for the number signal CHNO. Terminal control unit 500A in the same node device and
When communicating between 500B and 500B, the terminal control unit 5
Transmit channel registers in 00A and 500B
502 and receive channel register 503, respectively.
Set the same channel number. Below is an example of how to set the channel number.
I will explain. One terminal control unit on the sending side, for example
For example, at 500A, search for an empty channel and
If a channel is found, send the channel number.
channel register 502. Processing device 300
Now, the channel number set in this register 502
load the same channel number, and connect the same channel number to the same end.
Reception channel register 50 in end control unit 500A
3, and other terminal control unit 500
Transmit and receive channel registers 502 and
and 503 as well. In addition, the processing device 30
0, the mode register in the terminal control unit 500A
At 504, the receiving side connects the receiving bus 1303,
The receiving side instructs connection to internal bus 1304.
In this case, set bits 504-2 and 504-3 to 1.
At the same time, the mode register in the terminal control unit 500B
In star 504, the receiving side is connected to internal bus 130.
4. The sending side instructs connection to the sending bus 1302.
Set bits 504-1 and 504-4 to 1 so that
Keep it. As a result, the terminal control unit 500B
The transmission information from the transmitter 590B is indicated by the thick line in FIG. 8D.
Transfer via transmission bus 1302 as shown in
Similarly, a mode signal is sent to the control unit 400.
The data is sent to the transfer control unit 400 via the bus 1301.
Ru. The transfer control unit 400 controls the mode of the bus 1301.
Transmission information is set by turning on the code signal.
loop transmission line 120 on the channel numbered
Send to 0. In this way, the loop transmission line 12
The transfer control unit 400 takes in the information that circulated around 00.
and the terminal control unit 500 via the reception bus 1303.
A's receiving unit 591A. On the other hand, from the terminal control unit 500A to the terminal control unit 50
When sending information to 0B, the thick line in Figure 8D
The transmission unit 590A of the terminal control unit 500A
The transmission information is sent to the internal bus 1304 from
The data on the internal bus 1304 of the terminal control unit 500
The receiving unit 591B of B receives the received information. Also, the dotted line in the figure is the signal for the opposite case as described above.
The route is shown. Link control unit 600 The link control unit 600 performs
The packet data of connection control packet area A (hereinafter
Transmission and reception processing of (abbreviated as "downlink packet data")
It is something to do. The structure of this link control section 600
The configuration and operation are based on data during packet switching function.
The configuration and operation of the equipment that sends and receives data, and the terminal interface.
- Almost the same except for the face. FIG. 9 shows the configuration of the link control section 600.
This is an example. In the same figure, 602 and 603 are registers.
interface from the processing device 300 described above.
The connection control packet area A (hereinafter referred to as
The first channel of the link packet area (abbreviated as link packet area)
number and end channel number are respectively initialized.
It will be done. Therefore, for example, a frame structure as shown in FIG.
In the case of configuration, the link head channel register 602 is
is channel number 5, link end channel register
The value of channel number 20 is set in the register 603.
That will happen. Channel each register 602, 603
To set the data representing the channel number,
Specify a pre-assigned address for each register.
The light select signal WS to be set and the channel to be set.
Apply data D representing the channel number to the register.
This is achieved by Also, each register 60
Read select specifying 2,603 addresses
When the signal RS is applied, it is stored in each register.
The data representing the channel number
Read through buffer gates 608 and 609
It will be done. The outputs of both registers 602 and 603 are channel
Sent from the control unit 200 through the terminal bus
Match each with channel number information CHNO
It is added to detection circuits 604 and 605. Match detection
Circuit 604 stores the contents of register 602 and the channel.
Output signal when number information CHNO matches
This causes the start timing circuit 606 to start.
be moved. This timing circuit 606
Timing synchronized with clock CLKI in Yanel
Outputs the signal STCH to the On the other hand, the match detection times
The channel 605 stores the contents of the register 605 and the channel.
Output signal when number information CHNO matches
This causes the end timing circuit 607 to start.
be moved. This timing circuit 607
synchronized with the clock signal CLK in the clock
Outputs the signal TECH at the timing. By activating the top timing circuit 606,
After the first channel signal STCH passes through the terminal bus
The packet data is sent to the packet control unit 700 described above.
Start data transmission/reception control. Also, the termination timing circuit 607 is activated by
Similarly, the end channel signal TECH is packet-based.
The data is sent to the control section 70 to complete packet transmission/reception control.
let 631 is output when channel number CHNO is zero
It is a zero detection circuit that outputs
The output of the match detection circuits 604 and 605 is prohibited.
Ru. This circuit 631 is provided in the
If packet area A is not specified at all, register
In order for the contents of stars 602 and 603 to become 0, the previous
The first channel number 0 of the synchronization area
Detected and false timing signal STCH,
This is to prevent TECH from appearing. Next, we will explain the packet data transmission operation.
Ru. A packet to be transmitted is created by the processing device 300.
is created and sent via the interface section 601.
FIFO buffer memory circuit (hereinafter abbreviated as FIFO) for
)612. this write
As mentioned above, is allocated in advance to the transmit FIFO 612.
write select signal that specifies the address
WS and packet data D to the above transmission FIFO 61
This is achieved by applying 2. After writing the packet data is completed, the processing
A transmission request signal is sent from the device 300, and this
Through the interface section 601, the flip
Applied to flop 610. This flip-flop
The AND gate 623 is opened by the output Q of the tap. The contents of the first channel register 602 and the channel
The number CHNO matches the first timing circuit.
When the 606 starts, its output becomes the first channel signal.
At the same time, it is sent out to the terminal bus as a number STCH.
It is applied to the AND gate 623. This Ann
The AND output of the gate 623 is the OR gate 625
sent as status signal STATA via
It will be done. This status signal STATA is packet based.
It is sent to the control section 700 and connected with the timing signal STCH.
When I realized that there was a request to send the product, I
let Also, the output of the first timing circuit 606
The flip-flop 611 is set and its output is
Force Q is applied to AND gates 626 and 628.
It will be done. As a result, the
It becomes possible to receive the transmission gate signal SG. On the other hand, in the packet control unit 700, the link packet
Look at the first bit of area A and see if it is an empty area.
When this is confirmed, the transmission gate signal SG is sent out.
This transmission gate signal SG is the AND gate 62
6 to an AND gate 620.
Therefore, while the transmission gate signal SG is on, the clock
The signal CLK enters the transmit FIFO 612 and this clock
The data is stored in the transmit FIFO 612 in synchronization with the
The packet data is sequentially passed through the AND gate 627.
It is then sent out. This sending data SD is the sending bus
The mode select of the transfer control unit 400 described above is
408. Also, transmission gate signal
The SG resets the send request flip-flop 610.
Set. This will change the status of waiting for the next transmission request.
Become a state. The contents of the link end channel register 603,
If the channel number CHNO matches, the above
The timing circuit 607 outputs the end channel signal.
Send out TECH. This exit channel signal
TECH is connected to the packet control unit 7 via the terminal bus.
Enters 00. The packet control unit 700 will be described later.
Complete the packet data transfer process and send it.
Turn off the gate signal SG. This allows you to send
Gates 620, 627 connected to FIFO 612
is closed and the packet data of link packet area A is
Terminates the sending operation. Next, the packet sent from the other node device is
The operation of receiving the cut data will be explained. The above also applies to node devices that receive data.
Similarly, based on instructions from the processing device 300, the link
Start channel and end channel number of packet area A
Set the numbers in registers 602 and 603 respectively.
Ru. First channel number set in the same way as above
and the channel number sent via the terminal bus.
When the number CHNO matches, the first channel signal
STCH is sent to the packet control unit 700. Pake
The destination control unit 700 inputs the destination address as described below.
Detects a match between the address of the host and its own node device.
Then, the reception gate signal RG is turned on. The above reception gate signal RG is sent to the link control section 700.
is added to the gate 628 of the transfer control unit 400.
Their packet data PAKD is stored in the reception FIFO 613.
Added. Flip-flop 611 is the first chip
Since it is set at the timing of the
Output Q causes AND gate 628 to be open.
Therefore, the receive gate signal RG passes through gate 628.
is applied to the AND gate 621. This reception game
While the clock signal RG is on, the clock signal CLK
enters the receive FIFO 613, and the packet is synchronized with this.
The data PAKD is imported. Receive FIFO6
The packet data stored in 13 is processed by processing device 30.
Read by 0. That is, this receive FIFO
Read select signal that specifies the address of 613
When RS is applied, packet data is gated
Sequentially read out to the processing device 300 via the front panel 617
be done. On the other hand, if there is an overflow in the receive FIFO 613,
The signal representing nothing is sent to the end timing circuit 607.
is added to the AND gate 624 along with the output.
Ru. Timing to send end channel signal TECH
When the data stored in the receive FIFO 613 exceeds the
-When you are in a flow state, the above AND gate 6
24 produces an output, which is the status signal.
It is sent to the packet control unit 700 as STATA.
Ru. End of link packet area A (see Figure 2B)
When a channel is detected, the termination timing circuit 6
The flip-flop 611 is activated by the output signal of 07.
The gate 627 is reset, and as a result, the gate 627 is closed.
Data reception processing is completed. The output of AND gate 628 changes from on to off.
Due to the change in status register 615,
One bit is set on. Processing device 300
is pre-assigned to the status register 615 above.
read select signal that specifies the address
Send RS and game the contents of register 615.
By reading through Tobatuhua 619,
It is possible to know the end of data reception. This reception
Completion is notified to the processing device 300 by interrupt processing etc.
You can also Status register 615
The read select signal RS of
and apply it to the reset terminal of that register 615.
be done. Therefore, the contents of register 615 can be read.
It will be automatically reset after Next, the packet data sent from the sending node device is
The data travels around the loop-shaped common transmission line and then returns to its own state.
Remove this when you return to your node device.
We will explain the process of importing. The packet control unit 700 is the link control unit 600.
When the first channel signal STCH is received from
The originating address of the channel and the own node device
Find a match with an address. Both addresses match
This means that the received data is
The data sent from the card device goes around and comes back.
It means that it is something that Both addresses match
Then, the packet control unit 700 performs
Sends the termination gate signal TEG, which is the terminal bus
It is added to the link control unit 600 via.
This end gate signal TEG is the OR gate 629
AND gate 6 through AND gate 630
Enter 22. Therefore, the clock signal CLK is
Transmission end FIFO 61 through AND gate 622
4, and the packet from the transfer control unit 400
Data PAKD is sequentially transferred to the transmission end FIFO 614.
be included. As described later, this termination gate signal TEG
On and off during the entire period of link packet area A.
At least the address information is
Channel period (A in the example in Figure 2G)₀From A₃no chi
It is set to be on only during the Janel period). one
On the other hand, the status gate signal STATG is the status
Information channel period (A in the example in Figure 2G)₁₅no chi
It is set to be on only during the Janel period). subordinate
The termination gate signal TEG and status gate signal
Packets are sent only while one of the STATGs is on.
Transmission that operates to capture data PAKD
The ending FIFO 614 is A₀~A₃and A₁₅Chiyane of
This will import data from the file. This is the end of transmission.
This function allows you to selectively receive only the information you need at the time of completion.
Ru. Of course, the end FIFO sends information other than the above
614. The processing device 300
Displays the address assigned to the communication end FIFO 614.
This can be achieved by sending the read select signal.
Data stored in FIFO 614 of
It can be read through the port 618. Packet control 700 The packet control unit 700 controls the link packet area.
Packet data of A and packet exchange area D
to generate the timing signals necessary for transmission and reception.
It is something. For convenience of explanation, the following is a link packet.
Let us now discuss the case of sending and receiving data in the target area. FIG. 10 shows an embodiment of the packet control section 700.
The circuit configuration is shown. The first channel sent from the link control unit 600
channel signal STCH and end channel signal TECH
is the leading timing circuit of the packet control unit 700
701 and end timing circuit 702, respectively.
added. This timing circuit 701, 70
2 is the first channel of the link packet area and
A signal synchronized to the termination channel and
Generates a timing signal delayed by the desired channel
It is for the purpose of These timing signals
Based on the data necessary for sending and receiving data as explained below.
A timing signal is created. First, let's talk about the operation when transmitting packet data.
I will explain. As mentioned above, the information sent from the link control unit 600
The status signal STATA that comes is packet data.
means a request to send. If this request is made,
The packet control unit 700 hunts for empty packet areas.
Start operation. First, the first channel of link packet area A
A₀vacancy display bit A₀₀(See Figures 2F and 2G)
check), that is, check the contents of the idle signal IDLE.
do. Idle signal IDLE is on (or “1”)
, check that the link packet area is free.
When it is off (“0”), it means it is closed.
shows. When the idle signal IDLE is off, the
The gate 713 is closed and the transmission operation has started.
Wait until the first channel comes again. If the idle signal IDLE is on, the
The transmission flip-flop is activated by the output of the gate 713.
705 is set, and its output Q is connected to the transmitting gate.
is sent to the link control unit 600 as a signal SG.
Ru. The link control unit 600 uses this transmission gate signal.
When SG is received, the transmission FIFO 612 is
Send the stored data sequentially to the transfer control unit 400
Ru. At the same time, the output Q of the flip-flop 705
passes through the OR gate 720 and outputs the mode select signal.
It is added to the transfer control unit 400 as MODSEL.
The transfer control unit 400 receives a mode select signal.
When MODSEL is input, the link control unit 600 sends
Sends the incoming transmission data SD. Also, the output Q of the flip-flop 705 is
Busy-on signal via OR gate 719
It is sent to the transfer control unit 400 as BUSYON.
Ru. This signal is a busy signal in the transfer control unit 400.
is applied to the control circuit 407, and the link packet area
A's blockage display bit A₀₀is displayed as blocked. On the other hand, the signal generated from the leading timing circuit 701
First channel A₀Check the signal synchronized with
It is sent to the transfer control unit 400 as a switch signal BCCRST.
put out Transfer control unit 4 uses this signal BCCRST.
Contents of block check register at 00
BCCR is initialized to zero. On the other hand, the signal at the next timing causes frizz.
Pflop 703 is set and its output Q
The transfer control unit 40 uses the transfer operation signal BCCACT.
Sent to 0. When this signal BCCACT is input,
Block check calculator 41 of transfer control unit 400
5 output to block check register 416 in order.
The next setting operation starts. After that, it notifies the end of link packet area A.
The end channel signal TECH is sent to the link controller 60.
When it is sent from 0, the end timing circuit 70
2 is activated. This circuit 702 is in the data area.
Later check bite (channel A in Figure 2G)₁₄)
Create a timing signal that should be transferred and apply this to
Block check selection via command gate 718
is sent to the transfer control unit 400 as a block signal BCCSEL.
put out When this signal BCCSEL is input, the block is
The check selector 414 stores the check calculation results.
The contents of the block check register 416
Check code channel of link packet area A
Le A₁₄(See Figure 2G) and send it to the common transmission line.
put out Also, the timing from the end timing circuit 702
Flip-flop 705 transmits by timing signal
is reset and its output Q is turned off, so
Transmission gate signal SG, busy-on signal BUSYON
and mode select signal MODSEL are all off
The transmission operation ends. Next, the link packet sent from the originating node device
data goes around the loop transmission path and returns to its own node.
The operation when returning to the device will be explained. As in the case of transmission, the link control unit 600 sends a message to the terminal.
The first channel signal STCH is sent as a packet via the bus.
input to the start timing circuit 701 of the start control section 700.
This circuit 701 is activated. Also, the transfer control unit
The address which is the output of the receive register 403 of 400
The packet control unit 700 matches the packet control unit 700 with the matching signal ADDR.
It enters the output circuit 710. The coincidence detection circuit 710
First channel A of link packet area A₀of Thailand
At the timing, the address signal ADDR and the address
Address of own node device generated from generator 711
Detect whether the response signal matches the response signal. Main implementation
In the example, as is clear from Figure 2G, the first channel
Nell A₀has an originating node address assigned to
Therefore, this channel A₀and the address
This means that the address of the source generator 711 matches.
is the packet data sent from its own node device.
that the data has gone around the loop transmission path and returned.
means. Therefore, at this time, the received data is automatically
Import it into your own node device and complete the process of completing the transmission.
Ru. First, if the above two addresses match, the andgame
The output of the gate 714 causes the flip-flop to terminate the transmission.
706 is set. This flip flop
The output Q of 706 passes through the OR gate 721 and becomes the bit
Transfer control unit 40 as g-off signal BUSYOFF
0 busy control circuit 407. busy
The control circuit 407 controls the start of the link packet area A.
Bit A₀₀is set to “0” (displayed empty), and other nodes
Enable the device to use the above packet area A.
Ru. On the other hand, the timing circuit 701
Address information of target area A (A₀~A₃channel)
is sent from the transfer control unit 400 to the link control unit 600.
Flip-flop 70 ends at the timing when it is issued.
Create a timing signal that turns on 7.
This timing signal is connected to the set terminal S and
and reset terminal R. Also the status bar
It (Channel A)₁₅information) is transferred by the transfer control unit 400
The timing at which the data is sent from the link controller 600 to the link controller 600
status flip-flop 708 is turned on.
The flip-flop 7 outputs a timing signal such as
23, made with AND gate 716 etc., this
to the set terminal S and reset terminal R of the 708.
Apply. And both flip-flops 70 mentioned above
7 and 708 outputs are respectively termination gate signals.
TEG, reset as status gate signal STATG
is sent to the link control section 600. The link control unit 600 controls the game as described above.
During the period when the output signals TEG and STATG are on,
Channel A₀~A₃and A₁₅Finished sending information for
It operates as if it were imported into FIFO. In addition, as mentioned above, the flip-flop 707,
708 is turned on only for a predetermined period.
The timing circuit 70 generates the timing signal.
1,702 as a counter or shift register
This can be easily achieved by using
Ru. Next, the packet sent from the originating node device
The operation when receiving data will be explained. In this embodiment, the third channel of link packet area A is
Nell A₂(See Figure 2G) has the destination node address.
If you want to receive data, please use the channel.
Nell A₂address information and its own node device.
A match with the address must be detected. child
First, the timing circuit 701
Yanel A₂Create a timing signal that synchronizes with
This is applied to AND gate 717. On the other hand, the address sent from the transfer control unit 400
response signal ADDR and own node device address
are compared in the coincidence detection circuit 710, and the channel
Le A₂If both addresses match at the timing of
The output passes through the AND gate 717 and receives the reception signal.
Applied to the set terminal of flip-flop 709.
Both addresses must match at the above timing
In this case, the sent packet data is sent to the own node.
This means that the information is addressed to the device. therefore received
To start operation, the packet control unit 700 resets
For the link control section 600, the flip-flop 70
Sends the output Q of 9 as the reception gate signal RG.
Ru. The problem here is that each node device
It is only in the third stage that it is determined whether or not to receive the
When channel destination node address information is received
However, if it is determined that it should be received,
1st channel A₀the source node address and the second
Channel A₁The source terminal address must also be captured.
The point is that there is a point. For this purpose, the first,
2 channel A₀,A₁information is also temporarily accumulated.
It is needed. FIFO of the aforementioned transfer control unit 400
Memory 409 delays packet data by two channels.
This is used to spread the first
Channel A₀allows receiving data from
Ru. In other words, the packet control unit 700
When the root signal FG enters the link control unit 600, this
In synchronization with this, the transfer control unit 400 transmits the first channel.
A₀From 16th channel A₁₅is the packet data PAKD
It enters the link control unit 600 as
It will be incorporated into the 13th. On the other hand, the timing circuit 702
Channel A of status device in target area A₁₅same as
Create a specific timing signal and use it as an andgame.
applied to gate 722. Receive flip-flop 7
After 09 is turned on, the above channel A₁₅of Thailand
AND gate 722 opens at timing, and its output becomes
Transferred as status select signal STATSEL
It is sent to the control section 400. In the transfer control unit 400
receives the status select signal STATSEL
Then, status information STATB indicating the reception status is displayed.
The above channel A₁₅Receives packet data on
It is sent to the communication register 404. The above status message
No. STATB is a separate stage as seen in Figure 10.
status signal STATA and end channel signal TECH
The delay circuit 704 outputs the logical product with
Created by delaying. Also, stay
As can be seen from Figure 9, the status signal STATA is
When performing logical AND with TECH, receive FIFO 613 is turned on.
- indicates whether the bar has flowed or not.
Ru. The above explanation is based on the data in link packet area A.
Described timing control for transmission and reception.
However, in the case of sending and receiving data in the packet switching area,
Since they are exactly the same, their explanation will be omitted. Packet interface section 800 The packet interface unit 800
Interface between conversion device 1100 and other devices
, which constitutes the packet exchange area D (Fig. 2C,
(See Figure 2D)
cormorant. Configuration and operation of this interface section 800
is the same as that of the link control unit 600 (see FIG. 9).
Since they are almost the same, only the different parts will be explained below.
do. FIG. 11 shows the packet interface section 800.
This shows the frame configuration control section in
The part shown in FIG. 9 is the same as in FIG. The packet exchange area D is clear from Figure 2C.
In the case of this example, a maximum of 4 areas can be placed in a frame.
It is possible to set. Therefore the leading channel
4 sets each of registers and end channel registers
It is necessary to prepare. Therefore, here we will introduce the four-word level.
A distaff file memory 822 is used. head
channel portion 810 and end channel portion 820.
The configuration is the same, and here we use the first chip as a representative example.
The Yarnel register portion 810 will be explained. First channel number of each of the four packet exchange areas
are stored in the register file memory 82 in order from the youngest
Initialize to 2. This setting can be changed from the processing device to the
Write select to specify address of memory 822
Signal WS and data D indicating each leading channel number
This is achieved by sending the . Processing device 30
The signal from 0 passes through the interface section 801.
The recorder enters the decoder 811 and is decoded here.
It is set in the file memory 822. Most
If you do not perform area division until the number of major divisions is 4, the remaining
Set the contents of the register to 0. The decoder 811 includes a channel control section 200
The node act signal NODEACT sent from
The channel level is applied only when it is off.
Register numbers can be read and written. child
The node act signal NODEACT is as mentioned above.
Activate or stop the operation of the node device.
It is used to perform control to stop the operation. Read the contents of the register file memory 822 above.
When reading the lead selector from the processing device 300,
The access select signal RS is sent, and this is the access select signal RS.
826. This access selector 8
26 is when the node act signal NODEACT is off.
The read select signal RS is sent to selector 82.
Add to 3. Data read from memory 822
The data passes through the selector 823 and the buffer gate 827.
The data enters the processing device 300 through the process. After the initial configuration is completed, the node act signal
NODEACT is turned on and packet data is sent and received.
control of communications begins. First, the channel control unit 200 sends
A circuit that detects when the signal CHNO representing the channel number is zero
Added to 825. This zero detection circuit 825 is
A match is detected when the channel number is zero.
The output of the output circuit 824 is prohibited. This has been mentioned before
As shown above, when no packet area is specified at all
The contents of register file memory 822 are
It is “0”, and the channel number of the synchronization area is 0.
The coincidence detection circuit 824 outputs an output at the timing of
This is to prevent this from happening. On the other hand, the output of the zero detection circuit 825 is
Enters the reset terminal of the counter 828, and the counter 8
Reset the contents of 28. In other words, the access
The counter 828 has a period of 0 for the synchronization area X of the frame.
maintain the state of This access counter 828
The contents of are added to access selector 826.
The access selector 826 has a node door in the on state.
Since the act signal NODEACT is applied,
The signal (“0”) input from the dress counter 828
Output as is. This access selector 826
The output of
This becomes a selection signal for the aisle memory 822. follow lever
The 0th word of the register file memory 822 is read.
detected and printed on one input of the match detection circuit 824.
added. Channel number signal on the other input
CHNO is applied. Both input signals match.
Then, the start time is determined by the output of the coincidence detection circuit 824.
The ringing circuit 802 is activated and the subsequent operation is
The operation is the same as that of the link control section 600. The access clock is determined by the output of the timing circuit 802.
The value of counter 828 is counted up and becomes “1”.
becomes. Therefore, this time register file memory 8
The first word of 22 is read and the second packet
Preparations begin to detect the first channel of the exchange area. The above is an explanation of the detection of the first channel.
However, the same is true for the end channel.
The details will be omitted. Frame generation control unit 900 An example of the configuration of the frame generation control unit 900
will be explained with reference to FIG. This frame generation control unit 900 is a loop-like common controller.
One of the node devices connected to the communication path
Node device (this is called frame control node device)
), and the transfer system shown in Figure 7
Transmission/reception section 400A and transfer section 400B of control section 400
connected between. The transmit clock oscillator 901 is a data transmitter of the present invention.
Serves as a transmission clock source oscillator in communication systems.
The frame control node device is the only one that sends
The above transmitting clock is used as the transmitting clock of the receiving section.
The output of oscillator 901 is used. Output pulse of the above transmission clock oscillator 901
is first applied to the decimal clock counter 902.
It will be done. The use of a decimal clock counter is
In the embodiment of the invention, one channel consists of 10 bits.
This is because it has been This clock counter 9
The output of 02 is further printed on the clock decoder 903.
is added and used here in the frame control node equipment.
clock signal CLK₀,CLK₀and will be described later
Synchronization circuit 906 and frame memory 912
A timing signal for access is generated. The above
Lock signal CLK₀, is a normal node device
Similarly to the clock signal CLK, for example
Of the 10 bits in one channel, bits 0 to 1
and between 5 and 6 bits.
It becomes “1” for each case, and “0” for other cases.
It's like a clock. On the other hand, the receiver 401 of the transfer control unit 400 generates
frame synchronizer based on the timing signal
Clock signal CLK, which is generated by 100
and the signal transmitted from the reception register 403
RR is synchronized with the receive clock, and the above-mentioned transmit
It is asynchronous with the output of the communication clock oscillator 901.
Ru. Therefore, in this frame generation control section, the above
Incorporates lock signals CLK, RR signals, etc.
Transmission clock CLK₀, and perform phase matching with
There is. For this phase adjustment, first the synchronization circuit 906
, the clock signal from the frame synchronizer 100
CLK, and the signal from the clock decoder 903.
signal is applied, and here the reception clock CLK,
The timing before and after the rise of , and the transmission clock
CLK₀The timing before and after the rise of
A signal is created that occurs at appropriate timing. On the other hand, receive clock CLK and channel
The signal CHACT is applied to the AND gate 930.
The output of this gate 930 is the receive channel counter.
is added to the printer 908. This allows the receiving channel to
Channel counter 908 counts the predetermined number of channels.
Deco 907 decodes this and outputs the end chip.
Generates Janel signal ENDCH. The count value of the reception channel counter 908 and the reception
The contents RR of the communication register 403 are the contents of the synchronization circuit 906.
Each output timing has a synchronous buffer register.
909 and 917. Furthermore, the buffer registers 909 and 91
The contents stored in 7 are the receive clock CLK.₀of
receive register 910 and
It is set to 918. The clock decoder 903 is a transmitting clock.
CLK₀From the rising edge of CLK₀Turn on until the falling edge of
The signal to be turned on, that is, 1/2 the time of one channel.
This creates a signal that turns on the address selector.
added to Kuta 911 and Light Gate 914.
Ru. As a result, there are two address selectors 911.
Select the output of the receiving register 910 from among the inputs of
and add it to the address input terminal 912 of the frame memory.
I can do it. At the same time, the light gate 914 opens and the reception
The output of register 918 is input to frame memory 912.
Enter the power data terminal. Therefore, the frame memory 91
2 contains the address indicated by the reception channel register 910.
The contents of the receive register 918 are written to the
That will happen. The frame memory 912 has 10 bits per word.
and the number of words equal to the total number of channels in one frame.
It has the capacity to store information. In other words, 1 frame
It has the capacity to store all the information for frames. The other 1/2 time in one channel, that is, the transmit clock
Lock CLK₀From the falling edge of CLK₀falling of
During this period, there are two address selectors 911.
Select the output of channel counter 904 from among the inputs of
Select the frame memory 912 address input terminal
Add to. The above channel counter 904 is sent
clock CLK₀is being applied, and the transmitting chip is
Counting the number of yarns. Frame memory 9 above
12, the address indicated by the value of the channel counter 909
The address information is read and the transmit clock CLK₀
In the transmission register 913 at the rising edge of
is set. The count value of the channel counter 904 described above is predetermined.
When the value (final channel number) is reached, the decoder 9
The value is reset by the output of 05. On the other hand, the data read to the transmission register 913 is
The information is transmitted along with the output of the synchronization pattern generator 915.
is added to transmit selector 916. Send selection
The channel counter 916 indicates that the channel counter 904 is
(channel 0 to channel 3 in this example)
output from the synchronization pattern generator 915.
When sending out force and showing other areas
The contents of the transmission register 913 are sent. This send
The output RR of the selector 916 is the output of the transfer control unit 400.
Sent to the transfer unit. That is, receive register 4
The information RR received by 03 undergoes the above operation.
The phase is aligned with the timing of the transmit clock.
After that, it is sent to the transfer unit. The frame generation control unit 900 performs the phase matching described above.
In addition to this function, it also has an abnormality monitoring function. Sunawa
In other words, all the occupancy display bits of all channels indicate occupancy.
If this state continues for a certain period of time,
It is determined that there is an abnormality in the system, and the air block display is displayed.
This is a function that forcibly changes the display to an empty display. This function is applicable to the circuits 919 to 919 of the circuit shown in FIG.
This is realized by 929 components. In the following explanation, the above abnormality monitoring function is
Anomaly detection in the exchange area and packet exchange area
This will be explained separately. Timing of circuit switching area B (see Figure 2B)
The detection is performed in the channel control unit 200,
Line gate signal that is on during the period of circuit switching area B
The number LING is sent. This line gate signal is
AND gate 923 with lock signal CLK
and its output is a delay type flip-flop 91.
It is added to the C terminal of 9. On the other hand, transmission register 9
Busy information for one channel read on 13
The information of the bit, that is, the first bit, is transferred to the above flip.
It is applied to the D terminal of flop 919. As a result
If the busy bit is on, flip-flop 9
19 is set, and its output Q is input to the AND gate 9.
25 and the line gate signal LING is turned off.
Busy counter through gate 925
Enter 921. In this way, all channels in one frame
The first bit of the file remains on for several frames.
, the contents of the busy counter 921 above correspond to that frame.
The count is increased by the number of games. If 1st
There is even one empty channel in the frame.
If there is, flip-flop 919 is turned off,
The busy counter 21 is reset by the output Q.
be done. The busy counter 921 has its count value.
When the fixed value is exceeded, that is, all channels are busy.
Output when the state continues for a predetermined number of frames.
issue. This output signal is the line gate signal LING.
Both were added to ANDGATE927, and the game
The output of gate 927 is sent through OR gate 929.
Enter the selector. This will keep all channels busy.
The transmitter is set only when the specified number of frames continues.
Among the information sent from the director 916, circuit switching
You can force the busy bit of a region to turn off.
can. Next, we will explain abnormality detection in the packet exchange area.
do. First channel signal STCH of packet exchange area
is an AND gate with clock signal CLK.
924 and its output is a delayed flip-flop.
is applied to the C terminal of pin 920. This flippuff
As before, each channel is connected to the D terminal of the loop 920.
The information of the first bit of the channel is added. flip
The flop 920 outputs the terminal of the first channel signal STCH.
If the busy bit is on during timing, it is set.
The output Q becomes "1". Output Q is “1”
If the AND gate 926 is the end channel signal
An output is generated at the timing of TECH, and this
- enters the counter 922. If one frame of chi
Even one channel in the channel is displayed as empty.
If there is, the flip-flop 920 will be reset.
The value of the busy counter 922 is determined by the output Q.
will also be reset. What is the status of all channels busy?
The frame continues, and the count value of the counter 922 is a predetermined value.
If the value is exceeded, the alarm will be reset at the timing of the first channel.
A busy off signal is issued from the end gate 928,
This enters the transmit selector 916. This will send
Packet exchange signal sent from communication selector 916
The busy bit in the area is forcibly turned off. In the embodiment described above, 8 bits of data +
Data validity display bit + channel empty display bit
When one channel is configured with a total of 10 bits (below)
Abbreviated as lower 10-bit method. ). However, when connecting only the following terminals,
8 bits is sufficient for one channel. (1) Voice (telephone) information 7-bit PCM + channel
Air block display bit (2) 6 bits of data + data valid display bit + channel
Yarnel Air Force Display Bit (3) The packet only contains 1 bit of the first channel.
is used to indicate the blockage of the entire packet, and its channel is
The data part of the file is 7 bits. 2nd channel
After that, all 8 bits can be used as data.
Ru. Configure one channel with 8 bits using methods (1) to (3).
This method will be abbreviated as the 8-bit method below. 10 in Figure 13
1-channel video using bit method and 8-bit method
Indicates the allocation of points. In the figure, B is the chain
A is the data valid indication bit,
v indicates an unused bit. The method described so far in this example is for 8-bit
Even if a method is adopted, it can be applied without any essential changes.
be. The following describes the 10-bit method and 8-bit method in this example.
By switching between the two methods, one type of
Regarding the switching means to be realized with the hardware of
I will explain. Adopt 10-bit method or 8-bit method
How to do this depends on the network system shown in Figure 1.
Determined by whether a terminal like
Ru. Switch or process at system startup
Which method is selected depending on the signal from the device 300
stipulate. The above-mentioned distinction between the 10-bit method and the 8-bit method
To realize the conversion, replace the frame synchronization part in Figure 4 with the following
Change it as follows. Synchronous pattern generator 101, matching circuit 102,
Period counter 106, decoder 107, clock counter
counter 114 and decoder 115 to the existing 10-bit
In addition to the 8-bit version, we have created a new version for the 8-bit version.
Bit/10 bit switching signal (hereinafter referred to as signal OCTET)
Name omitted. ) to switch. Signal OCTET
When starting up the system, the switch or processing
300. Output clock of decoder 115
In the case of the 8-bit system, the lock signal CLK is
1 when the value of clock counter 114 reaches 4.5
This is a signal that becomes . Or, either the 8-bit method or the 10-bit method.
By adopting a circuit system that can be shared, for example,
Synchronous counter 106 and clock counter 114
Turn on and off the signal OCTET by using one each
Allows both 8-bit and 10-bit operations to be performed.
It is also possible to make it possible to do so. Furthermore, the entire circuit shown in Figure 4 is constructed using an 8-bit system.
It may also be provided separately for use. Figure 14 shows the addition of 8-bit/10-bit switching function.
An example of a transfer control unit is shown below. The operation in the case of the 8-bit system will be explained below. Clock signal CLK from shift register 402
It is captured in the reception register 403 at the timing of
Among the 8-bit data, empty block display bit A02
is set together with empty block indication bit A00 in 10-bit system.
Enter Rector 1400. If signal OCTET is on
If so, bit A02 is output as A00'. wife
In both 8-bit and 10-bit systems, bit
A00′ is the vacancy display bit for that channel.
will appear. Signal given to busy control circuit 407
Reset or reset by BUSYON and BUSYOFF.
sky that is set or does not change at all
The error indicator bit A00″ is clocked into the transmit register 412.
Surrounded by the timing of the clock signal CLK
After that, selector 1401 is empty when using 8-bit method.
Entered along with display bit A02. Selector 1401 is
The signal OCTET signal is on and the packet is
If it is not the second channel or later, set bit A00″ to A02.
Output as . 2nd channel of this packet
As a signal indicating that it is not the following, the signal shown in Figure 10 is used.
2 channels obtained from the leading timing circuit 701
Use the inverted version of the signal CHN2 that represents the eye
ing. Signal OCTET is off, i.e. 10 bits
2 packets when using the 8-bit method and when using the 8-bit method.
From channel number onwards, bit A02″ is set as A02.
Output as is. When using the 8-bit method, the packet
After channel 2, use bit A02″ as is.
The data is passed through from the second channel onwards.
This is to secure data for 8 bits. In the end, I added two selectors 1400 and 1401.
In addition, by using 8 bits, transfer control is possible.
Processing of busy control, sending and receiving data, etc.
It is the same regardless of the difference between 8 bits and 10 bits.
So it's a good thing. 8-bit signal with air block information bit A02
is transmitted through the check selector 414.
413 at the timing of the clock signal CLK.
Be taken in. In the case of 8-bit method, 10-bit method
10-bit shift register 41 prepared for expressions
Take the serial output from the 8th bit terminal in the middle of 3.
put out. Selector 1402 indicates that the signal OCTET is on.
When the output of the 8th bit of the transmission shift register 413
The force is selected and becomes the output of the selector 1402, and the
It is sent to transmitter 418 in FIG. Signal OCTET
When off, the 10th bit output is selected and sent in the same way.
The signal is sent to the transmitter 418. Figure 15 shows the 8-bit/10-bit switching function.
This is a partial configuration example of the terminal control unit.
The parts added to Figure 8A are shown. First, when transmitting data from a terminal device,
When the signal OCTET is on, the eighth
Flipper set by signal SREQ in figure A
The output signal SD01 from the loop 516 is
Output as data valid display bit SD03′ when using
It works to make things happen. This selector 1500
Therefore, the terminal device can handle data regardless of whether it is 8 bits or 10 bits.
If the data valid display signal is output as the signal SREQ,
The bit position depends on the method being used at the time.
A data valid display signal is output at the location. Next, when the terminal device receives data, the reception
The signal RD selected by the director 520 or
Data valid display when using 8-bit method in IND
Bit RD03 is selected by selector 1501.
It is output as RD01′. This allows the terminal
The input side is independent of the 8-bit/10-bit system.
If you detect RD01′, you know the validity of the data.
I can do it. In the end, using selectors 1500 and 1501
Therefore, the terminal device can use 8 bits/10 bits.
In both cases, the data valid indication signal is sent to the same bit position.
This means that you can input and output numbers.

[Brief explanation of drawings]

Figure 1 is a schematic diagram for explaining the overall system configuration of the system of the present invention, Figures 2A, 2B, and 2C.
Figure, Figure 2D, Figure 2E, Figure 2F, Figure 2G,
Figures 2H and 2J are schematic diagrams for explaining the frame structure in the system of the present invention, Figure 2I is an explanatory diagram for explaining the operation of the system of the present invention during the circuit switching function, and Figures 3A and 3B. is a block diagram showing an embodiment of a node device in the method of the present invention, FIG. 4 is a block diagram showing an embodiment of the frame synchronization section in the method of the present invention, and FIGS. 5A and 5B are channel control diagrams in the method of the present invention. FIG. 6 is a block diagram showing an embodiment of the processing device section in the present invention. FIG. 7 is a block diagram showing an embodiment of the transfer control section in the system of the present invention. Figure 8A, Figure 8B
8C and 8D are block diagrams showing one embodiment of the terminal control section in the system of the present invention, FIG. 9 is a block diagram showing one embodiment of the link control section in the system of the present invention, and FIG. FIG. 11 is a block diagram showing an embodiment of the packet control section in the method of the present invention. FIG. 12 is a block diagram showing an embodiment of the packet control section in the method of the present invention. The configuration diagrams illustrating the embodiment, FIGS. 13 to 15, are 10-bit system/8 in the system of the present invention.
This shows the case where a bit system switching function is added. Fig. 13 is an explanatory diagram showing an example of channel bit allocation in the 10-bit system and 8-bit system, and Fig. 14 shows an example of the transfer control section. Block diagram: FIG. 15 is a block diagram showing one embodiment of the terminal control section. 100... Frame synchronization unit, 200... Channel control unit, 300... Processing device, 400... Transfer control unit,
500...terminal control unit, 600...link control unit, 7
00...Packet control unit, 800...Packet interface unit, 900...Frame generation control unit, 1
000...Terminal device.

Claims (1)

[Claims] 1. A plurality of communication node devices are connected to a common signal transmission path, and at least one of the communication node devices generates a transmission frame consisting of a plurality of channels circulating around the signal transmission path at one regular cycle, and transmits the transmission frame to each communication node. In a data communication method in which connected communication terminal devices communicate with each other using at least one channel in the transmission frame, the plurality of channels in the transmission frame are configured with the same size, and these channels are used for packet exchange. first storage means 216, 217 for storing at least the first channel number of the communication area for circuit switching; a second storage means 822 for storing at least the first channel number of the packet exchange communication area; and a second storage means 822 for storing at least the first channel number of the communication area for packet exchange;
means 200, 800 for selectively activating the circuit switching operation system and the packet switching operation system by comparing the channel numbers stored in the storage means of the first and second storage means; setting means 300, and by changing the channel numbers set in the first and second storage means by the setting means, packet switching and line switching performed via the transmission frame can be performed. A data communication method characterized by the ability to change the ratio.