JPS5821942A - Data communication system - Google Patents

Abstract

PURPOSE:To increase the efficiency for data communication, by detecting coincidence between the channel number of information during the reception and the channel number stored in a storage device and then starting a circuit which controls the packet communication or the circuit exchange in accordance with the packet communication control. CONSTITUTION:The connection controlling packet transmitted to a loop transmission line 1200 is received at each node device and then sent to a packet controlling part 700 from a packet controlling part 400. Coincidence is checked at the part 700 between the address of the destination and the own address. If the coincidence is obtained, a link controlling part 600 is started. Then the data is fetched into the part 600. In the case of an exchange of packets, the head channel of the packet is detected from the channel number signal through a packet interface part 1100 for the node device of the receiving side, and then the part 700 is started. Thus the data communication is possible for the circuits of both the circuit exchanging system and the packet exchanging system.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data communication system, and more particularly to a system in which a large number of terminal devices are connected to a common transmission path and data is transmitted and received between the terminals in a time-division manner.

In recent years, office automation (hereinafter abbreviated as OA) aimed at improving office productivity has been attracting attention. In the past, OA was mainly for executing individual, routine tasks through batch processing, but in the future, it will be possible to perform more advanced administrative tasks involving so-called data processing, such as electronic files, e-mails, document editing, etc. There is a growing demand for automation.

On the other hand, with the rapid development of optical communication technology based on optical fibers, light emitting diodes, etc., there is an increasing possibility that high-speed and low-cost digital transmission can be applied to familiar networks.

Based on this technological background, facsimiles, telephones,
Attempts are being made to realize a comprehensive network system in which word processors, personal computers, various data terminals, etc. are connected to a common signal transmission path so that data can be freely communicated between the terminals.

However, in order to realize such a network, the following problems must be solved.

Among current terminal devices, there are those that perform data communication using a single-line switching system and those that perform data communication using a packet switching system, and each switching network exists independently.

Therefore, in order to connect many types of terminal devices configured to perform data communication using different switching methods to a common transmission path and to communicate between the terminals, it is necessary to use either one-car switching method. It is necessary to enable data communication.

Especially when performing such data communication.

It is necessary to identify by which switching scheme the received data channel is configured.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data communication system that meets the above-mentioned requirements.

Connect multiple node devices with a common loop-shaped transmission path,
In a data communication method in which information on a large number of channels is repeatedly transmitted on this transmission path at a fixed period, and channel information is sent and received between terminal devices connected to the node equipment ff1K, it is used for packet communication and circuit switching among the large number of channels. The first channel number of each channel group for use is stored in the storage means, and a match is detected between the channel number of the information currently being received and the channel number stored in the storage means. The present invention is characterized in that a circuit for controlling packet communication or a circuit for controlling circuit switching is activated in accordance with the matching channel number when the matching channel number is reached.

First, the overall system configuration of the method of the present invention will be explained with reference to FIG.

In the figure, reference numeral 1 denotes a loop-shaped common transmission line, for example, an optical fiber is used. 2 is a node device connected to this transmission path, the details of which will be described later. For example, 32 to 64 of these node devices are connected per loop, and at least one of them has a function of generating frames in the synchronization signal area and the information channel area. Reference numeral 3 denotes a terminal device, such as a facsimile, a word processor, a personal computer, a minicomputer, a telephone, and various data terminal devices.

This terminal device has 1-node devices, for example, 8 to 3 node devices.
Two are connected. Therefore, in the above example, 256,111 to 2,048 terminals are connected to one loop transmission path. Of course, the number of these devices is merely an example, and it goes without saying that the system of the present invention is not limited thereto.

Next, the frame structure in the time division multiplex communication system of the present invention will be explained.

In the method of the present invention, bit string information is transmitted through the above-mentioned loop-shaped transmission path l, and a continuous bit group with a fixed number of bits is referred to as a channel, and a group with a fixed number of consecutive bits is called a frame. It is called. This frame is generated at a constant repetition period if the transmission rate is constant.

A frame in the system of the present invention is composed of a synchronization area X and an information communication area Y, as shown in FIG. 2A. For example, four channels are allocated as the synchronization area X, and the remaining channels are used as the information communication area. In this embodiment, one channel consists of 10 bits. The frame repetition period is chosen to be 125 μ5 (8 KHz) in this example.

Therefore, if the data rate is lQMbps, the number of channels in one frame is 125, and at 32Mbps, there are 4 channels.
Becomes 00 channel.

A 10-bit bit pattern for synchronization is inserted into each channel in the synchronization area. It is desirable that this bit pattern be a bit pattern that appears in the information communication area Y less frequently.

The information communication area Y has different frame configurations depending on whether the line switching function is used or the packet switching function is used.

Figure 2B shows the frame structure during circuit switching function, Figure 2C,
Figure 2D shows the frame structure during packet switching function, Figure 2E
The figure shows a frame configuration when both types coexist. Each frame structure will be explained in detail below.

Frame structure during circuit switching As is clear from Figure 2B, the frame during circuit switching is as follows:
The synchronization area X1 is composed of a connection control packet area A and a line switching area B.

The beginning of the frame is a synchronization area X that transmits a fixed synchronization character (one character is a bit pattern of IO bits) for identifying the beginning of the frame, and is composed of a plurality of channels. There are two next areas, a connection control packet area A and a circuit switching area B, but these can be placed in either order as long as they are consecutive areas. Further, areas other than the above three areas may be included in the entire frame.

The connection control packet area A contains the addresses of the destination node device and terminal device to which data is to be sent, the addresses of the originating node device and terminal device, and the channel number in the circuit switching area B used for data transmission and reception, etc. It is used to transmit so-called connection control information in the form of packets.

This connection control packet area includes 16 channels A0 to A0. as illustrated in FIG. 2F. It consists of Each channel is formed from lO bits, with the first bit A0
゜ is used to display the connection control packet area. In other words, the frame repetition period is 125 μB.
(9KHz), maximum 8 as connection control information
This means that it is possible to transmit different connection information per second per second, but if this connection control packet region is used, the number of connections per second is 80.

The empty status of this area is indicated by setting the bit to °l II, and if not used, to °0°. Similarly, this connection control packet area A is only used when setting a channel for data transfer between terminals, canceling the setting, etc., and is used only when data is actually sent and received. During this period, only circuit-switched channels are used.

Connection control packet area 2nd pin of the person's channel) A
111 is preliminarily provided in this embodiment) and is not directly related to the present invention, so its explanation will be omitted.

Ao of each channel, ~A0. The 8 bits represent data information. FIG. 2G shows an example of the relationship between each channel A0 to A t s of the connection control packet area A and the information transmitted via the channel.

Channel A0 is used to transmit address information of a node device that transmits data, and AI is used to specify one of the terminals connected to that node device. A is the address of the destination node device to which data should be sent.

is used to transmit information representing the address of the data destination terminal connected to the node device. Channel A4 is used to transmit a connection control code that indicates the distinction between a data transmission request and a data termination request. Channel A is used for transmitting information representing a specific channel number within circuit switched area B used to perform data communications.

Channels A6 to A are used for transmitting various parameters, but when communicating using multiple channels at the same time in the 0-circuit switching area B, the explanation of which is omitted as it is not directly related to this invention. Channels A and ~A 1 m can also be used to display used channel numbers. Channel A ta is used for transmission of check codes. For example, go to channel Ao~! The result of performing certain arithmetic processing on the data in step 3 is transmitted as a check code, and the receiving side performs the same arithmetic processing on the same data to check whether the transmitted data is correct. Channel A
11 is used for transmitting status information. for example,
When the data destination node device receives the data, the data destination node device receives the data from this channel A1. is loaded with predetermined information and sent back to the sender. This allows the source node device to confirm data delivery.

On the other hand, the circuit switching area B is the connection control packet area A.
It is used to exchange information between multiple terminal devices through the specified channel.

This circuit switching area B has an arbitrary number of channels BOrB,
, B! ... Consists of B1. As shown in Figure 2H, each channel consists of 10 bits.
Pitsu)B. ,~BI1. 7 are allocated for data transmission. First bit B. is used as an empty indicator bit to indicate whether the channel is empty or already in use. 2nd bit) BOf indicates whether the 8-bit data of that channel is valid data or not.
Used to display invalid data. This information is valid/invalid (Pick)B. The data rate can be adjusted by I, and the reason for this will be briefly explained below.

As mentioned above, in the method of the present invention, the period of one frame is selected to be, for example, 125 μ5 (BKHz), so the amount of data that can be transmitted in one second on one channel is 8 bits x gK =
64 bits. In the present invention, this channel is used as a unit, and one channel is allocated to each terminal when a transmission request is received from the terminal, even if the terminal handles extremely low-speed data. Therefore, the data rate of the terminal is, for example, 5Qb.
Even if one channel is allocated in the case of extremely low speeds such as ps, data to be transmitted is generated only once every 64 to 150 frames. Actually, even if a frame is repeatedly generated 8 times per second, it is sufficient to use the channel of that frame once every 1000 frames.
This means that extremely low-speed data can be transmitted. Therefore, if multiple frames are sent to one channel, frames with data on that channel and frames with no data at all will be repeatedly generated. If there is data, the B01 bit is displayed as valid, e.g. set to "1", and when there is no data, the BOf bit is displayed as invalid, e.g. set to "0°. Therefore, the Bo1 bit's ° A cycle of 1° represents the data speed.In other words, each node device can freely adjust and transmit and receive data at different speeds by using the Bo bit.

On the other hand, when transmitting high-speed data of 64 Kbps or more, this can be easily handled by allocating multiple channels. For example, 16 channels may be allocated to a terminal that handles high-speed data of 1 Mbpl.

Next, the data communication procedure using the circuit switching system will be explained with reference to the second engineering drawing.

In response to a transmission request from a terminal, the synode device creates a destination address from the logical address (for example, a telephone number) of the other party's terminal.The address of each node device is assigned by a known method, such as fixedly assigned in advance. You can decide.

Next, among channels Bo, ..., B, in circuit switching area B, search for a channel whose empty display pitch (Be., B, .sB2゜...) is empty (for example, °0°), and The channel is set to the main display (for example, "l"). Thereafter, a connection control packet is created based on the connection control packet format as shown in FIG. 2G. In this case, a code for displaying a connection request is stored in the area corresponding to channel A4, and
, data representing the hunted channel number is stored in the area corresponding to .

Once the connection control packet has been created, the empty connection control packet area A is found and the packet (this will be referred to as the first packet) is transmitted. As described above, the idle state of area A can be identified by looking at the idle status indicator bit A0 of the first channel Ao of the connection control packet area.

The above connection control packet is received by the receiving node, which interprets the packet information contents and first checks whether the terminal requested for connection is not in use. If it is not in use, the data of the given channel number (channel A) is ) is set in the control unit of the terminal of the node device. By setting this channel number to be used, data sent through this channel will be received by the terminal from now on. after that,
Response packet information indicating that channel setting processing has been completed is created at the destination node device, and this packet (referred to as a second packet) is sent to the transmitting node device.

After confirming the delivery of the first packet, the sending node device waits to receive the second packet of response information. After receiving the second packet, a start instruction is issued to the transmitting terminal at a certain timing.

On the other hand, the destination node device, after confirming delivery of the second packet representing the response information, immediately issues a start instruction to the terminal. At this point, the same channel number to be used has already been set in the terminal control units of the originating and terminating node devices, and from then on, information exchange between the two terminals at frame periodic intervals is performed in the circuit switching area until a termination request is received. Continuously through B's designated channels.

At the timing when a certain frame is being generated, if the data to be transmitted has not yet been generated at the terminal, the receiving side node device As mentioned above, data can be automatically adjusted by using the validity indicator bit.

Based on the occurrence of a data transmission termination request from the transmitting terminal, packet information representing the termination request is created. This packet information is transmitted to the node device on the receiving side. Both node devices send a stop instruction signal to the terminal and release the channel in use. The sending side sets the leading bit of the channel in use to 0'' to return it to an empty state, and the receiving side releases the set channel.

The control described above is executed based on instructions from a processing device within the node device, which will be described later.

Frame structure for packet exchange The frame for packet exchange consists of a synchronization area X and a kerat exchange area, as shown in FIGS. 2C and 2D.

The synchronization area X is for identifying the beginning of the frame.
This is the case of a frame during line switching and the situation of a field.

As for the packet exchange area, the entire information communication area may be made into one packet exchange area as shown in FIG. 2D, or it may be divided into a plurality of packet exchange areas as shown in FIG. 420.

Each packet area has a plurality of channels Do, D1 . The information to be transmitted on each channel is allocated in advance as shown in the figure. of course,
Although FIG. 2J shows an example, other methods can be used for t@'f, packet format, and address assignment.

In this embodiment, the side that transmits the packet, that is, the source address information, is transmitted through the first two channels D, , D, and the side that receives the packet, that is, the destination address information, is transmitted through the next two channels D*-Ds t''. The addresses of the node devices are transmitted to the channels D, , D, and the addresses of the node devices are transmitted to the channels D, , D.

is assigned the address of the terminal device.

Channel D and subsequent consecutive channels D4 to D/-1 are allocated for data transmission. Channel D before the last channel! -+ is channel D0~D/-! is assigned for the check code of information, and the final pie) D/ is assigned for the status.

Note that each channel is composed of 10 bits as in the case of Fig. 2F, and only the most significant bit of the first channel D0 is used to indicate whether or not the packet exchange area is empty, and the lower 8 bits of each channel are used for information. represents the content of

Next, the operation of data communication using the packet switching method will be explained.

The sender notes according to the sending request from the sending terminal.

The device waits for an empty packet area to be received, marks the area as occupied, and sends out kerato information to the transmission path.

Each node device checks the destination address D in the packet information, and if it does not match its own node address,
Transfer it as is to another node device. When the destination address of channel D matches its own node address, that node device starts receiving operations.

The receiving node device transmits the packet information to the receiving terminal connected to it, and also puts status information indicating that it has been received on the final channel D/ of the kerato information, and sends it to the next node device along with other information. sequentially transmitted.

When the packet information travels through the loop-shaped transmission path and returns to the sending node device, this sending node device uses channel D.
Since the originating address of D06 matches the own node address, the packet information is taken in. At the same time, the empty indication beep for that packet area is displayed. D06 is displayed as empty, and the transmission ends.

The sending node device can check the normality of the transmission by checking the status of the packet information taken in after the round.

The frame configurations and data communication methods during line switching and packet switching according to the present invention have been described above. However, in the present invention, it is also possible to perform data communication by appropriately switching between the two switching methods. It is also possible to simultaneously create both a circuit switching area and a packet switching area within a single frame, and perform data communication in a form where both switching methods are mixed.

FIG. 2E shows a frame configuration when circuit switching functions and packet switching functions are simultaneously implemented.

The bit formats of the synchronization area X1 connection control area A1 circuit switching area B and packet switching area of this frame are the same as those shown in FIGS. 2B to 2D, and therefore their explanation will be omitted. Similarly, in FIG. 2E, the order of the areas A, B, and D may be arbitrary, and the packet exchange area may be divided into a plurality of areas.

FIG. 3A shows an example of the overall configuration of a normal node device for realizing the data communication system according to the present invention, in which ioo is a frame synchronization section, 200 is a channel control section, 300 is a processing device, 400 is a transfer control section, 500 is a terminal control unit, 6
00 beam/reverse control unit, 700 packet control unit, 800
is a packet interface section, 1000 is a terminal device, 1
100 Fi packetizer, 1200 is an optical loop transmission line, and 1300 is a terminal path.

In such a configuration, the frame synchronization unit 100:
The synchronization area at the beginning of the frame is identified from the received signal sent from the loop transmission path 1200, and a four-way pointing signal indicating the beginning of the frame and the beginning of the frame content channel is created and sent to other parts.

The channel control unit 200 identifies the channel number within the frame, indicates the line switching area of the frame, controls the operation of the node, displays the status, etc.

The processing device 300 is a part that performs storage program control using a microcomputer, memory, etc., and performs program control such as connection control processing and initial setting processing.

The transfer control unit 400 receives an input signal from the loop transmission path 1200 and performs a process of exchanging the transmitted and received signals with a predetermined terminal device 1000 etc.
Create a signal to send to.

The terminal control section 500 controls the transmission and reception of data to and from the corresponding terminal device 1000, and also controls the transfer of data to and from the transfer control section 400. For this purpose, the channel number within the frame to be transferred is stored.

The link control unit 600 performs line switching connection control and packet transmission/reception processing. The packet control unit 700 has basic functions necessary for receiving packet m, and performs address matching detection, searching for an empty channel, creating transmission/reception timing, etc.

In the packet interface unit 800, control signals with the packetization device 1100 when having a packet exchange area,
Controls transmitted and received data, stores packet areas, etc.

A terminal bus 1300 connects these devices 100 to 800 and serves to control mutual transmission and reception.

In such a configuration, when a received signal enters from the loop transmission path 1200, the transfer control unit 400 receives and demodulates it, and the frame synchronization unit 100 identifies the synchronization signal at the beginning of the frame from the received and doubled signals, and It also creates the timing required for receiving the intraframe channel and sends it to other parts.

The channel control unit 200 creates a channel number signal according to the timing from the frame synchronization unit 100, sends it to the terminal bus 1300, determines whether it is within the rotation exchange area based on this channel number signal, and sends it to the terminal bus 1300. 1300. In addition, the link control unit 60
In G, it is determined from the channel number signal from the channel control unit 200 whether the received channel is at the beginning or end of the connection control packet area, and the result is sent to the packet control unit 700.

Now, when a transmission request is received from a certain terminal device 1000, the processing device 300 detects it and sends a request to the terminal control section 5o.

Issue a Hehant request. The terminal control unit 500 determines the vacancy in the circuit switching area based on the vacancy indication bit of each channel received from the transfer control unit 400 and the signal indicating that the channel is within the circuit switching area from the channel control unit 200. Search for the channel to be displayed, and when it is found, the channel number signal at that time is received and stored in the terminal control unit 500, and a signal is sent to the transfer control unit 400 to display the empty indication bit of the corresponding channel. loop transmission line 1200
Send to.

The processing device 300 inputs the destination address to the terminal device 100.
0 or a predetermined fixed address, read and create the destination address, own address, and empty channel number received from the terminal control unit 500, and create a connection request code. etc. are sent to the connection control packet format link control unit 600. At the same time, when the processing device 300 issues a transmission request to the link control unit 600, the packet control unit 700 checks the empty indication bit of the first channel in the connection control packet area, and if it is empty, sends a signal to the transfer control unit 400. is sent to the loop transmission line 120 to change the empty/busy indicator bit of the first channel to indicate a block.
Send to 0. At the same time, it sends a signal to the link control unit 600 to transmit the already set connection control packet to the transfer control unit 400 and put it on the loop transmission path 1200 as packet transmission information.

The connection control packet sent to the loop transmission path 1200 in this manner is received by each node device. The operation is such that the data in the area is sent from the transfer control unit 400 to the packet control unit 700, which checks whether the destination address and its own address match, and if a match is detected, starts the link control unit 600. Then, the link control unit 600 takes in the received connection control packet data, and further the processing device 300 reads it.

The processing device 30G interprets the content of the read connection control packet, checks whether the terminal device 1000 to which the connection is requested is not in use, and if it is not in use, sets the sending node device as the destination address. A connection control packet containing response information is created and sent to the link control unit 600 along with the transmission request.

Thereafter, similarly to the sending node device described above, an empty connection control packet area is found, its empty/busy indication bit is set to an occupied indication, and the created connection control packet is inserted into that area, and the packet transmission path 1200 is Send K. Furthermore, the processing device 30o sets the received empty channel number in the terminal control unit 500 of the terminal device 1000 that has received the connection request.

On the other hand, in the sending node device, when the packet sent by itself returns after going around the loop transmission path 1200, the sending address in the data received by the transfer control unit 40G matches its own address. The packet control unit 700
A signal is sent to the transfer control unit 400 to set the empty indication bit of the first channel in the connection control packet area to empty. On the other hand, when the sending node device receives a connection control packet indicating a response sent from the receiving node device, the packet control unit 700
It detects that the address matches its own address, and receives a connection control packet to the processing device 300 via the link control unit 600, as described above.

The processing device 300 checks the response information and sends it to the terminal device 1.
A start command is generated at 000. In addition, the information transmitted by the receiving node device can be transmitted through the loop transmission path 1200 by
When it learns that a cycle has occurred, it sets the empty/busy indicator bit of the first channel in the connection control packet area to empty and issues a start command to the terminal device 100G, as described above.

In the sending node device, based on the start command from the processing device 300, the sending data is sent from the terminal device 1000 to the terminal control unit 500.

The terminal control unit 500 detects whether the set channel number matches the channel number signal from the channel control unit 200, and if a match is detected, the terminal device 100
The transmission data from 0 is sent to the transfer control unit 40G, and the transmission data is inserted into the corresponding channel and sent to the loop transmission path 1200.

On the other hand, in the receiving side node device, the transmitted data is received by the transfer control unit 400 and sent to the terminal control unit 500.

The terminal control section 500 determines whether the set channel number matches the channel number signal from the channel control section 200, and if a match is detected, sends the received data to the input terminal device 1000. Note that data can be similarly transmitted from the receiving node device to the transmitting node device at the same time using the same channel.

Note that it is also possible to perform transmission from the receiving side node device to the transmitting side node device using different channels.

Next, in the sending node device, when the terminal device 1000 issues a transmission end request to the processing device 300, the processing device 3
00 creates a connection control packet that rejects disconnection,
In the same manner as described above, the data is transmitted to the receiving node device and the terminal device 1000 is instructed to stop.

At the same time, in the sending node device, the processing device 3
00 issues a channel release request to the terminal control unit 500,
When the channel number signal matches the number of the occupied channel, a signal is sent to the transfer control unit 400, the empty indication bit of the channel is cleared, and the channel is released.

Note that when the set channel number matches the channel number signal, the terminal control unit 500 transmits data with the validity indicator bit set to be invalid if no data has been received from the terminal device 1000 yet. , informs the other party that the data is invalid, and can deal with any processing speed on the terminal device 1000 side.

Further, in the transfer control unit 400, the link control unit 60
A function that creates a check code by performing predetermined calculations on the data of the 1st to 14th channels of the connection control packet sent from 0, inserts that code into the 15th channel of Nokukerato, and transfers it. Then, the data of the 1st to 15th channels of the received 9th connection control node are subjected to predetermined calculations, the received data is checked for errors, and the results are inserted into the 16th channel as status information. It also has a function to transfer files.

On the other hand, when performing packet exchange, the packet interface unit 800 of the sending node device detects the leading channel of the packet exchange area and sends the packet to the packet control unit 70.
Send to 0. In the Nokukerato control unit 700, the transfer control unit 4
If the empty channel indication bit from 00 is displayed, a signal is sent to the transfer control unit 400, and the empty indication bit of the first channel is set to the empty indication bit. At the same time, the kerato information created by the node conversion device 1100 and set in the kerato interface section 800 is sent from the transfer control section 400 to the loop transmission path 1200. In the receiving side node device, the packet interface unit 1100 detects the first channel of the kerat based on the channel number signal, and activates the packet control unit 700. It detects that the destination address of the received packet data is its own address, and sends the result to the packet interface unit 1.
Inform 100. The interface section 1100 receives and receives the sent packet data and sends it to the processing device 300. When the packet interface section 800 detects the end channel of the packet exchange area, it performs the end operation.

In each node device, when the packet data sent by itself goes around the loop transmission path 1200 and returns again, the packet control unit 700 similarly receives the packet data from the transfer control unit, and the sending address is set to the own address. If they match, the transfer control unit 400
, the header of the corresponding packet is set to empty, and the packet area is released.

FIG. 3B is a ninth node device that implements the data communication system according to the present invention, and shows an example of the overall configuration of a node device having a frame generation function. is the transmitting/receiving section 400A and the transfer section 4
00B, and a frame generation control unit 900 is provided between them.

The node device serves as the normal node device described above, and also serves to generate frames with a constant cycle that circulate through the loop transmission path 1200.

The frame generation control unit 900 stores the frame information that has passed through the loop in the memory of the frame generation control unit 900 via the transmitting/receiving unit 400A of the transfer control unit 400, and generates four frames at the end of the transmission, and Based on this, a synchronization area pattern is created first, and then the memory is sequentially read out to form a frame. The information is sent to the transfer unit 400B of the transfer control unit. Thereafter, the same operations as the others are performed, and information to the next node is sent via the 400 transmitting/receiving sections of the transfer control section. The frame generation control unit 900 also has a function of monitoring abnormalities. In other words, in each of the circuit switching area and the packet switching area, when it is detected that all the empty/occupied indication bits of each channel are continuously indicating this indication for a certain number of times or more, the empty/occupied indication bit of each channel is changed. The function is to force the display to be empty.

The other operations are the same as those shown in FIG. 3A, so their explanation will be omitted.

Hereinafter, specific configuration examples of each part in FIGS. 3A and 3B will be described in detail.

a) Frame synchronization unit 100 FIG. 4 shows an example of a specific configuration of the frame synchronization unit 100.

In the figure, signals TIM, SR, and OUT are signals generated by the receiver and shift register as detailed in FIG. From the loop transmission line 1200 to the transfer control unit 4
By demodulating the serial reception information sent to 00 by the receiver and extracting the timing of the bit interval of the reception information, the timing signal T of 50
An IM is created. Using this timing signal TIM, the p series of received information is sequentially transferred to the shift register. The parallel output of that shift register is signal 5i40LIT.

In frame synchronization 5ioo, synchronization pattern generator 101
The synchronization pattern in the frame synchronization area set in When this happens, the matching flip-flop 103 is passed through the AND gate 104 and set.

This flip-flop 1031Z) set has a/
The synchronization counter 106 is activated through the gate 1ost- to start counting the number of received bits thereafter.

The decoder 10 recognizes that one shift of the synchronization counter 106 corresponds to 90 bits per channel (10 in this embodiment).
7, the AND gate 108 checks whether the contents 15ROLIT of the shift register of the transfer control unit 400 match the synchronization pattern again. If they do not match, the AND gate 108 outputs the data through the OR gate 109. The matching flip-flop 103 and the synchronizing flip-flop 106 are reset, and again,
Each time a bit is received, a match between the contents of the shift register and the synchronization pattern is searched.

Shift register contents and synchronization pattern continue! If there is a match, the match flip-flop 103 remains set, and at that time, a signal is sent from the synchronization block 106 to the synchronization character counter 110, and the synchronization character counter 110 is incremented by one. In this way, when channels matching the synchronization pattern are continuously received, the number of characters is counted in the synchronization character counter 110. As mentioned above, if the number of channels in the synchronization area is 4, the value of the counter 110 is 3.
None, and the value of the synchronization counter 106 after detecting the next synchronization character of the fourth channel is, for example, 3 at the time of death,
That is, the decoders 111 and 107 detect that a coincidence has been obtained in four consecutive channels, and when timing the timing signal TIM, an output is generated at the AND GO (AND GO) 112, and the synchronization flip-flip 113 is set. , indicates that the synchronization has been established, and the set output is sent to the coincidence flip-flop 103 through the OR gate 109.
The synchronization counter 106 and the synchronization character counter 110 are all reset, and the output of the AND gate 104 is prohibited. Accordingly, - it is necessary to stop the dispersion operation and prevent the contents of subsequent information channels from being mistakenly regarded as synchronous channels.

On the other hand, the clock counter 114 is driven by the reception timing signal TIM and outputs the shift register output 8RO.
This is for creating a clock that indicates the timing at which the UT indicates information for -channels. For this purpose, when the AND gate 112 detects synchronization OK, the contents of the rip-tuk counter 114 are forcibly set to the value of the synchronization counter 106, that is, 3, and the value of the synchronization counter 106 and the rip-tuk counter 114 are Phase matching is performed by making the values the same. On the other hand, the output of the clock counter 114 is input to the decoder 115, and when the value of the clock counter 114 is 0.1, the decoder 115 outputs the error signal CLKI.
is output, and the value of the clock counter 115 is 5.
6, the clock signal CLKI is output. In addition, for special purposes, when the value of the clock counter 115 is 4, the clock signal CLK[[ is outputted.

According to this CLKI, the output of the shift register is transferred to the reception register as described later, and subsequent processing can be performed in units of information for each channel. On the other hand, even when the clock counter 114 is out of synchronization, the clock counter 114 is always operating, so the clock counter 114 is always output, and the processing of other parts of the node device is not interrupted.

When the synchronization flip-flop 113 is set, a channel act signal CHACT is sent from the frame synchronization unit 10G to the channel control unit 200, and the channel control unit 200
Activates the channel color/res in the clock signal CLKI.
Counting is started at the timing of clock signal CLKII.
The number of channels in the frame (excluding the number of channels in the synchronization area) is counted. When the contents of the channel color/ri reach the number corresponding to the number of channels in the information communication area (second figure Y) in the frame, the decoder sends an end channel signal END CH back to the frame synchronization section 100, and the ) 116 to reset the synchronization flip-flop 113. Accordingly, the synchronization detection operation as described above is started, and each time one bit is received by the shift register of the transfer control section 400, a check is made again to see if it is a synchronization character pattern. In addition, a check is made to see if the synchronization area of the next frame is normally received following the end of the previous frame.

Due to missing bits in the transmission information on the loop transmission path 1200, bit leakage due to noise, etc., there may be cases where no synchronization pattern is detected in the synchronization area of the next frame. In this case, since we want the channel information in the frame to be recognized correctly, it is necessary to immediately resynchronize or cancel the processing in the meantime. Must.

This synchronization shift is detected by resetting the synchronization flip-flop 113 in response to the end channel signal ENDCH indicating the end of the previous frame.
A match with the synchronization turn is detected at the timing when the value of 4 becomes 0, that is, at the timing when all the information of the synchronization channel at the beginning of the synchronization area of the next frame is input to the shift register of the transfer control unit 400. If the match flip-flop 103 is not reset, an output is generated from the AND gate 117 and sets the out-of-sync flip-flop 118. Out-of-sync flip-flop 118
The out-of-synchronization signal 8T OUT, which is the set output of , is sent to the channel control section 200 .

This flip-flop 118 was able to synchronize! 7
It is reset by the output of the lip flop 113.

(2) Channel control section 200 Figure 5 shows an example of a specific configuration of the channel control section 200.

As mentioned above, when the frame synchronization section 100 establishes synchronization and outputs the channel act signal CHACT, the channel control section 200 also outputs the clock signal CLK from the frame synchronization section 100 at the timing of the clock signal CHACT. AND gate 201 is opened and channel counter 202 starts counting.

When the contents of the channel counter 202 reach a value corresponding to the number of channels in the information communication area within the frame, the decoder 20
3 outputs an end channel signal ENDCH. Channel act signal OHACT from frame synchronization unit 100
turns off, it resets the channel counter 202 through the invert gate 204.

As will be described later, the output of the channel color/receiver 202 is sent to the terminal 1300 as a channel number signal CHNO through the AND gate 206 when the node act clip flop 205 is set.

On the other hand, the interface circuit 207 is a circuit for writing data to and reading data from the register selected from the processing device 30G, and its specific configuration is as follows.
For example, as shown in FIG. 5B.

The interface circuit 207 shown in FIG.
NC, terminal number TMNO, register number REGNO, read/write control signal R/W, and data D are input, and in the matching circuit 208, when synchronization signal 5YNC is input, the terminal number TMNO is input to the terminal number generator. 209
It compares it with the terminal number assigned to itself from , and when the two match, it produces an output from the AND gate 210 or 211 according to the read/write control signal R/W, and the write decoder 212 and the read decoder 213 to select the register number REGN from the processing device 300.
A write select signal WS or a read select signal R8 is output to the register corresponding to O. At the same time, the transmission gate 214 or the reception gate 215 is also selected, and data D from the processing device is written to the register selected by the write select signal WS, or the contents of the selected register are read and sent to the processing device. Send it or do it. Note that register numbers R and EGNO are not limited to registers;
It may also be something with a memory function, such as a flip-flop.

In FIG. 5A, line head channel register 216,
Line termination channel register 217, out-of-sync flip-flop 218, and node act flip-flop 205 are selected by register number REGNO from the processing unit.

The line start channel register 216 and line end channel register 217 contain the first channel number and the last channel number of the line switching area of the frame in advance according to the write select number WS or WS sent from the processing device through the interface circuit 207. is stored in advance. (9) The flip-flop 205 is set with data D at the timing of the write select signal WS when operating the node device. and,
When the match circuit 219 detects that the contents of the channel counter 202 match the line head channel register 216, the line switching area flip-flop 220 is set. Further, the match circuit 22 indicates that the contents of the channel counter 202 match the line end channel register 217.
1, the detection signal is delayed by a delay circuit 222 for a certain period of time, and then the flip-flop 220 is reset. When the flip-flop 220 is set, if the node act flip-flop 205 is in the set state, the AND gate 223 is opened and the line gate signal LING is output.
is generated and sent to the terminal bus 1300.

In the processing device 300, in order to know the state of the out-of-synchronization state flip-flop 218, the interface circuit 2
A read select signal S is sent through 07, the buffer gate 224 is opened, and the contents of the flip-flop 218 are taken in, and the flip-flop 218 is reset by a signal delayed for a certain period of time by the delay circuit 225.

Furthermore, the contents of register 216 or 217 are successively outputted through buffer gate 226 or 227 in response to read select signal R8 from interface circuit 207.

(3) Processing device 300 FIG. 6 shows an example of a specific configuration of the processing device 300.

The processing device 300 is divided into a processing section 300A and a conversion section 300B.
01, memory 302 and bus 303.

The address strobe signal 5YNC is connected to the board 303 to which the processor 301 and memory 302 are connected.
, address signal ADR8, read/write control signal R/
W and data D, and these signals are input to the converter 300B. In the conversion unit 300B, the processing unit 3
() Sends the upper bit of address signal ADR8 from OA to coincidence circuit 304, address strobe signal A8YN
The upper bits of the address are set in the address generator 305 at timing C. It is checked whether the address pattern indicates access to the interface circuit or not, and if they match, a synchronization signal 8YNC is generated. Also,
The lower bits of address ADR8 are sent out as they are as terminal number TMNO and register numbers R and EGNO.

In addition, the read/write control signal R/W is the synchronization signal 5Y.
It is sent through AND gate 306 at the timing of NC, and also sent through AND gates 306 and 307.
Data D is transmitted or received by opening buffer gate 308 or 309.

The various signals created in this manner are not limited to the interface circuit of the channel control unit 200 described above.
It is also sent to the interface circuits of the terminal control section 500, link control section 600, and packet interface section 800.

(4) Transfer Control Unit 400 FIG. 7 shows a specific example of the configuration of the transfer control unit 400, which consists of 400 transmitting/receiving units and a transfer unit 400B.

In the transmitting/receiving section 400λ, the receiver 401 receives information from the loop transmission path 1200, demodulates the information, and uses the information to generate the bit timing signal T I of the received information.
'M is extracted and the information is sequentially stored in the shift register 402 at the timing of this timing signal TIM.

Next, at the rising edge of the clock signal CLKI from the frame synchronization section 100 described above, the output of the lO bit of the shift register 402 is set in parallel to the reception register 403.

On the other hand, the transfer unit 400B sends two bits of the output of the reception register 403, the valid indication bit and the occupancy indication bit, to the reception register 404 as is, and sends the occupancy indication bit to the occupancy indication signal through the not gate 405. I
It is sent to the terminal bus 1300 as a DLE. The remaining 8-bit data information output from the reception register 403 is sent to the packet control unit 7 as a signal ADDR for address verification.
00 and one input of the status selector 406. Further, the other input of the status selector 406 receives a status signal 5TATB from the packet control unit 700 and a status signal indicating the presence or absence of an error, which will be described later. This status selector 4
In step 06, transmission data is selected in accordance with the status select 5TATSEL from the packet control unit 700. That is, when the signal is not present, the output of the reception register 403 is selected, and when the signal is present, the other input, such as the status signal 5TAB, is selected.

On the other hand, the STATSEL signal (status select) is sent, for example, when it is necessary to return the status to the 16th channel while receiving a connection control packet area, and selects the status signal 5TATB and the output of the zero detector 417. The selected output of status selector 406 is sent to reception register 404. In the reception register 404, input data is set using the signal CLKi from the frame synchronization unit 100. The empty/busy indication bit of the output of the reception register 404 is input to the busy control circuit 407, and the remaining 9 bits are input to the terminal bus 1300K as reception data RD.
At the same time, it is input to one of the mode selectors 408. Further, the output of 8 bits of data information from the reception register 404 is input to the register 1 constituting the FIFO memory 409. In the FIFO memory 409, the receive register 4
CLK output of 04 to registers 409-1, 409-2
It is sequentially stored in 409-3 at the timing of i and at the timing of CLK...

Therefore, the received data output from FIFO memory 409 is delayed by two channels and is sent to link control section 600 as packet received data PAKD.

The reason why the FIFO memory 409 is used here is that the destination address in the connection control packet is the third channel, and it is necessary to determine that the destination address is the own address and input the received data. It is from.

The other input of mode selector 408 has terminal bus 13
In this selector 408, when the mode selector signal MOD8EL from the packet control unit 700 is turned on, the transmit data SD from 00 is input.
When D is selected and the mode select signal MOD8EI is turned off, the output from the receiving register 404 is selected.

The busy control circuit 407 forcibly sets the empty/busy indication bit in the received information to a high display when the busy-on signal BUSYON from the packet control unit 700 is on, and when the busy-off signal BUSYOFF is on, the busy control circuit 407 The display bit is forcibly set to empty display. At other times, the busy control circuit 407 has the function of outputting the signal from the receiving register 404 as is.

Next, busy control circuit 407 and mode selector 40
8 is set in the transmission register 412 at the timing of the clock CLKI. Of the output of the transmission register 412, two bits, an empty indication bit and a valid indication bit, are inputted as they are to the transmission register 413 of the transmission section 400A.

On the other hand, the remaining 8-bit data information is input to check selector 414 and arithmetic unit 415.

The check register 416 is initialized to 6o by the reset signal BCCR8T from the packet control unit 700, and then receives the check operation start signal B from the packet control unit 700.
CCACT operates the arithmetic unit 415 to perform arithmetic operations on the output of the check register 416 and the output of the transmission register 412, and sets the result in the check register 416 at the timing of the clock CLK. This operation is a division by a specific constant, and is a method generally used for checking transmission information. These operations are repeated, for example, while transmitting data information of channels 1 to 14 in the connection control packet area.

At the 15th channel, a check select signal BCC8EL is sent from the packet control unit 700 to the selector 414, and the selector 414 selects the output of the arithmetic unit 415 at that timing and sends it to the transmission register 413.

The zero detector 417 indicates that all bits of the arithmetic unit 415 have a predetermined value,
For example, it has a function of detecting that it is O, and its output is input to the status selector 406 together with the status signal 5TATB. In short, zero detector 4
17 detects whether there is an error in the data information by checking whether the calculation results of each bit of the data information of channels 1 to 15 in the connection control packet area are all zero, for example. It is placed on the 16th status channel within the area.

The transmitting register 413 of the transmitting/receiving unit 40OA sets the outputs of the transmitting register 412 and the check selector 414 at the timing of the clock CLK[[ from frame Xl[100], and then transmits the contents to the timing signal TI.
The data is shifted one bit at a time by M and transmitted to the loop transmission line 1200 via the transmitter 418.

Further, as described above, the frame synchronization unit 100 generates clock timing even when frame synchronization is not established, so that received information can be transmitted easily at all times.

(5) Terminal control section 500 FIGS. 8A and 8B show an example of a specific configuration of the terminal control section 500, and FIG. 8A shows its basic part, and FIG.
The figure shows an empty channel selection section.

In the basic part of FIG. 8A, the interface circuit 501
is composed of a circuit similar to that shown in FIG. 5B, and sends and receives data to and from the processing device 300.

The transmission channel register 502 stores the channel number within the circuit-switched area to which data is to be transmitted, and the receive channel register 503 stores the channel number within the circuit-switched area to which data is to be received. The contents of the mode register 504 consist of 4 bits of information, of which 2 bits 504-1 and 504-2 indicate the bus connection method at the time of transmission. 504-1 indicates when data is to be transmitted to the loop transmission line 1200 via the transmission bus within the terminal bus 1300, and 504-2 indicates when transmitting data to the loop transmission path 1200 via the transmission bus within the terminal bus 1300; It tells you when to send data through.

First, the remaining bit 02 of the mode register 504 504-
3,504-4 indicates the bus connection method at the time of reception.
Bit 504-3 indicates the case where data is received from the loop transmission line 1200 via the receiving bus of the terminal bus 1300, and bit 504-4 indicates that data is received from the internal bus of the terminal bus 1aoo from the other terminal control unit in the same node device. This shows the case of receiving data via.

These transmission channel register 502, reception channel register 503, and mode register 504 are controlled by the write select signal WS from the interface circuit 501.
Data D can now be set, and the outputs of these registers 502, 503, and 504 are read by the read select signal R8, and the buffer gates 50
Interface circuit 5 via 5, 506 and 507
01.

Also, transmit and receive channel registers 502 and 5
03, the timing HTCL of the clock CLKI after the hunt request is made, as explained in detail in FIG. 8B.
The channel number CHNO is updated and registered using K-8 and B, and when an empty channel occurs in the circuit switching area, it is possible to finally register that channel number. 50 which is the transmission instruction of the mode register 504
Only when there is an output from the OR gate 524 that detects that one of 4-1, 504-2 is set, the output of the transmit channel register 502 is outputted to the matching circuit 510 by AND/GO (AND GO) 508.

Similarly, the OR gate 525 is used to transmit the transmission mode register 50.
It is detected that either one of the channel registers 504-3 and 504-4 is set, and the output of the channel register 503 is outputted to the coincidence circuit 511 by the analogue register 509.

Note that data from the processing device 300 is set in the registers 502 and 503 via the interface circuit 501, for example, when a connection control packet is received from the other party and the transmission/reception channel number is specified in ζ. be.

Matching circuits 510 and 511 detect a match between the contents of the receiving and transmitting channel register 502 and the receiving channel register 503 whose data is set in registers 502 to 504 and the channel number signal CHNO.

When the match circuit 510 detects a match between the channel number signal and the transmission channel register 502, the mode register 5
If the content of 504-1 is 1, the AND gate 512 is opened and the mode signal MODE is sent to the terminal bus 1300, and the buffer gate 514 is opened via the AND gate 513.
The contents of transmit buffer 515 are sent to terminal bus 1300. On the other hand, in the terminal device 1000, in order to turn on the transmission request signal 8REQ when the transmission data is complete, the 8-bit transmission data SD is set in the transmission buffer 515, and the transmission request flip-flop 516 is set.
The output signal 516 is used as a valid indication bit and is sent to the transfer control section 400 as transmission data 8D to the end-of-line bus 1300 along with data information when the buffer gate 514 is opened and dead. As described above, the transfer control unit 400 selects the mode select signal MODSE corresponding to the mode signal MODE.
L Operate the mode selector and send data 8
Send D to other node devices.

A signal obtained by delaying the coincidence output of the coincidence circuit 51G by the delay circuit 517 is sent to the terminal device 1000 as the transmission OK signal 80, while the transmission request flip-flop 516 is reset. Therefore, if a match of 1 channel number is detected before the transmission data from the terminal device 1ooo is complete, the validity indication bit of the transmission data 8D is 0, indicating that the transmitted data is invalid. In other words, if the processing speed on the terminal device 1000 side is slow and the data to be sent is not available, the processing speed on the terminal device 1000 side is not limited by displaying an invalid display.

Next, when a match is detected in the match circuit 510, if the pin 504-2 of the mode register 504 is 1, an AND gate 518 uses a Shibara gate 519 to transfer the aforementioned transmission data to internal bus data. Send it to the internal bus as IND.

On the other hand, when the match circuit 511 detects that the output of the receive channel register 503 matches the channel number from the terminal bus, bits 504-3 of the mode register 504
, 504-4.

That is, the reception selector 520 receives the reception data fLD from the reception bus and the reception data IND from the internal bus.
is input, and this selector 520 selects received data RD when bit 504-3 of mode register 504 is 1, and selects internal bus data IND when bit 504-4 of mode register 504 is 1. It has become. Among the data selected in this way, data information is input to the reception buffer 521, and the oath display bit is input to the reception buffer 521.
22. The AND gate 522 is activated by the valid indication signal of the valid indication bit and the coincidence output of the coincidence circuit 511.
The output of the receive selector 520 is set in the receive buffer 521, and the receive request flip-flop 523 is set. This flippuff■ Tsubu 5
The set output of 23 is sent to the terminal device 1000 as a reception request signal RREQ, and the contents of the reception buffer 521 are sent to the terminal device 1000 as reception data RD. When the terminal □ device 1000 receives the reception request signal RREQ, it sends back a reception OK double signal OK and resets the reception request flip-flop 523.

In this way, the 1-AND gate 522 transmits the received data to the terminal device 1 only when the valid indication bit is valid.
000, so it will be received only when it is sent as complete data by the sending terminal device, and data can be sent and received without being affected by the speed of the terminal device. can.

Next, the empty channel selection function will be explained with reference to FIG. 8B. Although FIG. 8B only shows the circuit related to the empty channel selection function during either transmission or reception, in reality, the circuit in FIG. 8B corresponds to transmission and reception.
Two circuits shown in the figure will be provided.

In such a configuration, when a hunt request is sent from the processing device 300 via the interface circuit 501, the AND gate 53 is sent at the timing of the clock CLKI.
1 to set the hunt request flip-flop 532. When the hunt request flip list tab 532 is set, the line gate No. 8 L indicating circuit switching area °q reception is set.
ING, an empty display signal IDLE indicating that the received data channel is an empty channel, and the output of the hunt request flip-flop 532 are input to the AND gate 533, and when the above-mentioned hunt condition is satisfied, an output is output from the AND gate 533. After the signal is delayed for a predetermined time by the delay circuit 534, the empty channel acquisition flip-flop 535 is set and the hunt request flip-flop 532 is reset. On the other hand, while the hunt request flip-flop 532 is set, the clock CLKI
36 is opened to obtain the signal HTCLK, and this signal is input to the channel register 502t or 503 in FIG. 8A. At that timing, the channel number signal CHNO is successively input to the channel register 502 or 503 and updated. As described above, when an empty channel is detected and the hunt request flip-flop 532 is reset, the register reading operation is stopped, so eventually the channel number corresponding to the empty channel is stored in the register. This means that

The output signal of the delay circuit 534 is input to the delay circuit 538 through the OR gate 537, where it is delayed for a predetermined time and sent to the packet control unit 700 as a busy signal BU8Y.
Converts to busy-on signal BUSYON. Thereby,
The transfer control unit 400 sets the idle indicator bit of the corresponding channel being transferred to an idle indicator, and prohibits hunting in other terminal devices. Thereafter, even after the hunt is established, the match output C0IN-8t or B of the match circuit 510 or 511 in FIG. 8A is sent to the delay circuit 5 through the AND gate 539 and the OR gate 537.
38, and after being delayed for a predetermined time by the delay circuit 538,
Similarly, it is sent as a busy signal BUSY, and the occupancy indication bit is set to occupancy indication. Note that the delay circuit 53B is provided to maintain appropriate timing.

After the flip-flop 535 is set and the node is established, χ is used as the set output, and the AND gate 531
, and prohibits future I/O requests to prevent double channel hunting.

On the other hand, when data transmission or reception is completed and the occupied channel is to be released, the interface circuit 501 sends out a write select signal WS according to an instruction from the processing device 300, and an AND gate is executed at the timing of the clock CLKI. 540 and release request flip-flop 541
Set. Then, the channel register 5 in FIG. 8A
Waiting for a match between the contents of 02 or 503 and the channel number signal CHNO, the match circuit 510 or 5
11, a match is detected and the signal C0IN-8 or C0I
When N-R is output, the output from the anime game) 542 is delayed for a predetermined time by the delay circuit 543 for timing adjustment, and then the empty display OK defect signal DLEOK is sent to the packet controller 7.
00, a busy-off signal BU8YOFF is sent to the transfer control unit 400, and the empty indication bit of the occupied channel is forcibly set to the idle indication.

At the same time, the release request flip-flop 541 and the channel clearing flip-flop 535t are reset and the release operation is performed.

2. Make sure that the terminal control unit of the Kaede filter in the same node device does not enter the I/NT ice state at the same time. Multiple terminal controllers are connected to the same channel.
It prevents it from entering.

In the above-mentioned embodiment, a case has been described in which the terminal device occupies only one channel for transmission or reception, but the terminal device may use multiple channels *t+p. FIG. 8C shows an example of the configuration of the main part of the basic part of the terminal control section in this case.

In the figure, channel registers 551 and 552 are used for both transmission and reception, and matching circuits 555 and 556 detect a match between the contents set in these registers t' and the channel number signal C) iNO. When a match is detected in the mosquito circuit, an output is made from the OR gate 557.

On the other hand, in order to adjust the speed of the terminal interface for sending and receiving, FIFO memories 558 are provided for sending and receiving, respectively.
and 559 are provided.

This FIFO memory 558 contains terminal device jl1000.
At the timing of the transmission request signal 8REQ sent from the sender, a validity indicator bit indicating that the data is valid is stored together with the transmission data SD.

When a match is detected as described above, the detection signal is delayed for a predetermined time by the delay circuit 560, and the transmission data stored in the FIFO memory 558 is read out at the timing of the delay signal. At this time, when transmitting data, the mode register 504's pins 504-1 and 504-2
The same operation as that described in FIG. 8A is performed depending on the contents of .

On the other hand, when receiving data, the mode register 50
Depending on the contents of bits 504-3 and 5L)4-4 of bit 4, receive data RD or internal path data IND is selected by selector 520 as described in FIG. Sometimes the data is FIF
The data are sequentially stored in the O memory 559, and the contents are read out at a predetermined timing and sent out as the read terminal device 100GK reception data RD.

Further, a circuit having an empty channel selection function as shown in FIG. 8B is provided corresponding to the channel register 551, and in that case, the output signal H of the J node gate 536 is
Apply T CL K-I SHT CL K -n to the channel registers 551 to 552, and at that timing, the channel number CHNO is applied to the channel register 551 P one after another.
-552 and update.

Further, the OR gate 563 calculates the logical sum of the outputs of each bit of the mode register 504, and only when any bit of the mode register 504 is set to 1, the outputs of the channel registers 551 to 552 are output to the AND gate 553.
~554 to the matching circuit 553/-554. Also, the coincidence output C0 of the coincidence circuit 555ff556
IN-1 to C0IN-n are connected to each AND gate 53
9 and 542.

Also, the output obtained by calculating the logical sum of the outputs of each delay circuit 538 using an OR gate is sent out as the busy signal BUOY, and the logical sum of the outputs of each delay circuit 543 is similarly calculated, and the output is multiplied by the empty display OK. Signal DLEO
It is configured to be sent as K.

Further, in response to read select signal BS from interface circuit 501, buffer gates 561 and 562 can be opened to allow the contents of channel registers 551 to 552 to be taken into the processing device.

In the embodiment described above, by using the mode register 504 and the internal bus, it is possible to communicate between any two of the plurality of terminals within the same node device. This will be explained in detail with reference to the drawings.

The figure shows a transfer control unit 400, a plurality of terminal control units 500A,
This shows the connection relationship with 5ooB, and the terminal bus 1300
are buses necessary for connection between them, that is, a bus 1301 for mode signal MOOE, a transmission bus 1302 for transmission data SD, and a reception bus 1303 for reception data RD.
, an internal bus 1304 for internal bus data IND, and a bus 1305 for channel number signal CHNO.

500 terminal control units and 500B in a four-node device
When communicating between the terminal control units 5GOA and 5
The values of the transmission channel register 502 and reception channel register 503 in 00B are set to the same channel number.

Next, an example of a method for setting a channel number will be described. One terminal control unit on the transmitting side, for example, 500 people, searches for an empty channel, and when an empty channel is found, sets the channel number in the transmission channel register 502. The processing device 300 reads the channel number set in this register 502, and stores the same channel number in the reception channel register 503 in the same terminal control unit 500A.
It is also set in the transmission and reception channel registers 502 and 503 in the other terminal control unit 5oo13. Furthermore, in the mode register 504 in the terminal control unit 500A, the processing device 300 sets bits 504-2 and 504- to instruct connection to the receiving bus 1303 on the receiving side and to the internal bus 1304 on the transmitting side.
3 is set to 1, and in the mode register 504 in the terminal control unit 500B, the receiving side is connected to the internal bus 1304.
, the transmitting side sets bits 504-1 and 504-4 to 1 to instruct connection to the transmitting bus 1302. Accordingly, the transmitting information from the transmitting section 590B of the terminal control section 500B is transmitted as shown in FIG. 8D. 1 transmission bus 13 as shown in the thick line
Similarly, a mode signal is sent to the transfer control unit 400 via the bus 1301.
send to When the mode signal of the bus 1301 is turned on, the transfer control unit 400 sends the transmission information to the loop transmission line 1200 on the channel with the set number.

The information that has circulated around the loop transmission path 200 in this manner is received by the transfer control section 400 and sent to the reception section 591A of the terminal control section 500A via the reception bus 1303.

On the other hand, when transmitting information from the terminal control section 500A to the terminal control section 500B, as shown by the bold line in FIG. The data of 1304 is now received by the receiving section 591B of the terminal control section 500B.

Moreover, the dotted line in the figure shows the signal path in the opposite case to that described above.

Link Control Unit 600 The link control unit 600 performs transmission and reception processing of packet data in the connection control packet area A (hereinafter abbreviated as link packet data) during the circuit switching function. This link control unit 600(1)! The configuration and operation are almost the same except for the configuration and operation of the device that transmits and receives data during the packet switching function and the terminal interface.

FIG. 9 shows an example of the configuration of the link control section 600.

In the figure, 602 and 603 are registers, in which the first channel number and the end channel number of the interface link packet area (abbreviated as interface link packet area) are initialized, respectively, by the processing device 300 described above. Therefore, in the case of a frame configuration as shown in FIG. 2B, for example, the value of channel number 5 is set in the link start channel register 602 and the value of channel number 2o is set in the link end channel register 603. When setting data representing a channel number in each register 602, 603, a write select signal WS specifying an address assigned in advance to each register and data D representing a channel number to be set are used.
By applying and to the register, K is realized. Furthermore, when a read select signal fL8 that specifies the address of each register 602, 603 is applied, the data representing the channel number stored in each register is transferred through the buffers 608, 609, and 609, respectively. Read out.

The outputs of both registers 602 and 603 are sent to the channel control unit 2.
Along with the channel number information CHNO sent from 00 through the terminal bus, the scattering output circuits 604 and 60 respectively
Added to 5. - The scatter product output circuit 604 has a register 60
When the contents of 2 and the channel number information CHNO match, an output signal is output, and the leading timing circuit 60
6 is activated. This timing circuit 606 outputs the signal 5TCH at a timing synchronized with the clock CLKI in the first channel. On the other hand, -scattering output circuit 60
5 is the contents of the register 605 and the channel number information CH
When the output signal matches NO, an output signal is output, which activates the end timing circuit 607. This timing circuit 607 outputs a clock signal CL in the end channel.
The signal TECH is output at a timing synchronized with KM.

Upon activation of the start timing circuit 606, the start channel signal 5TCH is sent via the terminal bus to a packet control unit 700, which will be described later, to start packet data transmission/reception control.

Furthermore, upon activation of the end timing circuit 607, the end channel signal TECH is similarly sent to the packet control section 700, thereby completing the packet transmission/reception control.

Reference numeral 631 is a zero detection circuit that outputs an output when the channel number CHNO is zero, and when this output is present, the outputs of the coincidence detection circuits 604 and 605 are inhibited. This circuit 631 is provided because the contents of the registers 602 and 603 become 0 when no link packet area person is specified. Timing signal 5T by mistake
CH.

This is to prevent TECH from being output.Next, the packet data transmission operation will be explained.

A packet to be transmitted is created by the processing device 300,
FIFO for transmission via interface section 601
Buffer memory circuit (hereinafter abbreviated as FIFO) 612
are written sequentially. This post, as mentioned above,
This is realized by applying a write select signal WS specifying an address previously assigned to the transmission FIFO 612 and packet data D to the transmission PIFO 612.

After writing of the packet data is completed, the processing device 300
A transmission request signal is sent from the interface section 601 and applied to the flip-flop 610 via the interface section 601. The cyanto gatero 23 is opened by the output Q of this flip-flop.

The contents of the first channel register 602 and the channel number C
When the first timing circuit 606 is activated with the first channel signal HNO, its output is sent to the terminal bus as the first channel signal 5TCH and applied to the AND gate 623 at the same time. The logical product output of this AND gate 623 is sent to the status signal 5TAT via an OR gate 625.
Sent as . This status signal 5TATA is sent to the packet control section 700, and the timing signal 5TCH
By calculating the product of

Further, a shift flip-flop 611 is set by the output of the head timing circuit 606, and its output Q is applied to AND gates 626 and 628. As a result, it becomes possible to receive the transmission gate signal SG sent via the terminal bus.

On the other hand, the packet control unit 700 looks at the first bit of the link packet area and, when confirming that it is an empty area, sends out a transmission gate signal SG.

This transmission gate signal 8G passes through the AND gate 626 and is applied to the AND gate 620. Therefore, while the transmission gate signal 8G is on, the clock signal CLK enters the transmission PIF0612, and the transmission F
The packet data stored in IFO 612 is sequentially sent out through AND gate 627. This sending data 8D is applied to the mode selector 408 of the aforementioned transfer control section 400 via the transmission bus. Also, a transmission request flip-flop 61 G') is sent by the transmission gate signal 8G! j
Set above. This puts the device in a state of waiting for the next transmission request.

When the contents of the link end channel register 603 match the channel number CHNO, the timing circuit 607 sends out the end channel signal TECH as described above. This end channel signal TECH enters the packet controller 700 via the terminal bus. The packet control unit 700 performs packet data transfer completion processing, as will be described later, and turns off the transmission gate signal SG. For this purpose, the sending FIF
Games) 620 and 627 connected to O 612 are closed, and the packet data transmission operation of the S/Q packet area is completed.

Next, the operation of receiving packet data sent from the other party's node device will be explained.

Similarly to the above, in the node device that receives data, based on instructions from the processing device 300, the start channel and end channel numbers of the link packet area are stored in the register 602.
603 respectively. When the first channel number CHNO set in the same manner as described above and the channel number CHNO sent via the terminal bus match, the first channel signal 8TCH6 is sent to the packet control section 700. As will be described later, when the packet control unit 70G detects a match between the destination address and the address of its own node device, it turns on the reception gate signal RGt-.

The reception gate signal RG is applied to the gate 628 of the link control section 700, and the packet data PAKD from the transfer control section 400 is applied to the reception PIFO 613. Since the flip-flop 611 is set at the timing of the first channel, its output Q causes the cyanto gatero 2
8 is open.

Therefore, reception gate signals R and G are applied to AND gate 621 through gate 62B. This reception gate signal R
During the period when G is on, the rip-tsuku signal CLK is sent to the reception FIFO.
613, and in synchronization with this, the notebook data PAK
D is imported. The packet data stored in the reception FIFO 613 is read out by the processing device 300. Finally, when a read select signal R8 specifying the address of this reception PIFO 6t3 is applied, the kerat data is sequentially read out to the processing device 300 via the gate buffer 617.

On the other hand, a signal indicating the presence or absence of overflow of the reception PIFO 613 is applied to the AND gate 624 together with the output of the end timing circuit 607.

If the data stored in the receiving FIFO 613 is in an overflow state at the timing of transmitting the end channel signal TECH, an output is generated from the above-mentioned computer game controller 624, and this is transmitted to the packet controller 700 as a status signal 5TAT.

When the end channel of link packet area A (see FIG. 2B) is detected, the shift flip-flop 611 is reset by the output signal of the end timing circuit 607, and as a result, the gate 627 is closed and the data reception process is completed. .

When the output of AND gate 628 changes from on to off, one bit in status register 615 is set on. The processing device 300 sends a read select signal BS specifying an address assigned in advance to the status register 615, and reads the contents of the register 615 via the gate buffer 7619, thereby determining the end of data reception. I can do it. The completion of reception can also be notified to the processing device 300 through interrupt processing or the like. The read select signal R8 of the status register 615 is sent to the register 6 via the delay circuit 616.
15 reset terminals. Therefore, register 6
After the contents of 15 are read out, it is automatically reset.

Next, the packet data sent by the sending node device is
The process of inputting the data when it goes around the loop-shaped common transmission path and returns to its own node device will be explained.

When the packet control unit 700 receives the first channel signal 5TCH from the link control unit 600, it detects a match between the originating address of the first channel and the address of its own node device. If both addresses match, it means that the received data is the data that has been sent from the own node device and returned in one cycle.0 When both addresses match, the packet control unit 700 A termination gate signal TEG is sent out as follows, and this is applied to the link control section 600 via the terminal bus.

This end gate signal TEG passes through OR gate 629 and AND gate 630 and enters AND gate 622 .

Therefore, the clock signal CLKfi is applied to the AND gate 62.
2 and is added to the transmission end FIFO 614, and the packet data PAND from the transfer control unit 400 is sequentially taken into the transmission end FIFO 614.

As will be described later, this termination gate signal TEG is not on during the entire period of the link packet area, but at least during the channel period of the address information (second G
In the example shown in the figure, the channel is turned on only during the channel period from Ao to person.

On the other hand, the status gate signal 5TATG is turned on only during the channel period of the status information (in the example of FIG. 2G, the channel period of person 8.).

Therefore, the end gate signal TEG and the status gate signal 8
Transmission termination FIPO 6 operates to input packet data PAKD only while any one of TATG is on.
14 will input data of channels A0 to A1° and A1°. This is a function that selectively receives only the necessary information at the end of transmission. Of course, information other than the above may be taken into the transmission end FIFO 614.The processing device 300 reads the data stored in the transmission end PIFO 614 by sending out a read select signal representing the address assigned to the transmission end PIFO 614. It can be read out through buffer gate 618.

Packet Control 700 The packet control unit 700 is for generating timing signals necessary for transmitting and receiving packet data in the link packet area and the packet exchange area. For convenience of explanation, the case of transmitting and receiving data in the link packet area will be described below.

FIG. 10 shows a circuit configuration of an embodiment of the packet control section 700.

The start channel signal 5TCH and end channel signal TECH sent from the link control section 600 are applied to the start timing circuit 701 and end timing circuit 702 of the packet control section 700, respectively. The timing circuits 701 and 702 are for producing a good signal in synchronization with the first channel and the last channel of the link packet area, and a timing signal delayed by an arbitrary channel amount from the good signal. Based on these timing signals, timing signals necessary for transmitting and receiving data, which will be described below, are created.

First, the operation when transmitting packet data will be explained.

As described above, the status signal 5TATA sent from the link control unit 600 means a request to transmit packet data. When this request is received, the packet control unit 70
0 starts a hunt operation for an empty packet area.

First, the first channel person with a large link packet area.

vacancy display bit A0° (see Figures 2F and 2G),
Check the contents of the idle signal IDLE. When the idle signal IDLE is on (or °1"), it indicates that the link packet area is empty, and it is off ("0").
') indicates that the channel is occupied.When the idle signal IDLE is off, the AND gate 713 is closed, the transmission operation is not started, and the idle signal IDLE is turned on until the first channel comes again. In some cases,
The transmission flip-flop 705 is set by the output of the AND gate 713, and its output Q is the transmission gate signal SG.
It is sent to the link control unit 600 as a. When the link control section 600 receives this transmission gate signal SG, it sequentially sends out the data stored in the transmission PIFO 612 to the transfer control section 400 as described above. At the same time, the above flip-flop 70
The output Q of 5 is passed through the OR gate 720 and is seen by the transfer control unit 400 as the mode select signal MOD8EL.

When the transfer control section 400 receives the mode select signal MODSEL, it sends out the transmission data SD sent from the link control section 600.

Further, the output Q of the flip-flop 705 is sent to the transfer control section 400 as a busy-on signal BUSYON via an OR gate 719.

This signal is transmitted to the busy control circuit 4 in the transfer control section 400.
07, and the empty/occupied indicator bit A0° of the link packet area is set to indicate occupancy.

On the other hand, the first channel person generated from the first timing circuit 701. Check the signal synchronized with the reset signal BCC
It is sent to the transfer control unit 400 as R8T. This signal B
The content BOCR of the block check register in the transfer control unit 400 is initialized to zero by CCR8T.

On the other hand, the shift flip/flop 703 is set by a signal at the next timing, and its output Q is sent to the transfer control unit 400 as a check operation signal BCCACT.

When this signal BCCACT is input, an operation for sequentially setting the output of the block check calculator 415 of the transfer control unit 400 in the block check register 416 is started.

Thereafter, when the end channel signal TECH indicating the end of the link packet area A is sent from the link control unit 600, the end timing circuit 702 is activated. This circuit 702 is a check byte (second G
Channel person 8 in figure. ) is generated, and is passed through the AND gate 718 to the transfer control unit 40G as the block check select signal BCC8EL.
Send to. When this signal BCC8EL is input, the pre-check check selector 414 changes the contents of the block check register 416, which stores the result of the check operation, to the channel number 1 of the link packet area-sized check code. (see Figure 2G) and sends it out to the common transmission path. Also, the timing signal from the end timing signal 702 resets the transmitting block flop 705 and turns off its output Q, so that the transmitting gate signal SG and the busy-on signal BU are
8YON and mode select signal MOD8EL are all turned off, and the transmission operation ends.

Next, the operation when the link packet data sent from the originating node device goes around the loop transmission path and returns to its own node device will be explained.

As in the case of transmission, the leading channel signal 5TCH is transmitted from the link control unit 600 to the packet control unit 70 via the terminal path.
Enters the leading tie construction circuit 701 of 0, and this circuit 701
starts. Also, the reception register 40 of the transfer control unit 40G
The address signal ADDR, which is the output of No. 3, enters the coincidence detection circuit 710 of the packet control section 700. -Scatter product output circuit 71
0 detects whether the address signal ADDR and the address signal of its own node device generated from the address generator 711 match at the timing of the first channel person in the large link packet area.

In this embodiment, as is clear from FIG. 2G, since the originating node address is assigned to the first channel A0, the address of this channel A0 and the address generator 71
1 means that the packet data sent from the own node device has gone around the loop transmission path and returned. Therefore, at this time, the received data is loaded into its own node device and the transmission is completed.

First, if the above two addresses match, Antogame)71
At the output of 4, the transmit end flip-flop 706 is set. The output Q of this 7-lip flop 706 is passed through an OR gate 721 to a busy off signal BUSYOFF.
This is added to the busy control circuit 407 of the transfer control unit 40G. The busy control circuit 407 sets the leading bit Aoo of the large link packet area to 0'' (empty display), allowing other node devices to use the large packet area.

On the other hand, the timing circuit 701 controls the link packet area A.
A timing signal is provided to turn on the termination flip-flop 707 at the timing when the address information (channels of 80 to 80 people) is sent from the transfer control unit 400 to the link control unit 600. is applied to the set terminal S and reset terminal R of. A timing signal that turns on the status flip-flop 708 at the timing when the status byte (information about channel person 1.) is sent from the transfer control unit 400 to the link control unit 600 is sent to the flip-flop 723, the AND gate 716, etc. 708, and apply it to the set terminal S and reset terminal 708.

The outputs of both the above-mentioned Aritz flops 707 and 7082) are sent to the link control section 600 as a termination gate signal TEG and a status gate signal 5TATG, respectively.

The link control section 600 receives the gate signal T as described above.
During the period when EG and 8TATG are on, it operates to input the information of channel numbers 0 to A, and A to the transmission end FIFO.

Note that creating a timing signal that turns on the flip-flops 707 and 708 for a predetermined period as described above can be easily realized by using a counter or a shift register as the timing circuits 701 and 702. I can do it.

Next, the operation when receiving packet data sent from the originating node device will be explained.

In this embodiment, the third channel person whose link packet area is large,
(See FIG. 2G) contains the destination node address, so when receiving data, it is necessary to detect a match between the address information of channel A and the address of its own node device.

To this end, the timing circuit 701 first sends a timing signal synchronized with the channel operator.

This is applied to AND gate 717.

On the other hand, the data v x sent from the transfer control unit 400
The signal ADDR and the address of its own node device are compared in a match detection circuit 710, and if both addresses match at the timing of channel A, the output passes through an AND gate 717 and is set in a receiving flip-flop 709. Applied to the terminal.

If both addresses match at the above timing, it means that the sent packet data is information addressed to the node device itself. Therefore, in order to start the reception operation, the packet control section 700 sends the output Q of the flip-flop 709 to the link control section 600 as the reception gate signal RG.

The problem here is that each node device determines whether or not it should receive packet data at the time it receives the destination node address information of the third channel, but if it is determined that it should receive the packet data, The point is that it is also necessary to capture the source node address of the first channel A and the source terminal address of the second channel A1. For this reason, it is also necessary to temporarily store information on the first and second channels A, , A,. FIF of the aforementioned transfer control unit 400
The O memory 409 is used to delay packet data by two channels, so that the first channel A
It is possible to receive data from o. That is, when the reception gate signal RG enters the link control unit 600 from the packet control unit 700, the transfer control unit 400 synchronizes with this.
Yoshi 1st channel 80 Yoshi 16th channel A. is input to the link control unit 600 as packet data PAKD, and is input to the reception PIFO 613.

On the other hand, the timing control 702 applies timing control synchronized with the channel A111 of the status device in the link packet area to the computer 722. After the receive flip-flop 709 is turned on,
AND gate 722 at the timing of channel A1s above.
opens and its output is the status select signal 8TAT8
It is sent to the transfer control unit 400 as an EL. When the transfer control unit 400 receives the status select signal 5TAT8EL, it sends status information 8TATB indicating the reception status.
is placed on the channel A1-, and the packet data is sent to the reception register 404. Above status signal 5TAT
B is another status signal 5T as seen in FIG.
It is created by delaying the AND output of ATA and the end channel signal TECH by a delay circuit 704 for a predetermined time. Also, as can be seen from FIG. 9, the status signal 5TATA is
FO613dl - Shows the status of whether or not the bar has flowed.

The above explanation has been about timing control in the case of transmitting and receiving data in the link packet area A, but since it is exactly the same in the case of transmitting and receiving data in the packet exchange area, the explanation thereof will be omitted.

Packet interface unit SOO The packet interface unit 800 is the packetizer 1
The configuration and operation of this interface section 800, which constitutes an interface between the interface section 100 and other devices and controls the transmission and reception of data in the packet exchange area D (see FIGS. 2C and 2D), are as follows: (9th
Since it is substantially the same as that of (see figure), only the different parts will be explained below.

FIG. 11 shows a frame configuration control section in the packet interface section 800, and other parts are the same as FIG. 9.

As is clear from FIG. 2C, in this embodiment, a maximum of four packet exchange areas can be set in a frame. Therefore, it is necessary to prepare four sets each of the first channel register and the end channel register. Therefore, a four-word register file memory 822 is used here. Start channel part 810 and end channel part 8
(20 have the same configuration), and the first channel register portion 810 will be explained here as a representative example.

The first channel numbers of the four packet exchange areas are initialized in the register file memory 822 in ascending order. This setting is realized by sending from the processing device a write select signal WS specifying the address of the memory 822 and data D indicating each leading channel number.

The signal from the processing device 300 is sent to the interface section 801.
The data is input to the decoder 811 via the decoder 811, decoded here, and then set in the register file memory 822. When the area is not divided up to the maximum division number of 4, the contents of the remaining registers are set to 0.

A node act signal N0DEACT sent from the channel control unit 200 is applied to the decoder 811, and reading and writing of channel register numbers are possible only when this signal is off. This node act signal N0I
) EACT is a system that operates the node device as described above.
Alternatively, it is used to perform control to stop the operation.

When reading the contents of the register file memory 822, a read select signal R8 is sent from the processing device 300, and this causes access leakage 5. 826. This access selector 826 applies the read select signal R8 to the selector 823 only when the node act signal N0DEACT is off. The read data from the memory 822 is sent to the selector 823 and the buffer gate 82.
It enters the processing device 300 via 7.

After the initial setting is completed, the no lower act signal N0DEAC
T is turned on and control of transmission and reception of packet data is started.

First, a signal CHNO representing a channel number sent from the channel control section 200 is applied to the zero detection circuit 8.25. This zero detection circuit 825 inhibits the output of the coincidence detection circuit 824 when detecting that the channel number is zero. This is because, as mentioned earlier, when no packet area is specified, the contents of the register file memory 822 are @0'', and the match detection circuit 824 outputs an output at the timing of channel number 0 in the synchronous area. This is the ninth step to prevent it from being put away.

On the other hand, the output of the zero detection circuit 825 enters the reset terminal of the access power counter 828 and resets the contents of the counter 828. However, the access counter 828 maintains a state of 0 during the synchronization region X of the frame. The contents of this access counter 828 are determined by the access selector 82.
Added to 6.

Since the node act signal N0DEACT in the on state is applied to the access selector 826, the signal ("0") input from the address counter 828 is output as is. The output of this access selector 826 is
3 and becomes a selection signal for the register file memory 822. Therefore, the .theta.th word of this register file memory 822 is read out and applied to one input of the -scattering product output circuit 824. The other input is the channel number signal CH
NO is applied. When both input signals match, the output of the match detection circuit 824 causes the leading timing circuit 802 to be activated, and the subsequent operation is the same as that of the link control section 600.

The access counter 8 is controlled by the output of the timing circuit 802.
The value of 28 is counted up and becomes .degree.l". Therefore, the first word of the register file memory 822 is read out this time, and preparations are made to detect the first channel of the second packet exchange area.

The above is a description of the detection of the first channel, but the same applies to the end channel, so the details will be omitted.

Frame generation control section 900 An example of the configuration of the frame generation control section 900 is shown in the twelfth section.
Stone explained with reference to diagram.

This frame generation control unit 900 is provided in one of the node devices (referred to as a frame control node device) of the node devices connected to the loop-shaped common transmission path, and is a transfer control unit shown in FIG. Transmitting/receiving section 400 of section 400
It is connected between the person and the transfer unit 400B.

The transmission clock oscillator 901 is the original oscillator of the transmission lock in the data communication system of the present invention, and only the frame control node device uses the output of the transmission clock oscillator 901 as the transmission clock of the transmitting/receiving section. .

First, the output pulse of the transmission clock oscillator 901 is 1
Applied to 0-base clock counter 902. The reason why a decimal clock counter is used is that in the embodiment of the present invention, one channel consists of more than 10 bits. The output of the counter 902 is further applied to a clock decoder 903, where the clock signals CLK0I CLK, [, and
Timing signals for accessing a synchronization circuit 906 and frame memory 912, which will be described later, are generated. As mentioned above, the clock signal CLK0 (, [ is the same as the clock signal CLKI, l in a normal node or device.
and between 5 and 6 bits @1° respectively
, otherwise it becomes 0'' and is locked.

On the other hand, the clock signals CLKl and 2, which are generated by the frame synchronization unit 100 based on the timing signal generated by the receiver 401 of the transfer control unit 400, and the signal RR sent from the reception register 403 are synchronized with the reception clock. It is synchronous and asynchronous with the output of the above-mentioned transmission clock oscillator 901. Therefore, this frame generation control section inputs the clock signal CLK, l[, RR multiplied signal, and performs phase matching with the transmission haze signal CLKol,y.

For this phase adjustment, the clock signal CLKI,y from the frame synchronizer 100 and the signal from the clock decoder 903 are first applied to the synchronization circuit 906, and here A signal is generated at an appropriate timing that avoids the timing and the timing before and after the rise of the transmission clock CLKol.

On the other hand, the reception signal CLK and the channel act signal CHACT are applied to an AND gate 930, and the output of this gate 930 is added to the reception channel counter 90g. When reception channel counter 908 counts a predetermined number of channels, decoder 907 decodes this and generates end channel signal ENDCH. −
The count value of the receive channel counter 908 and the content RIR of the receive register 403 are output from the synchronous pap-a-registers 909 and 91, respectively, at the output timing of the synchronous circuit 906.
It is set to 7.

Furthermore, the contents stored in the buffer register 909 and 917 are set in the receiving registers 910 and 918, respectively, at the timing of the transmitting clock CLK, l.

The clock decoder 903 receives the transmission clock CLK, l
A signal that is on from the falling edge of CLK to the falling edge of CLK, l[, and a signal that is on for 1/2 of one channel, is added to address selector 911 and write gate 914. It will be done. Accordingly, the address selector 911 selects the receiving register 910 from among the two inputs.
The selected output is applied to the address input terminal 912 of the frame memory. At the same time, the write gate 914 opens and the output of the receive register 918 enters the input data terminal of the frame memory 912. Therefore, the frame memory 912 (
C1'i, the contents of the receive register 918 are written to the address indicated by the receive channel register 910.

The frame memory 912 has 10 bits per word, and 1
It has a capacity to store information with a number of words equal to the total number of channels in a frame. In other words, it has a capacity to store all information for one frame.

During the other 172 times within one channel, from the falling edge of the transmission clock CL K,l to the falling edge of CLK,l, the output of the channel counter 904 of the two inputs of the address selector 9111/i is selected. It is selected and added to the address input chain of the frame memory 912. A transmission clock CLK01 is applied to the channel counter 904, which counts the number of transmission channels. The information of the address indicated by the value of the channel counter 909 is read from the frame memory 912, and the information of the address indicated by the value of the channel counter 909 is read.
It is set in the transmission register 913 at the rising timing of LKol.

When the count value of the channel counter 904 mentioned above reaches a predetermined value (final channel number), the value is reset by the output of the decoder 905.

On the other hand, the information read into the transmission register 913 is
Together with the output of synchronization pattern generator 915, it is applied to transmission selector 916. The transmission selector 916 transmits the output of the synchronization pattern generator 915 when the channel number 5904 indicates a synchronization region (0 channel to 3'-channel in this embodiment), and transmits the output of the synchronization pattern generator 915 when it indicates other regions. The contents of register 913 are sent. The output RR of this transmission selector 916 is sent to the transfer section of the transfer control section 400. That is, the information RR received by the reception register 403 is sent to the transfer unit after being phase-aligned with the timing of the transmission a by the above-described operation.

The frame generation control unit 900 has an abnormality monitoring function in addition to the above-mentioned phase matching function. In other words, if all the occupancy indication bits of all channels continue to indicate occupancy for a certain period of time, it is determined that there is an abnormality in the system, and the occupancy indication bits are forcibly changed to emptiness. It is.

This function is realized by components 919 to 929 of the circuit shown in FIG.

In the following explanation, the above-mentioned abnormality monitoring function will be described separately into abnormality detection in the circuit switching area and abnormality detection in the packet switching area.

Timing detection in circuit switching area B (see Figure 2B) is as follows:
This is performed in the channel control unit 200, and is performed in the circuit switching area B.
A line gate signal LING that is on during the period is sent out. This line gate signal enters the AND gate 923 together with the clock signal CLKl[, and its output is applied to the C terminal of the delay type flip-flop 919. On the other hand, the busy bit of information for l channels read into the transmission register 913, T! , ) information of the first bit is added to the D terminal of the flip-flop 919. As a result, if the busy bit is on, the flip-flop 919 is set and its output Q is applied to the AND gate 925, and when the line gate signal LING is off, the gate 925
and enters the busy counter 921. In this way, when the state in which the leading bits of all channels of an I frame remain on continues for several frames, the contents of the busy counter 921 are incremented by the number of frames. If there is even one empty channel in one frame,
The flip-flop 919 is turned off, and the busy counter 921 is reset by the output Q of the input signal. The busy counter 921 outputs an output when its count value exceeds a predetermined value, or when the all-channel busy state continues for a predetermined number of frames. This output signal is applied to an AND gate 927 together with a line gate signal LING, and the output of the AND gate 927 enters the transmission selector via an OR gate 929. This makes it possible to forcibly turn off the busy bit in the circuit switching area of the information sent from the transmission selector 916 when frames in which all channels are busy continue for a predetermined number of frames.

Next, abnormality detection in the packet switching area will be explained.

The first channel signal 8TCH of the packet exchange area enters the AND gate 924 together with the clock signal CLKl[, and its output is applied to the delay type flip-flop 920 (DC terminal). The information of the first bit of each channel is added.The flip-flop 920 is set if the busy bit is on at the timing of the first channel signal 8TCH, and its output Q becomes "1".The output Q becomes "1"
, AND gate 926 outputs the end channel signal TEC
An output is generated at the timing of H, and this is the busy counter 9.
Enter 22. If there is even one empty channel among the channels in one frame, the flip-flop 920 is reset, and the output Q of the flip-flop 920 also resets the value of the busy counter 922. When the state in which all channels are busy continues for several frames and the count value of counter 922 exceeds a predetermined value, a busy off signal is output from AND gate 928 at the timing of the first channel, and this signal is input to transmission selector 916. This allows the transmission selector 916
The busy bit of the packet exchange area sent from the packet exchange area is forcibly turned off.

In the embodiments described above, a case has been described in which one channel is constituted by a total of 10 bits (8 bits of data + data validity indicating bit + channel empty indicating bit) (hereinafter abbreviated as 10-bit system).

However, when only the following terminals are connected, 8 bits for one channel is sufficient.

(1) Voice (telephone) information 7 bits) PCM + Channel empty indicator bit (2) Data 6 bits + Data valid indicator bit + Channel empty indicator bit (3) The entire packet consists of only the 1 bit of the first channel at the beginning. This channel is used to indicate whether or not the channel is empty, and the data portion of that channel is 7 bits. From the second channel onwards, all 8 bits can be used as data.

The method of configuring one channel with 8 bits using the methods (1) to (3) is hereinafter abbreviated as the 8-bit method. FIG. 13 shows bit allocation for one channel using the 10-bit method and the 8-bit method. In the figure, B indicates a channel empty indicator bit, A indicates a data valid indicator bit, and v indicates an unused bit.

The methods described so far in this embodiment can be applied without any essential changes even if an 8-bit system is adopted.

In the following, a switching means for realizing switching between the 1,0-bit method and the 8-bit method using one type of hardware in this embodiment will be explained.

Whether to adopt a 10-bit system or an 8-bit system is determined depending on what kind of terminals are connected to the network system shown in FIG. When the system is started up, either method is determined by a switch or a signal from the processing device 300.

To realize the above-mentioned switching between the 10-bit system and the 8-bit system, the frame synchronization section shown in FIG. 4 is changed as follows.

Synchronous bang generator 1o1, coincidence circuit 1o2, synchronous counter 106, decoder 1o7, clock counter 114,
A new 8-pit decoder 115 is provided in addition to the existing 10-bit decoder 115, and switching is performed using an 8-bit 210-pit switching signal (hereinafter abbreviated as signal 0CTET). The signal 0CTET is obtained from the switch or processor 300 at system start-up. Decoder 11
In the case of the 8-bit system, the output clock No. 1g CLKII of No. 5 is a signal that becomes 1 when the value of the clock counter 114 becomes 4.5.

Alternatively, by adopting a circuit system that can be used in both the 8-bit system and the 10-bit system, for example, the synchronous counter 106 and the clock counter 114 are each made into one, and the ON/OFF of the signal 0CTET is changed to 8 bits/10 bits. , it is also possible to allow any of the bits to perform the operations.

Furthermore, the entire circuit shown in FIG. 4 may be provided separately for the 8-bit system.

FIG. 14 shows an embodiment of a transfer control section to which an 8-bit/10-bit switching function is added.

The operation in the case of the 8-bit system will be explained below.

Of the 98-bit data taken into the reception register 403 from the shift register 402 at the timing of the clock signal CLKI, the empty/occupied indicator (PI) AO2 is input to the selector 1400 together with the empty/occupied indicator (PI) AOO in the 10-bit system. If signal 0CTET is on, bit AO2 is AOO
' is output. In both the 8-bit system and the 10-bit system, bit A00' is the vacancy indicating bit for that channel.

a signal BUSYON given to the busy control circuit 407;
The vacancy indicator bit A0 is reset or reset by BU8YOFF, or is not activated at all.
0 is written into the transmission register 412 at the timing of clock 1st signal CLKI, and then into the selector 1401.
It is entered together with the vacancy indicator bit AO2 in the 8-bit system. The selector 1401 is set to bit (0) when the signal 0CTET is on and not on the second or subsequent channels of the packet.
O" is output as AO2". As a signal indicating that this packet is not the second channel or later, an inverted version of the signal CHN2 representing the 12th channel obtained from the head timing circuit 701 in FIG. 10 is used. When the signal 0CTET is off, that is, in the 10-bit system,
From the second channel onward of the packet in the bit method,
Bit AO2" is output as is as AO2". 8
K for bit method, bit A for packet 2nd channel and beyond
The reason why O2"? is passed as is as AO2M is to secure 8 bits of data from the second channel onwards.

In the end, I added two selectors 1400 and 1401 to 8
Since K is used in the bit mode, the processing of busy control, transmission/reception data, etc. in the transfer control section can be the same regardless of the difference in 8-bit/10-bit format.

The 8-pin toy number with the vacancy information pin) AO2' on it passes through the check selector 414 and is taken into the transmission register 413 at the timing of the clock signal CLKm. In the case of an 8-bit system, 10 bits are prepared for the 10-bit system.
A serial output is output from the 8th bit terminal in the middle of the bit shift register 413. Selector 1402 is signal 0C
When TET is on, the 8th bit output of the transmission shift register 413 is selected and becomes the output of the selector 1402.
It is sent to transmitter 418 in FIG. When the signal 0CTET is off, the 10th bit output is selected and similarly sent to transmitter 4.
Sent to 18th.

FIG. 15 shows an example of the configuration of a part of a terminal control section having an 8-bit/10-bit switching function, and shows the part added to the main figure 8A.

First, when transmitting data from a terminal device, selector 1
500 is the signal 8 in FIG. 8A when the signal QCTET is on.
It functions to output the output signal 5DO1 from the flip 70 knob 516 set by REQ as a data valid display signal SDO3' in the 8-bit system. With this selector 1500, if the terminal device outputs the data valid indication signal as the signal 8REQ regardless of whether it is 8 bits or 710 bits, the data valid indication signal is output at the bit position corresponding to the system being used at that time.

Next, when the terminal device receives data, the reception selector 5
8 of the signals RD or IND selected by 20
The data validity indicating bit RDO3 in the bit system is outputted by the selector 1501 as a p)RDOI'. As a result, the terminal device can know the validity of the data by detecting the RDOI' regardless of the 8-bit/10-bit format.

After all, by using the selectors 1500 and 1501, the terminal device can input and output the data validity indicator No. 1g to the same bit position in both 8-bit and 10-bit cases.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram for explaining the overall system configuration of the system of the present invention, FIG. 2A, FIG. 2C, FIG. 2D,
Figure iE, Figure 2X, Figure 2G, Figure 2H, and Figure 25 are schematic diagrams for explaining the frame structure in the method of the present invention, and the second construction diagram explains the operation of the method of the present invention during the circuit switching function. 3A and 3B are configuration diagrams showing an embodiment of the node device in the system of the present invention, and FIG. 4 is a configuration diagram showing an embodiment of the frame synchronization section in the system of the invention, 5A and 5B are block diagrams showing one embodiment of the channel control section in the method of the present invention, FIG. 6 is a block diagram showing an embodiment of the processing unit section in the present invention, and FIG. Configuration diagram showing one embodiment of the transfer control unit, No. 8
Fig. A, Fig. 8B, Fig. 8C, and Fig. 8D are block diagrams showing an embodiment of the terminal control section in the method of the present invention, and Fig. 9 is a block diagram showing an embodiment of the link control section in the method of the present invention. ,
FIG. 10 is a configuration diagram showing an embodiment of the packet control section in the method of the present invention, FIG. 11 is a configuration diagram showing an embodiment of the packet control section in the method of the present invention, and FIG. Figures 1 to 15 show that in the method of the present invention, 10
Figure 13 is an explanatory diagram showing an example of channel bit allocation in the 10-bit and 8-bit systems, and Figure 14 is a transfer diagram. FIG. 15 is a block diagram showing an embodiment of the control section. FIG. 15 is a block diagram showing an embodiment of the terminal control section.
IJa unit, 300...processing unit★, 400...transfer control unit. 500 one terminal control unit, 600... link control unit. 700... Packet control unit, 800... Packet interface unit, 900... Frame generation control unit. 1000...Terminal device◇ '8 IJ area ■yo■

Claims (1)

[Claims] Data that connects a plurality of node devices through a common loop-shaped transmission path, repeatedly transmits information on a large number of channels at a fixed period over the skeleton transmission path, and sends and receives channel information between terminal devices connected to the node devices. In a communication system, at least the first channel number of each of a group of channels for packet communication and circuit switching out of a large number of channels is stored in a storage means, and the channel number of information currently being received is stored in the storage means. A matching channel number is detected, and when a match is detected, a circuit that performs packet communication control according to the matched channel number and activates five circuits or a circuit that performs circuit switching control. Data communication method.