JPS5821941A - Data communication system - Google Patents

Abstract

PURPOSE:To perform the communication of data in time division between terminal devices, by adding a connection controlling code showing the transmission request and the discrimination of the end request of a node device at the remote side and the circuit exchanging code showing the channel number to the region of the connection controlling information. CONSTITUTION:Plural communicaton node devices 2 are connected to a common signal transmission line 1. At least one of these devices 2 produces repetitively plural channels in a certain period to transmit them. Each device 2 performs the communication of data through a channel. Then plural continuous channels are used as the regions to transmit the connection controlling information. The information region has a frame constitution which can use both a circuit exchange and a packet exchange together and includes a synchronizing region X, the connection control code showing the discrimination between the transmission request and the end request of the address data of the device 2 and the circuit exchange code showing the channel number.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data communication system, and particularly to a system in which a large number of terminal devices are connected to a common transmission path and data is transmitted and received between the terminals in a time-division manner.

In recent years, office automation (hereinafter abbreviated as ON), which aims to improve office productivity, has been attracting attention. In the past, OA mainly used batch processing to execute ual-specific and routine tasks, but in the future, it will be possible to perform tasks that involve so-called data processing, such as file editing, single-child mail, document editing, etc. The automation of advanced office work is increasingly being requested.

On the other hand, with the rapid development of optical communication technology based on optical fibers and light-emitting diodes, high-speed and low-cost digital transmission is becoming possible with CRR, which can be applied to familiar networks.
potential is increasing.

Based on this technical background, facsimile, <tX
Attempts are being made to realize a network system in which word processors, personal computers, and various data terminals (sr) are connected to a common signal transmission path and data can be freely communicated between the terminals. .

However, in order to realize such a network, several problems such as those described below must be solved.

The first problem is that many types of terminal devices are connected to a common transmission path, and the speeds of data handled by each terminal device are drastically different. That is, there are a wide variety of existing terminal devices, ranging from those that handle extremely low-speed data of about 50 bps to those that handle high-speed data of 1 Mbps or more.

Also, in recent telephone exchange technology, 0.3 ~ & 4 KH
A time-sharing electronic switching system has been put into practical use that converts analog signals in the z voice band into 8-bit (7-bit systems are also available) digital information at 8 KHz (125 μS cycle) and exchanges at the digital and digital information level. But in this case 6
It is necessary to cope with a data rate of 4Kbl)S (8 bits x 8KHffi).

Achieving an effective data communication system that can handle such a wide variety of data speeds is an extremely important issue in this type of network.

The second problem is that among the current terminal devices, there are some that perform data communication using the circular exchange method and others that use the nokukerato exchange method, and each switching network is independent. The point of existence is Ruru.

Therefore, in order to connect various types of terminal devices i configured to perform data communication using different exchange methods to a common transmission path and to communicate between the terminals, it is necessary to use both conversion methods. In either case, it is necessary to be able to perform all data communications.

An object of the present invention is to provide a data communication system that meets the above requirements.

First, the overall system configuration of the method of the present invention will be explained with reference to FIG.

In the figure, reference numeral 1 denotes a loop-shaped common transmission line, for example, an original fiber is used. 2 is a node device connected to this transmission path, the details of which will be described later. This node device has 1 route, for example 32 to 6411i! At least 11 of them have the function of generating a frame consisting of a synchronization signal area and an information channel area. 3 is a terminal device, such as a facsimile, a word glossary, a personal computer, a minicomputer, a spoken language, and various data terminal devices.

This terminal device corresponds to one node device, for example, 8 to 32
11iA is connected. Therefore, in the above example, terminals 256+ia+ to 20481161 are connected to the l-loop transmission line. Of course, the number of these devices is merely an example, and it goes without saying that the system of the present invention is not limited thereto.

Next, the frame structure in the time division multiplex communication system of the present invention will be explained.

In the method of the present invention, bit string information is transmitted through the above-mentioned loop-shaped transmission path, and a group of consecutive bits with a fixed number of bits is referred to as a channel, and a group with a fixed number of consecutive bits is referred to as a channel. It is called a frame. This frame is generated at a constant repetition period if the transmission rate [- is constant.

A frame in the system of the present invention is composed of a synchronization area X and an information communication area Y, as shown in FIG. 2A. For example, four channels are allocated as the synchronization area X, and the remaining channels are used as the information communication area. In this embodiment, the l channel consists of 10 bits. The frame repetition period is chosen to be 125 μS (8 KHz) in this example.

Therefore, if the data speed is k 10 Mbps, the number of channels in one frame is 125, and at 32 Mbps, it is 400 channels.

A 10-bit bit pattern for synchronization is inserted into the valley channel of the same iJA area. It is desirable that this bit pattern be a bit pattern that appears in the information communication area Y with a small number of reservations.

The information communication area Y has different frame configurations depending on whether the line switching function is used or the packet switching function is used.

Figure 2B is the bottom of the frame groove during line switching function, Figure 2C is
Figure 2D shows the frame structure during packet switching function, Figure 2E
The figure shows a frame configuration when both types coexist. Each frame structure will be explained in detail below.

, 1gI line father exchange frame structure As is clear from Fig. 2B, the frame during line exchange is as follows:
It consists of a synchronization chain acid X1 connection control packet area person and a 1gl exchange reconnaissance area B.

The beginning of the frame is a synchronization area X that transmits a fixed synchronization character (one character is a 10-bit bit pattern) for identifying the beginning of the frame, and is composed of a plurality of channels. There are two next areas, a connection control packet control area A and a circuit switching area B, but these can be placed in either order as long as they are consecutive areas. Further, areas other than the above three areas may be included in the entire frame.

The connection control packet area contains the addresses of the destination node device and terminal device to which data should be sent, the addresses of the originating node device and terminal device, and the channel number in circuit switching area B used for data transmission and reception, etc. It is used to transmit so-called connection control information in the form of packets.

This connection control packet area A is composed of 16 channels A0 to AIs as illustrated in FIG. 2F. Each channel is formed from lO bits, with the first bit Ao
o is used to indicate whether the connection control packet area A is empty or blocked. In other words, the frame repetition period is set to 125 μs (
8KHz), different connection information of up to 8Kf/sec can be transmitted as connection control information.
If this connection control packet area A' is used, A, pict t-"i" is not used, "0°
By setting , the empty status of this area is displayed. Similarly, this connection control packet area is only used when setting and canceling the settings of channels for data transfer between terminals, and is used when data is actually sent and received. Only circuit-switched channels are used during the period.

Connection control packet area 2nd bit A of the person's channel
ot is preliminarily provided in this embodiment and is not directly related to the present invention, so its explanation will be omitted.

The 8 bits A62 to A09 of each channel are filled with data information. The s2G diagram shows an example of the relationship between the valley channels A, -'-A, etc. of the connection control packet area A and the information transmitted via the respective channels.

Channel AO is used to transmit address information of a node device that transmits all data.

is used to specify one of the terminals connected to that node device. A is used to transmit information representing the address of the destination node device to which the data is to be sent, t'', and the address of the data destination terminal connected to the node device 7. Channel A4 is used to transmit the connection control code that indicates the distinction between data transmission ['request and termination request'ft'.Channel person is the tgI+1!exchange area BP'3 used for data communication.
used for transmitting information representing a specific channel number. Channel members 6 to 6A and 1 are used for transmitting various parameters, but since they are not directly related to this invention, their explanation will be omitted. When communicating using multiple channels at the same time in circuit switching area B, go to this channel 〇~AI'f
It can also be used to display the channel number used. Channel A, 4 is used for transmission of check codes. For example, transmitting the result of certain arithmetic processing on the data of channel persons 6 to A13 as a check code,
On the receiving side, the same arithmetic processing is performed on the same data,
Check the accuracy of the sent data. Channel Al
l is used for transmitting status information. For example, when the data destination node 1tlt receives the data, it carries predetermined information on this channel Al11 and sends it back to the source. This allows the source node device to confirm data delivery.

On the other hand, the circuit switching area B is the connection control packet area A.
It is used to exchange information between multiple terminal devices through the specified channel.

This circuit switching area B has an arbitrary number of channels B Oa81
, B*...B. dX2H
As shown in the figure, the valley channel consists of 10 bits, and the lower 8 bits B (11 to B61 are allocated for data transmission. The first bit Boo indicates whether the channel is empty or has already been used. It is used as an empty/occupied indicator bit to indicate whether it is being used.

2nd bit B. 1 is used to indicate whether the 8-bit data of that channel is valid data or invalid data. The data rate can be adjusted by the M enable/disable bit Boi of this information, and the reason for this will be briefly explained below.

As mentioned above, in the method of the present invention, the period of one frame is selected to be, for example, 125 μ8 (8 KHz), so the data that can be transmitted in one second on the l channel is 8 pins x 8 = 64 bits. In the present invention, this channel is used as a unit, and even if a terminal handles extremely low-speed data, one channel is assigned to one terminal when a transmission request is received from the terminal. Therefore, if the data rate of the terminal is e.g.
In the case of an ultra-low speed of about 0 bps, even if one channel is allocated, data to be transmitted is generated only at the opening of about once every 64 to 150 frames. In short, even if a frame is repeatedly generated eight times per second, it is sufficient to use the channel for that frame once every 1000 frames, which means that extremely low-speed data can be transmitted. Therefore, if the number of channels is increased to one, frames with data on that channel and frames with no data at all will be repeatedly generated. B. 1
The bits are displayed as valid, for example, by setting all the bits to 0, and when there is no data, the set bits are displayed as invalid, eg, set to 0. Therefore B. 1 bit °1
The period of `` represents the entire data speed. In other words, by using 80g bits, each node device can freely adjust and transmit and receive data at different speeds.

On the other hand, when transmitting high-speed data of 64 Kbps or more, this can be easily handled by allocating multiple channels. For example, a 1i channel may be assigned to a terminal that handles high-speed data of 1 Mbps.

Next, the data communication procedure using the circuit switching system will be explained with reference to the second engineering drawing.

In response to a transmission request from a terminal, the node device creates a destination address from the logical address (eg, telephone number) of the destination terminal. The address of each node device is determined by a known method such as fixed assignment in advance.

Next, in channel Bo-Bm of circuit switching area B, the blockage indication bit (BOG, Bl.5B2G...)
is searched for a channel with an empty display (for example, 0°), and that channel is set as the base display (for example, 1°). Then, based on the connection control packet format as shown in Figure 2G,
Create a connection control package If. In this case, channel A4
A code indicating a connection request is stored in the area corresponding to %AI, and data representing a hunted channel number is stored in the area corresponding to %AI.

Once the connection control packet has been created, the empty connection control packet area A is found and the packet (hereinafter referred to as the first packet) is transmitted. As described above, the idle status of the area person can be identified by looking at the idle status indicator bit Aook of the first channel A0 of the area person in the connection control packet.

The above connection control packet is received by the receiving node, which interprets the packet information and first checks whether or not the terminal that requested the connection is in use. , data) is set in the control unit of the terminal of the node device. By setting this used channel number, the terminal will receive data sent through this channel from now on. after that,
Response packet information indicating that channel setting processing has been completed is created at the destination node device, and this packet (referred to as a second packet) is sent to the transmitting node device.

After confirming the delivery of the first packet, the transmitting node device waits to receive the second packet of response information. After receiving the second packet, a start instruction is issued to the transmitting terminal at a certain timing.

On the other hand, after confirming the delivery of the second packet representing the response information, the rejecting node device immediately issues a start instruction to the terminal. At this point, the same used channel number has already been set in the terminal control units of the sending and receiving side node devices. This is done continuously through a designated channel in exchange area B.

When a certain frame is being generated, if the data to be transmitted has not yet been generated by the terminal, the validity indicator bit (for example, B/t) in the channel can be set to, for example, °0°, so that the receiving side can For node devices,
Tells that the data in that frame is invalid. As described above, it is possible to automatically adjust the data by using the validity indicating bit.

When a data transmission termination request is issued from the sending 1g side terminal,
In the same manner as described above, packet information for the termination request 1kfi is created based on the format shown in FIG. 2G. This packet message is transmitted to the node device on the receiving side. Both node devices send a stop instruction signal to the terminal and release the channel in use. In other words, the sending side sets the first bit of the channel in use to °O", returns it to the empty state,
Receiving Side The control described above is executed based on instructions from a processing device within a node device, which will be described later.

Frame structure for packet exchange The frame for packet exchange consists of a synchronization area X and a packet exchange area, as shown in FIGS. 2C and 2D.

The synchronization area X is used to identify the beginning of the frame,
This is similar to the case of frames during circuit switching.

Packet exchange area DFi, the entire information communication area may be made into one packet exchange area as shown in Fig. 2D, or the 2C
As shown in the figure, it can also be used by dividing into a plurality of packet switching areas.

As shown in Fig. 25, each packet area has multiple channels (Do # DI m...D), and the information to be transmitted on each channel is allocated in advance as shown in the figure. . Of course, although FIG. 2J shows an example, other methods can be used for the packet format and address assignment.

In this embodiment, the side that transmits the packet, that is, the originating address information, is transmitted through the first two channels Do and D+k, and the side that receives the packet, that is, the destination address information, is transmitted through the next two channels Dt and Dsk. be done. The addresses of the node devices are assigned to the channels Do and Ds, and the addresses of the terminal devices are assigned to the channels Dr-Ds.

゛Channel D, subsequent consecutive channels D4 to D L-
t is allocated for data transmission. The channel Dj-s immediately before the final channel is the channel D0 to Dt-*
The last byte Dt allocated for the check code of information
is assigned for status.

Similarly, each channel is composed of 10 bits as in the case of Fig. 2F, and only the most significant bit of the first channel Do is used to indicate the vacancy in the packet exchange area, and the lower 8 bits of the valley channel are used for information. Reveal the content.

Next, the operation of data communication using the packet switching method will be explained.

The sender notes according to the sending request from the sending terminal.

It waits for an empty packet area to be received, sets the area as occupied, and sends packet information to the transmission path.

Each node device checks the destination address Dt in the packet information, and if it does not match its own node address,
Transfer it as is to another node device. When the destination address of channel D matches its own node address, that node device starts receiving operations.

The receiving node device transmits the packet information to the receiving terminal connected to it, and also puts status information indicating that it has been received on the final channel DL of the node information, and transmits it to the next node device along with other information. Transmit sequentially.

When the packet information travels through the loop-shaped transmission path and returns to the sending node device, this sending note is determined to be the sending address of channel Do as its own note.

Since it matches the address, the kerato information of the circled area is taken in. At the same time, the vacancy indicating bit D0° of the kerat area is set to be empty, and the transmission is terminated.

The sending node device can check the normality of the transmission by checking the status of the incoming packet information after the round.

Above, we have described the frame structure during circuit switching and packet switching according to the present invention, and the respective 100 data communication methods. However, in the present invention, it is also possible to perform data communication by appropriately switching between the two switching methods. Also, is it possible to simultaneously create both a circuit switching area and a packet switching area in one frame, and use both switching methods? Data communication can also be performed in a mixed manner.

FIG. 2E shows a frame configuration when circuit switching functions and packet switching functions are simultaneously implemented.

The bit formats of the synchronization area X, connection control area A, line switching area B, and packet switching area of this frame are the same as those shown in FIGS. 2B to 2D, and therefore their explanation will be omitted. In FIG. 2E, the order of the valley regions A, B, and D may be arbitrary, and the packet conversion region may be divided into a plurality of regions.

FIG. 3A shows an example of the overall configuration of a normal node device for realizing the data communication system according to the present invention. 100 is a frame synchronization unit, 200 is a channel control unit, 300 is a processing device, 400 is a transfer control unit, 500 is a terminal control unit, 6
00 is a link control unit, 700 is a packet control unit, 800
Hanoku Kerato interface section, 1000 is a terminal device,
1100 is a packetizer, 1200 is an optical loop transmission line, and 1300 is a terminal bus.

In such a configuration, the frame synchronization unit 100:
The synchronization area at the beginning of the frame is identified from the received signal input from the loop transmission path 1200, and a clock timing signal indicating the beginning of the frame and the beginning of each channel of the frame is created and sent to the music part.

The channel control unit 200 identifies the channel number in the frame, instructs the line switching area of the frame, controls the operation of the node, displays the status, etc.

The processing device 1300 is a section that performs storage program control using a microcomputer, memory, etc., and performs program control such as connection control processing and initial setting processing.

The transfer control unit 400 receives the input signal from the loop transmission path 1200, performs a process of exchanging the transmitted and received signals with a predetermined terminal device 1000, etc., and then performs loop transmission w! 112
Create a transmission signal to 00.

Terminal side (iQItfis 500 f'i, the side that controlled transmission and reception with the corresponding terminal device 1000, transfer control unit 4
Controls the transmission and reception of data to and from 00. For this purpose, all channel numbers within the frame to be transferred are stored.

The link control unit 600 performs line switching connection control and packet transmission/reception processing. The packet control unit 700 has basic functions necessary for transmitting and receiving packets, and performs address matching detection, searching for empty channels, creating transmission and reception timing, etc.

In the packet interface unit 800, control signals with the packetization device 1100 when having a packet exchange area,
Controls transmitted and received data, stores packet areas, etc.

The terminal bus 1300 includes these devices 51100-so.

It connects between 0 and 0 and serves to control mutual transmission and reception.

In such a configuration, when a received signal comes in from the loop transmission path 1200, the transfer fee 419400 receives and demodulates it, and the frame synchronization unit 100 identifies the synchronization signal at the beginning of the frame from the received signal, and Creates a lock timing for internal channel reception and sends it to other parts.

The channel control section 200 creates a channel number signal according to the timing from the frame synchronization section 100 and sends it to the terminal bus 1300.
The link controller 600 determines whether or not it is within the circuit switching area from the No. g signal and sends it to the same terminal (S 1300).The link controller 600 also uses the channel number signal from the channel controller 200 to control the connection of the receiving channel. ) Determine whether it is the beginning or end of the Kukerato area and set the Nokuket fl
lJI1 Department 700.

Now, the processing device 1300 detects that there is a transmission request from a certain terminal device 1000, and issues a hunt request to the terminal side #550O. The terminal control unit 500 uses the empty/busy indication bit of each channel fetched from the transfer control unit 400 and the signal indicating that the channel is within the circuit switching area from the channel control unit 200 to determine the empty indication in the circuit switching area. When a channel is searched and found, the channel number signal at that time is fetched and stored in the terminal control unit 500, and a signal is sent to the transfer control unit 400 to change the empty indication bit of the corresponding channel to the main display. It is sent to the loop transmission line 1200.

In the processing device [30G, the destination address is sent to the terminal device 100
0 or a predetermined fixed address, and creates the destination address, own address, and empty channel number received from the terminal control unit 500, and creates a connection request code. etc. are edited based on the connection control packet format to create a connection control packet and send it to the link control unit 600. At the same time, when the processing device 300 sends a transmission request to the link control unit 600, the packet system ##700 checks the empty indication bit of the first channel in the connection control packet area, and if it is empty, the transfer control unit 400 A signal is sent to the loose transmission path 1200 to set the empty/busy indication bit of the leading channel to no indication. At the same time, a signal is sent to the link control unit 600, and the already set ffG control packet i transfer control unit 400 is sent to the loose transmission path 1200 as packet transmission information.

The connection control packet sent to the loop transmission path 1200 in this manner is received by the valley node device. The operation is such that data in the cough area is sent from the transfer control unit 400 to the packet control unit 700, where the destination address and the own address are -fltfnicked, and if a match is detected,
Link control part 60G? The link control unit 600 receives the received connection control packet data, and the processing unit 300 reads it.

The processing device 300 interprets the contents of the read connection control packet, checks whether the terminal device 1000 to which a connection request has been made is not in use, and if it is not in use, the transmitting node device t't”ffl Reply information with destination address @
, and sends it to the link control unit 600 along with the transmission request.

Thereafter, in the same way as the sending node device described above, find an empty connection control packet area, change the empty indication bit to this indication, insert the created connection control packet into that area, and start the packet transmission M1200. Output -rfc, 1A11 [300] Sets the sent empty channel number in the terminal device section 500 of the terminal device 1000 to which the connection is requested.

On the other hand, in the sending node device, when the 1M packet sent by itself returns after going around the loop transmission path 1200, the sending address in the data received by the transfer control unit 400 becomes the own address. Must match f Packet control unit 7
A determination is made at 0G, and a signal is sent to the transfer control unit 40G to set the empty indication bit 1 of the first channel in the connection control packet area to empty indication.

On the other hand, when the transmitting node device receives a connection control packet indicating the current capacity sent from the receiving node device, the packet control unit 700 detects that the destination address matches its own address, and Similarly, the connection control packet is sent to the processing device 1 via the all link control unit 600.
Import into 300.

The processing unit 300 acknowledges the response information and sends it to the terminal device 1.
A start command is generated at 000. In addition, when the receiving node device learns that the information it transmitted has made a round through the loop transmission path 1200, it displays the empty indication bit of the first channel in the connection control packet area as empty, as described above. Then, issue a start command to 11000.

In the transmitting side node device, based on a start command from the processing device [300], transmission data is sent from the terminal device 1000 to the terminal control unit 500.

The terminal control unit 500 detects whether the set channel number matches the channel number signal from the channel control unit 200, and if a match is detected, the terminal device 100
The transmission data from 0 is sent to the transfer control unit 400, and the transmission data is inserted into the corresponding channel and sent to the loop transmission path 1200.

On the other hand, in the receiving side node device, the transmitted data is received by the transfer control unit 400 and sent to the terminal control unit 500.

The terminal control section 500 determines whether the set channel number matches the channel number signal from the channel control section 200, and if a - print is detected, the received data is sent to the terminal device d1000 including money and 9. Note that data can be similarly transmitted from the receiving node device to the transmitting node device at the same time using the same channel.

Note that it is also possible to perform transmission from the receiving side node device to the transmitting side node device using different channels.

Next, in the sending node device, when a transmission end request is issued from the terminal control 1000 to the processing device 300, the processing bag m3
00 creates a connection control packet that instructs disconnection,
In the same way as described above, it is sent to the receiving side node device and instructs the terminal device 1000 to stop.

At the same time, in the sending node device, the processing device 3
00 to the terminal control unit 500, and when the channel number signal matches the number of the occupied channel, it sends a signal to the transfer control unit 400, clears the empty display focus of that channel, Release the channel.

Note that when the set channel number matches the channel number signal, the terminal control unit 500 transmits data with the validity indicator bit set to be invalid if no data has been received from the terminal device 1000 yet. , it is possible to inform the other party that the data is invalid, and to cope with any processing speed on the terminal device 10oO side.

Further, in the transfer control unit 400, the link control unit 60
A function of creating a check code by performing a predetermined operation on the data of the 1st to 14th channels of the connection control packet sent from 0 and inserting it into the 15th channel of the coated packet and transmitting it; A predetermined operation is performed on the data of the 1st to 15th channels of the received connection control packet to check the integrity of the received data, and the refined data is inserted into the 16th channel as status information and transferred. It has the following functions.

On the other hand, when performing packet exchange, the packet interface unit 8oo of the sending node device detects the leading channel of the packet exchange area and sends the packet to the packet control unit 70.
Send to 0. In the packet control unit 700, the transfer control unit 40
If the empty channel indication bit e is checked and the empty channel is displayed, a signal is sent to the transfer control unit 400, and the empty/occupied indication focus of the first channel is set to ``occupied''. At the same time, the packet information created by the packetization device 110G and set in the packet interface 5soo is sent to the transfer control unit 40.
0 to the loop transmission line 1200. In the receiving side node device, the first channel of the packet is detected by the all-packet interface section 1100 based on the channel number signal, and the packet control section 700 is activated. Packet control unit 700
Then, it detects that the illuminated address of the packet and data sent from the transfer control unit 400 is its own address, and notifies the packet interface unit 1100 of the transfer. The interface 1110G receives and receives the packed packet data and sends it to the processing bag 1130G. When the packet interface section 800 detects the end channel of the packet exchange area, it performs the end operation.

In each node device, when the packet data sent by itself goes around the loop transmission path 1200t and returns again, the packet control unit 700 similarly receives the packet data from the transfer control unit 9, and the sending address is set to the own address. If they match, the transfer control unit 40
0, the header of the corresponding packet is set to empty indicating bit, and the packet area is released.

FIG. 3B shows an example of the overall configuration of a node device that has a frame generation function in order to realize the data communication system according to the present invention. is the transmitting/receiving section 400A and the transfer section 4
00B, and a frame generation control unit 900 is provided between them.

This node device plays the role of the above-mentioned normal node device, and also plays the role of generating frames with a constant cycle that circulate around the loop transmission path 1200.

In the frame generation control $900, the entire frame information that has gone through the loop is passed through the transmitting/receiving section 400A of the frame information transfer control section 400.The memory in the frame generation control section 900 stores the number of frames. Based on the clock, a synchronous area pattern is created first, and then the memory is sequentially read out to form a frame. The nuclear information is sent to the transfer unit 400B of the transfer control unit. After that, the same steps as the others are performed, and the information to the next node is sent via the 400 transmitting/receiving sections of the transfer control section.

Furthermore, the frame generation side g4 unit 900 has a function of monitoring abnormalities. In other words, in each of the circular crossing area and the packet switching area, if it is detected that all the vacancy indication bits of the valley channel indicate the base indication for a certain number of consecutive times, the vacancy of each channel is The function is to force the blank display to display if the display is empty.

The other operations are the same as those shown in FIG. 3A, so their explanation will be omitted.

Hereinafter, specific examples of the configuration of each part shown in FIGS. 3A and 8 will be described in detail.

(1) Frame synchronization unit 100 FIG. 4 shows an example of a specific configuration of the frame synchronization unit 100.

In the figure, signals TIM and 8ROUT are signals that are enabled by the receiver and shift register as detailed in FIG. From the loop transmission line 1200 to the transfer control unit 40
The receiver demodulates the serial reception information sent to 0, and extracts the timing of the bit interval of the reception information to generate a timing signal TI with a duty of 50.
M is created. The serial reception information of this timing signal TIM is sequentially stored in a shift register. The parallel output of the shift register is the signal 8BOUT.

In the frame synchronization section 100, a synchronization pattern generator 101
The matching circuit 102 compares the synchronization pattern in the frame synchronization area, which is set in is set through the gate 104 and the corresponding frigflock 103t.

By setting the free lag flop 103, the synchronization counter 106 is operated through the bundle gate 105, and the subsequent counting of the number of received bits is started.

The decoder 107 detects that the value of the synchronization counter 106 corresponds to the number of bits per channel (10 in this embodiment).
When detected by the AND gate 108, the transfer control unit 4
It is checked again whether the contents 5ROUT of the 0G shift register match the synchronization pattern, and if they do not match, the match flip-flop 103 and synchronization counter 106 are reset through the OR gate 109 by the output of the AND gate 10B. Then, each time one bit is received, a match between the contents of the shift register and the synchronization pattern is searched again.

If the contents of the shift register and the synchronization pattern continue to match, the match flip frog 103 remains set, and at that time, the signal from the synchronization counter 106 goes to the synchronization character color/reference 110 at full height, and the synchronization character color/reference signal 110t is output.
Add -+1. In this way, when channels matching the synchronization pattern are received consecutively, the synchronization character counter 110
The number of characters is counted. As mentioned above, if the number of channels in the synchronization area is 4, the value of the counter 110 becomes 3, and the content of the synchronization counter 106 becomes the value, for example 3, after being detected by the next synchronization character of the fourth channel. The decoders 111 and 107 detect that a Y attack has been obtained in four consecutive channels, and generate an output in the AND gate 112 at the timing of the timing signal TIM. 'i set indicates that synchronization has been established, and with the way the set is output, the match flip frog 103, Pj4 counter 1o6, and synchronization character counter 1 are input through the 4-7 gate 109
10i all reset and AND gate 104
Prohibit the output of In addition, the coincidence detection operation is completely stopped to prevent the contents of subsequent information channels from being mistakenly regarded as synchronization channels.

On the other hand, the clock counter 114 is driven by the reception timing signal Txytvc and is used to generate a clock that indicates the timing at which the shift register output 5ROUT indicates information for -channels. Therefore, when the AND gate l12 detects synchronization OK, the contents of the clock counter 114 are forcibly transferred to the synchronization counter 1.
06, that is, 3, and the value of the synchronization counter 106,
Phase matching is performed by making the values of the clock counters 114 the same. On the other hand, the output of the clock counter 114 is input to the decoder 115, and when the value of the clock counter 114 is 0.1, the clock signal CL is sent from the decoder 115.
KIt- is output, and when the value of the clock counter 115 is 5.6, a clock signal CLKII is output. Furthermore, for special purposes, a clock signal CLKm is output when the value of the clock counter 115 is 4. This CLK
1, the output of the shift register is transferred to the receiving register as described below. Subsequent processing becomes possible in units of information for each channel. On the other hand, since the clock counter 114 is always operating even when the clocks CLKI to (2) are out of synchronization, the clock counter 114 is always output and does not interrupt the processing of other parts of the C1 node device.

When the synchronization flip-frog 113 is fully set, the frame synchronization section 100 sends a channel act signal CHACT to the channel control section 200, and the channel control section 200
Activates the channel color/res in the clock signal CLKI.
Counting starts at the timing of [, and the clock signal CLKI
The number of IOs, that is, the number of channels within the frame (excluding the number of channels within the synchronization area) is counted. When the contents of the channel counter reach a number corresponding to the number of channels in the information communication area (Y in FIG. 2A) within the frame, the decoder sends an end channel signal END CH4-frame synchronization unit 100.
The synchronization clip block 113 is reset through the AND gate 116t-. As a result, the same A1 detection operation as described above is started by the transfer control unit 40.
Every time 1 bit is received in the 0 shift register, a check is made again to see if it is a synchronous character pattern. Thereby, it is checked whether the synchronization area of the next frame is normally received following the end of the previous frame.

A synchronization pattern may not be detected in the synchronization area of the next frame due to missing bits in the transmission information on the loop transmission path 1200, bit leakage due to noise, etc. In this case, since the channel information in the frame is not recognized correctly, it is necessary to immediately resynchronize and take some other action, such as stopping the processing in the meantime. Must.

This synchronization shift is detected at the timing when the value of the clock counter 114 becomes 0 after the synchronization flip-flop 113 is reset by the end channel signal END CH indicating the end of the previous frame. If a match with the synchronization pattern is not detected at the timing when all the information of the first synchronization channel of the synchronization area of An output is generated from gate 117 and sets an out-of-sync flip-flop 118. Out of sync clip flock 11
The out-of-synchronization signal ST 0UTe, which is the set output of 8, is sent to the channel control section 200. When the clip flock 118 is synchronized, the clip flock 118
It is reset by the output of 3.

(2) Channel Control Unit 200 FIG. 5A shows an example of a specific configuration of the channel control unit 200.

As described above, when the frame Iir] M section 100 establishes synchronization and outputs the channel act signal CHACT, the channel control m200 performs an AND gate at the timing of the clock signal CLK[ also from the frame synchronization section 100. 201 and the channel counter 202 starts counting.

When the contents of the channel counter 202 reach a value corresponding to the number of channels in the information communication area within the frame, the decoder 20
;In'' outputs the end channel signal ENDCH.

Channel act signal C from frame A11 section 100
When HACT is turned off, it resets channel counter 202 through invert gate 204.

The output of channel counter 202 is sent to terminal bus 1300 as channel number signal CHNO through AND gate 206 when node act and flip-flop 205 are set, as will be described later.

On the other hand, the interface circuit 207 is a circuit for writing data into and reading data from the register selected by the processing device 300, and its specific configuration is shown in FIG. 5B, for example.

The interface circuit 207 shown in FIG. 5B receives a synchronization signal 8Y from the processing device 300 through the terminal bus 130
NC, terminal number TMNO, register signal RE number O, read and write control signal MW data D are input,
In the matching circuit 208, when the synchronization signal 8YNC is input, the terminal number TMNO is compared with the terminal number assigned to itself from the terminal number generator 209, and when the two match, the read/write control signal R/W is output. generates an output from the AND gate 210 or 211 in accordance with Output. At the same time, the transmission gate 214 or the reception gate 215 is also selected, and either the data D from the processing device is inserted into the register selected by the write select signal WS, or the contents of the selected register are output and sent to the processing device. do. In addition, register number RE
What is designated as GNO''c is not limited to a register, but may also be a device with a storage function such as a flip-flop.

In FIG. 5A, line head channel register 216,
The line termination channel register 217, the out-of-synchronization status 7 flag 218, and the node act flip 70 flag 205 are selected by the register number REGNO from the processing device.

The line start channel register 216 and line end channel register 217 have the first channel number and the last channel number of the line switching area of the frame stored in advance by the write select number WS or ws sent from the processing device through the interface circuit 207. is stored in advance. Further, the clip 70 toggle 205 is set with data D at the timing of the write select signal ws when operating the node device. and,
When the match circuit 219 detects that the contents of the channel counter 202 match the line head channel register 216, the line switching area flip-flop 220 is set. Further, the match circuit 22 indicates that the contents of the channel counter 202 match the line end channel register 217.
1, the detected signal is delayed for a certain period of time by the delay circuit 222, and then the flip-flop 220 is reset.

When the 7 lip flop 220 is set, if the node is active and the 7 lip flop 205 is in the set state, the AND gate 223 is opened and the line gate signal LI
NG is generated and sent to the terminal) (S 1300).

In the processing device 300, in order to know the state of the out-of-synchronization state flip-frog 218, the interface circuit 2
A read select signal R8 is sent through 07, the buffer gate 224 is opened, and the contents of the flip-flop 218 are taken in. At the same time, the flip-flop 218 is reset by a signal delayed for a certain period of time by the delay circuit 225.

Furthermore, the contents of register 216 or 217 are successively outputted through buffer gate 226 or 227 in response to read select signal R8 from interface circuit 207.

0) Processing device 300 FIG. 6 shows an example of a specific configuration of the processing device 3oo.

The processing device array OO is divided into a processing section 300A and a conversion section 300B, and the processing section 300A has at least a processor t3.
01 memory 302 and bus 303.

A bus 303 connected to the processor 301 and the memory 302 receives address strobe signals A8YNC,
Address signal ADR8, read/write control signal R/W
and data Dr, and those signals are converted into the converter 3
It is input to 00B. In the conversion unit 300B, the processing unit 30
The upper bit of the address signal ADR8 from 0A is sent to the matching circuit 304, and the upper bit of the address is sent to the address generator 3 at the timing of the address strobe signal ASYNC.
It is set to 05. A check is made to determine whether the address pattern indicates access to the interface circuit. Furthermore, the lower bits of address ADR8 are sent out as they are as terminal number TMNO and register numbers R and EGNO.

In addition, the read/write control signal R/W is the synchronization signal 5Y.
At the timing of NC, data D is transmitted through AND gate 306, and AND gates 306 and 307 open buffer gate 308 or 309t to transmit or receive data D.

The various signals created in this way are processed not only by the interface circuit of the channel control unit 200 described above, but also by
Terminal control unit 500. ! It is also sent to the interface circuit of the Jlink control section 600 and the packet interface section 800.

(4) Transfer Control Unit 400 FIG. 7 shows an example of a specific configuration of the transfer control unit 400, which is composed of 400 transmitting/receiving units and a transfer unit 400B.

In the transmitting/receiving section 400A, the receiver 401 receives information from the loop transmission path 1200, demodulates the information, and uses the information to generate a bit timing signal TIM of the received information.
The information is sequentially stored in the shift register 402 at the timing of this timing signal TIM. ,0
Next, at the rise of the clock signal CLKI from the frame synchronization 5100 described above, the output of the shift register 402,010 bits is set in the receiving register 403 in parallel.

On the other hand, the transfer unit 400B sends two bits of the output of the reception register 403, the valid indication bit and the occupancy indication bit, to the reception register 404 as they are, and sends the occupancy indication bit through the not gate 405 to the occupancy indication signal I.
It is sent to the terminal bus 1300 as a DLE. The remaining 8-bit data information output from the reception register 403 is sent to the packet control unit 7 as a signal ADDR for address verification.
00 and one input of the status selector 406. Further, the other input of the status selector 406 receives a status signal 5TATB from the packet control unit 700 and a status signal indicating the presence or absence of an error, which will be described later.

In this status selector 406, the packet control unit 7
Send data is selected according to status select 5 TATSEL from 00. That is, when the signal is not present, the output of the receiving register 403 is selected, and when the signal is present, the status signal 5TA8 etc. which is the other input is selected. On the other hand, the status select 5 TAT 8 EL signal is sent, for example, when it is necessary to return the status to the 16th channel while receiving the kerato area for connection control.
The status signal 8TATB and the output of the zero detector 417 are selected. The selected output of status selector 406 is sent to reception register 404. In the reception register 404, input data is set by the frame synchronization unit 100 or the rack lock CLKH. The empty/occupied indicator pin in the output of the reception register 404 is input to the busy control circuit 407, and the remaining 9 bits are sent to the terminal bus 1300 as reception data RD.
At the same time, it is input to one side of the mode selector 408. Further, the output of 8 bits of data information from the receiving register 404 is inputted to the register 1 of the t-FIFO memory 4091. The FIFO memory 409 stores the output of the reception register 404 in registers 409-1 and 409-2.
At the timing of CLKI, and at 409-3, CLKI
Stored sequentially at timing I.

Therefore, the received data output from FIFO memory 409 is delayed by two channels and is sent to link control section 600 as packet received data PAKD.

The FIFO memory 409 used here is that the destination address in the connection control packet is the third channel, 61),
This is because it is necessary to judge that the destination address is the own address and input the received data.

The other input of mode selector 408 has terminal bus 13
When the transmit data 8D from 0G is input, the selector 408 selects the transmit data 8 when the mode select signal MOD8EL from the packet control unit 700 is turned on.
When D is selected and the mode select signal MOD8EL is turned off, the output from the receiving register 404 is selected.

The busy control circuit 407 forcibly sets the empty/busy indication bit in the received information to this display when the busy-on signal BU8YON from the packet control unit 700 is on, and when the busy-off signal BUSYOFF is on, the busy control circuit 407 The display bit is forcibly set to empty display. At other times, the busy control circuit 407 has the function of outputting the signal from the receiving register 404 as is.

Next, busy control circuit 407 and mode selector 40
8 is set in the transmission register 412 at the timing of the clock CLKI. Of the output of the transmission register 412, two bits, the empty indication bit and the valid indication bit, are the tt.
The data is input to the transmission register 413 of 400 transmitters and receivers.

On the other hand, the remaining 8-bit data information is input to check selector 414 and arithmetic unit 415.

The check register 416 is reset by a reset signal BCCR8T from the packet control unit 700.

After the packet control unit 700 receives the check operation start signal BCCACT, the arithmetic unit 415 is operated to perform an operation on the output of the check register 416 and the output of the transmission register 412, and the result is clocked. Set in the check register 416 at the timing of CLKI[. This operation is a division by a specific constant, and is a method generally used for checking transmission information. These operations are repeated, for example, while transmitting data information of channels 1 to 14 in the connection control packet area.

At the 15th channel, the check select signal BCC8EL is sent from the packet control 115700 to the selector 414, and at that timing, the selector 414 selects the arithmetic unit 4.
15 outputs are selected and sent to the transmission register 413.

The zero detector 417 indicates that all bits of the arithmetic unit 415 have a predetermined value,
For example, it has a function of detecting 0, and its output is input to the status selector 406 together with the status signal 5TATB. In short, the zero detector 417 detects whether or not the data information is defective based on whether the calculation results of each bit of the data information of channels 1 to 15 in the connection control packet area are all zero, for example. Then, put the result on the 16th status channel in the packet area.

The transmission register 413 of the transmission/reception unit 400A sets the outputs of the transmission register 412 and the check selector 414 at the timing of the clock CLK11 from the frame synchronization unit 100, and then outputs the contents to the timing signal TIM.
The data is shifted one bit at a time and transmitted to the loop transmission line 1200 via the transmitter 418.

In addition, as mentioned above, in frame 1lJG [100, clock tie/
The received information can be transferred at any time.

(5) Terminal control section 500 FIGS. 8A and 8B show an example of a specific configuration of the terminal control section 500, and FIG. 8A shows its basic part, and FIG.
The figure shows an empty channel selection section.

The 8th person figure has an interface circuit 501 in the basic part.
is composed of a circuit similar to that shown in FIG. 5B, and sends and receives data to and from the processing device 300.

The transmission channel register 502 stores the channel number within the circuit-switched area to be transmitted 61, and the reception channel register 503 stores the channel number within the circuit-switched area to be received.

Also, the contents of the mode register 504 are 4 bits of information υ, and the 2 bits 504-1 and 504-2 of the circle are:
This shows how to connect the bus during transmission. 504-1 is connected to the loop transmission line 12 via the transfer bus in the terminal bus 130G.
00 to send data, and 504-2 to the terminal bus 1300! to another terminal control unit in the same node device.
- Indicates when transmitting data via the internal bus.

First, the remaining two bits 504- of the mode register 504
3,504-4 indicates the bus connection method at the time of reception.
Bit 5G4-3 indicates the case where data is received from the loop transmission line 1200 via the terminal path 1300, and bit 504-4 indicates the case where data is received from the terminal I (speed) from the other terminal control unit in the same node device. 13 shows a case where data is received via an internal bus within the 1300.

These transmit channel registers 502, receive channel registers 503, and mode registers 504 can be set with data D by the write select signal WS from the interface circuit 501. Read the output according to the select signal R8 (respectively buffer) 50
5, 506 and 507't- to the interface circuit 501.

Also, transmit and receive channel registers 502 and 5
03, as will be explained in detail in FIG. 8B, the timing of the clock CLKI after the hunt request is received is
K-8 and R are used to update and register channel number CHNO1, and when an empty channel in the circuit switching area occurs, it is possible to finally register that channel number. 50 which is the transmission instruction of the mode register 504
Only when there is an output from the OR gate 524 that detects that either 4-1 or 504-2 is set, the output from the transmission channel register 502 is outputted to the signature circuit 510 by the AND gate 508.

Similarly, the OR gate 525 is used to transmit the transmission mode register 50.
It is detected that one of 504-3 and 504-4 of 4 is set, and the output of channel register 503 is passed through AND gate 509 and output to coincidence circuit 511.

Note that data from the processing device ft300 is set in the registers 502 and 503 via the interface circuit 501, for example, when a connection control packet is received from the other party and a transmission/reception channel number is specified therein.

Matching circuits 510 and 511 detect a match between the contents of the receiving and transmitting channel register 502 and the receiving channel register 503 whose data is set in registers 502 to 504 and the channel number signal CHNO.

When the match circuit 51G detects that the channel number signal matches the transmission channel register 502, the mode register 5
If the content of bit 504-1 of bit 04 is equal to 1, AND gate 512 is opened and mode signal MODE is set to terminal path 1.
At the same time, the buffer gate 514 is opened via the I-AND gate 513, and the transmission buffer 515
The contents of are sent to the terminal bus 1300. On the other hand, when the terminal device 1000 has all the transmission data, it sends a transmission request signal 8REQ.
By turning t-on, 8-bit transmission data 8Df is set in the transmission buffer 515, and the transmission request flip-flop 516 is also set, and the output signal of 9516 is used as a valid indication bit, and is output when the back 7 agate 514 is opened. It is sent to the transfer control unit 400 as transmission data 8D along with the data information to the terminal path 1300. As described above, the transfer control section number 00 operates the mode selector according to the mode select signal MOD8EL corresponding to the mode signal MODE, and sends the transmission data 8D to another node device.

The match output of the match circuit 510 is sent to the delay circuit 517 by j! While transmitting the extended signal to the terminal device 1000 as a transmission OK signal 80, the transmission request flip-flop 1516 is reset. Therefore, if a match of channel numbers is detected before the transmission data from the terminal device 1000 is completed,
Since the transmission request flip-flop 516 is reset before transmitting the data, the valid indication bit of the transmission data 8D becomes O, indicating that the transmission data is invalid. In other words, if the processing speed on the terminal device 1000 side is slow and the data to be sent is not available, the processing speed on the terminal device 1000 side is not limited by displaying an invalid display.

Next, when a match is detected in the match circuit 510, if the mode register 5040 bit 504-2 is 1, the AND gate 518 opens the buffer gate 519, and the above-mentioned transmission data is transferred to the internal bus as internal bus data IND. Send to.

On the other hand, the output of the receiving channel register 503 is ! When detected by circuit 511, the next operation is performed according to the contents of bits 5G4-3 and 504-4 of mode register 504.

That is, the receive data RD from the receive bus and the receive data IND from the internal bus are input to the receive selector 520, and when the bit 504-3 of the mode register 504 is 1, the receive data RD is input to the receive selector 520. is selected, and when bit 504-4 is 1, internal bus data pIND is selected. Among the data selected in this way, data information is input to the reception buffer 521, and the valid display bit is input to the AND gate 522.
to be applied. Based on the valid indication signal of the valid indication bit and the coincidence output of the coincidence circuit 511, the output of the AND gate 522 is turned on, the output of the reception selector 520 is set in the reception buffer 521, and the reception request flip-flop 523 is set. do. This free lag flop 523
The terminal device 1 uses the 0 set output as the reception request signal RREQ.
000, and also sends the contents of the reception buffer 521 to the terminal device 1000 as reception data RD.

When the terminal device 1000 receives the reception request signal RREQ, it sends back a reception OK signal 1'LOK and resets the reception request flip-flop 523.

In this way, the received data is transmitted to the terminal device 1 only when the AND gate 522 indicates that the valid indication bit is valid.
000, it will be received only when it is sent as complete data by the sending terminal device, and data can be sent and received without being affected by the speed of the terminal device. I can do it.

Next, the empty channel selection function will be explained with reference to FIG. 8B. Although FIG. 8B only shows the circuit related to the empty channel selection function during either transmission or reception, in reality, the circuit in FIG. 8B corresponds to transmission and reception.
This means that two circuits shown in the figure are provided.

In such a configuration, when a hunt request is sent from the processing device 300 via the interface circuit 501, the AND gate 53 is sent at the timing of the clock CLKI.
1 and set the hunt request clip 70 tab 532. When the hunt request clip 70 tab 532 is set, the line gate signal LIN indicates reception of the line switched area.
G, the empty display signal IDLE indicating that the channel of the received data is an empty channel, and the output of the hunt request flip processor 1532 are input to the AND gate 533, and when the above-mentioned hunt condition is satisfied, the AND gate 533 After the output signal is delayed for a predetermined time by the delay circuit 534, the empty channel acquisition flip-flop 535 is set and the hunt request flip-flop 532 is reset. On the other hand, while the hunt request flip-flop 532 is set, the clock CLKI input gate 53
6 to obtain the signal HTCLK, input this signal to the channel register 502 or 503 of the 8th person figure, and at that timing, channel number signal CHNO1-*b is sequentially loaded into the channel register 502 or 503 and updated. As described above, when an empty channel is detected and the hunt request flip-flop 532 is reset, the register reading operation is stopped, so that eventually the channel number corresponding to the empty channel is stored in the register. This means that it has been done.

The output signal of the delay circuit 534 is input to the delay circuit 538 through the OR gate 537, where it is delayed for a predetermined time and sent to the packet control unit 700 as a busy signal BUOY.
Converts to busy-on signal BU8YON. Besides,
The transfer control unit 40G sets the idle indication bit of the corresponding channel being transferred to an occupied indication, and prohibits hunting in other terminal devices. Thereafter, even after the hunt is established, the match output C0IN-8 or B of the match circuit 510 or 511 in FIG. 8A is sent to the delay circuit 53 through the AND gate 539 and the OR gate 537.
8, and after being delayed for a predetermined time by the delay circuit 538, it is also sent out as a busy signal BUSY, and the empty/occupied indication bit is set to indicate occupied. Note that the delay circuit 538 has a clip-flop 535 set to maintain proper timing.
After one hunt is established, the set output closes the AND gate 531, prohibits subsequent hunt requests, and prevents double channel hunt.

On the other hand, when data transmission or reception is completed and the occupied channel is to be released, write select 1 is sent from the interface circuit 501 according to an instruction from the processing device 1300.
Sends the d WS, opens the AND gate 540 at the timing of the clock CLKI, and releases the release request flip-flop 5.
One set on 41st. Then, the contents of the channel register 502 or 503 in FIG. 8A and the channel number signal CH
Wait for a match with NO to be detected, and when a match is detected in the match circuit 510 or 511 and the signal C0IN-8 or C0IN-R is output, the output from the Antogame 1542 is sent to the delay circuit for timing v4 adjustment. After a predetermined time delay in 543, the empty display OK double signal DLEOK is sent to the packet control unit 700, and the busy off signal BU8YOFF is sent.
is sent to the transfer control unit 40G, and the empty indication bit of the occupied channel is forcibly made to be empty.

At the same time, the release request flip-flop 541 and the empty channel acquisition flip-flop 535 are reset,
Complete the release action.

In addition, in order to prevent multiple terminal control units in the four-node device from entering the hunt request state at the same time, the program in the processing unit is controlled so that only one terminal always performs the operation. This prevents multiple terminal control units from hunting.

In the above-described embodiment, a case has been described in which the terminal device occupies only one channel for transmission or reception, but it is also possible to allocate a plurality of channels to the terminal device. FIG. 8c shows an example of the configuration of the main part of the basic part of the terminal control section in this case.

In the figure, channel registers 551 and 552 are used for both transmission and reception, and matching circuits 555 and 556 detect a match between the contents set in these registers and the channel number signal CHNO, and one of the matching circuits If a match is detected, an output is made from the OR gate 557.

On the other hand, in order to adjust the speed of the sending and receiving terminal interfaces, FIFO memories 55 are provided for sending and receiving, respectively.
8 and 559 are provided.

In this FIFO memory 558, a validity indicator indicating that the data is valid is stored together with the transmission data 8D at the timing of the transmission request signal 5REQ sent from the terminal device 1000.

As described above, when a match is detected, the detection signal is delayed for a predetermined time by the delay circuit 560, and the transmission data stored in the FIFO memory 558 is read out at the timing of the delayed signal.At this time, data transmission is performed. If the mode register 504 pitches 504-1 and 504-2
The same operation as that described in FIG. 8A is performed depending on the contents of .

On the other hand, when receiving data, the mold register 5
According to the contents of bits 504-3 and 504-4 of 04, receive data RD or internal bus data IND is selected by selector 520 as described in 5 in the 8th person figure, and when the selected data is valid, , that data?
The terminal device 1000 K9! stores the contents sequentially in the F'0 memory 559 and reads the contents at a predetermined timing. , I
Send as M data RD.

Also, corresponding to the channel register 551, the 8th BwJ
A circuit having an empty channel selection function as shown in FIG. The channel numbers CHNO are taken into the channel registers 551 to 552 one after another and updated. Further, the output of each bit of the mode register 504 is logically summed by an OR gate 563, and only when any bit of the mode register 504 is set to 1, the output of the channel registers 551-552 is output to the AND gates 553-554. Through the matching circuit 553~
554.

Coincidence outputs C0IN-1 to C0IN-n are applied to respective AND gates 539 and 542.

Further, the output obtained by taking the logical sum of the outputs of the respective delay circuits 538 using an OR gate is sent out as the busy signal BUOY, and the logical sum of the outputs of the seven n delay circuits 543 is similarly taken, and the output is used as an empty signal. Display OK signal IDLEO
It is configured to be sent as K.

In addition, the interface circuit 5o construction - dose Vri)
Signal RS signal, buffer gates 561 and 562
It is also possible to open the channel registers 551 and 552 and import the contents of the channel registers 551 to 552 into the processing device.

In the embodiment described above, communication between any two of the plurality of terminal control units in the same node device is possible by using the mode register 504 and the internal bus, but this is shown in the gSD diagram. Let me explain in detail.

The figure shows a transfer control unit 40G and a plurality of terminal control units 500'A.
, 500B, and shows the connection relationship with the terminal bus 130
0 are buses necessary for connection between them, that is, bus 1301 for mode signal MODE, transmission high for transmission data sD, 1302, reception bus 13 for reception data RD.
03. It has an internal bus 13o4 for internal bus data IND and a bus 13o5 for channel number signal CHNO.

Terminal control units 500A and 500B in the same node device
When communicating between the terminal control unit 500 Ao! The values of the transmitting channel register 502 and receiving channel register 503 in the host 500B are all set to the same channel number.

Next, an example of a method for setting a channel number will be described. One terminal control unit on the transmitting side, for example, 500 people, searches for an empty channel, and when an empty channel is found, sets the channel number in the transmission channel register 502. The processing device 300 reads the channel number set in this register 502, and stores the same channel number in the reception channel register 503 in the same terminal control unit 500A.
It is also set in the transmission and reception channel registers 502 and 503 in the other terminal control unit 500B. Furthermore, in the processing device 300, the terminal control unit 5
In mode register 504 in 00A, bits 504-2 and 504-3 are set to 1 to instruct connection to reception bus 1303 on the reception side and connection to internal bus 1304 on the transmission side, and bits 504-2 and 504-3 in terminal control unit 500B are set to 1. In mode register 504, bits 504-1 and 504-4 are set to 1 to instruct connection to internal bus 1304 on the receiving side and to transmission bus 1302 on the transmitting side.

As a result, the transmission information from the transmission section 590B of the terminal control section 5QOB is transmitted to the transmission bus 1 as shown by the thick line in FIG. 8D.
Similarly, a mode signal is sent to the transfer control unit 400 via the bus 1301.
Send to 0. When the mode signal of the bus 1301 is turned on, the transfer control unit 400 sends the transmission information to the loop transmission line 1200 on the channel of the set number.

The information thus circulated around the loop transmission path 1200 is received by the transfer control unit 400 and sent to the reception ff11591A of the terminal control unit 500A via the reception bus 1303.

On the other hand, when transmitting information from the terminal control section 500A to the terminal control section 5ooB, as shown by the thick line in FIG. Data on the internal bus 13o4 is received by the receiving section 591B of the terminal control section 500B.

Moreover, the dotted line in the figure shows the signal path in the case of the above-mentioned transfer.

Link Control Unit 600 The link control unit 600 performs processing for transmitting and receiving packet data in the connection control packet area (hereinafter abbreviated as link packet data) during the circuit switching function. The configuration and operation of this link control unit 6oo are the same as the configuration and operation of a device that transmits and receives data during the packet switching function.
They are almost the same except for the terminal interface.

FIG. 9 shows an example of the configuration of the link control section 600.

In the figure, 602 and 603 are registers in which the start channel number and end channel number of the connection control packet area A (hereinafter abbreviated as link packet area) are sent from the processing device 300 through the interface unit 601, respectively. Initialized. Therefore, for example, in the case of a frame configuration as shown in FIG. 2B, the link head channel register 6
02 is set to channel number 5, and link end channel register 603 is set to channel number 20. When setting data representing a channel number in each register 602, 603, a write select signal WS specifying an address previously assigned to each register and data D representing a channel number to be set are applied to the register. This is achieved by Further, when a read select signal R8 designating the address of each register 602 and 603 is applied, data representing a channel number stored in each register is read out via buffer gates 608 and 609, respectively.

The output of both registers 602 and 603 is determined by the channel control unit 2.
Along with the channel number information CHNO sent from 00 through the terminal bus, the scattering output circuits 604 and 60 respectively
Added to 5. - The scatter product output circuit 604 has a register 60
When the contents of 2 and the channel number information CHNO match, an output signal is output, and this causes the start timing circuit 60
6 is activated. This timing circuit 606 outputs the signal 8TCH at a timing synchronized with the clock CLKI in the first channel. On the other hand, −scattering product output circuit 605
is the contents of register 605 and channel number information CHN
When the 0 and 0 match, an output signal is generated, thereby activating the end-timing circuit 607. This timing circuit 607 outputs the clock signal CLKM in the end channel.
The signal TECH is output at a timing synchronized with .

Upon activation of the head tie building circuit 606, the head channel signal 8TCH is sent via the terminal bus to a packet control unit 700, which will be described later, to start packet data transmission/reception control.

Further, when the end timing circuit 607 is activated, the end channel signal TECH is sent to the packet control section 70G in the same manner as before, and the packet transmission/reception control is completed.

A zero detection circuit 631 outputs an output when the channel number CHNO is zero, and when this output is present, the output of the one-way detection/output circuits 604 and 605 is prohibited. This circuit 631
is provided because the contents of registers 602 and 603 become 0 when there is no specified date for link packet area A.
A match was detected and the timing signal 5TCH was detected by mistake.

This is to prevent TECH from appearing.

Next, the packet data transmission operation will be explained.

A packet to be transmitted is created by the processing device 300,
FIFO for transmission via interface section 601
Buffer memory circuit (hereinafter abbreviated as PIFO) 612
are written sequentially. This post, as mentioned above,
This is realized by applying a write select signal W8 specifying an address previously assigned to the transmission FIFO 612 and packet data D to the transmission PIF 0612.

After writing the packet data is completed, processing device #L30
0, a transmission request signal is sent out, and this is applied to the flip-flop 610 via the interface section 601ft. The output Q of this flip-flop opens AND gate 623.

The contents of the first channel register 602 and the channel number C
When the start timing circuit 606 is activated and its output is sent to the terminal path as the start channel signal 8TCH, the signal K is simultaneously output.

It is applied to the AND gate 623. The AND output of this AND gate 623 is sent out via an OR gate 625 as a status signal 8TAφ. This status signal 5TATA is sent to the packet control section 700,
A transmission request is issued to calculate the product with the timing signal 8TCH. Also, a flip-flop 611 is set by the output of the leading timing circuit 606, and its output Q is added to AND gates 626 and 628.

As a result, it becomes possible to receive the transmission gate signal 8G sent via the terminal bus.

On the other hand, the packet control unit 700 looks at the leading bit of the large link packet area and, when confirming that it is an empty area, sends out a transmission gate signal SG.

This transmission gate signal 8G passes through the AND gate 626 and is applied to the AND gate 620. Therefore, while the transmission gate signal SG is on, the clock signal CLKII enters the transmission PIFO 612, and the packet data stored in the transmission FIFO 612 is sequentially sent out through the AND gate 627 in synchronization with this clock. This transmission data 8D is applied to the mode selector 408 of the aforementioned transfer control section 400 via the transmission path. Further, the transmission request flip 70 knob 610 is reset by the transmission gate signal SG. This puts the device in a state of waiting for the next transmission request.

When the contents of the link end channel register 603 match the channel number CHNO, the timing circuit 607 sends out the end channel signal TECH as described above. This end channel signal TECH enters the packet controller 700 via the terminal bus. The packet control unit 700 performs packet data transfer completion processing as described later, and turns off the transmission gate signal 8G'. This is the sending PI
The game connected to F0612) 620°627 is closed,
The operation of transmitting packet data of the size of the link packet area ends.

Next, the operation of receiving packet data sent from the other party's node device will be explained.

Similarly to the above, in the node device that receives data, based on instructions from the processing device 300, the start channel and end channel numbers of the link packet area are stored in the register 602.
603 respectively. When the leading channel number set in the same manner as described above and the channel number CHNO sent via the terminal bus match, the leading channel signal 5TCH is sent to the packet control unit 700. As will be described later, when the packet control unit 700 detects -gcwo between the destination address and the address of its own node device, it turns on the reception gate signal RG.

The reception gate signal RG is applied to the gate 628 of the link control section 700, and the packet data PAKD from the transfer control section 400 is applied to the reception PIF0613. Since the flip-flop 611 is set at the timing of the first channel, its output Q causes the AND gate 62 to be set.
8 is open.

Therefore, the reception gate signal RG passes through the gate 628 and is torn.
/ )" is applied to the Ketoro 21. While this reception gate signal G is on, the clock signal CLKI [ enters the reception FIFO 613, and packet data PAKD is taken in in synchronization with this. The reception FIFO 613 The packet data stored in is read out by the processing device 300.In other words, when the address of this reception FIFO 613 is specified and the output signal R8 is applied, the packet data is sequentially read out by the processing device 300 via the gate buffer 7617.
Reads out as 00.

On the other hand, a signal indicating whether there is an overflow in the receiving FIFO 613 is applied to the AND gate 624 together with the output of the end timing circuit 607. At the timing of transmitting the end channel signal TECH, the reception FIFO 613
When the stored data is in an overflow state, the AND gate 624 generates a multiple output, which is sent to the packet controller 700 as a status signal 8TATA.

When the end channel of the link packet region (see Figure 2B) is detected, the output signal of the end timing circuit 607 resets the shift flip-flop 611, which closes the gate 627 and completes the data reception process. .

The change in the output of AND gate 628 from on to off causes one bit in status register 615 to be set on. The processing device 300 sends a read select signal R8 specifying an address previously assigned to the status register 615, and reads the contents of the register 615 via the gate buffer 619, thereby knowing the end of data reception. can. The completion of reception can also be notified to the processing device 300 through interrupt processing or the like. The read select signal R8 of the status register 615 is sent to the register 6 via the delay circuit 616.
15 reset terminals. Therefore, register 6
After the contents of 15 are read out, it is automatically reset.

Next, the packet data sent by the sending node device is
The process of taking in the data when it goes around the loop-shaped common transmission path and returns to its own node device will be explained.

When the packet control unit 700 receives the first channel signal 8TCH from the link control unit 600, it detects a match between the originating address of the first channel and the address of its own node device. When both addresses match, it means that the received data is the data that was sent from the own node device and returned after completing one cycle. When both addresses match, the packet control unit 700 sends an end gate signal TEG? as described later. This is sent to the link control unit 600 via the terminal bus.

This end gate signal TEG enters the AND gate 622 through the OR gate 629 and the AND gate 63G'i. Therefore, the clock signal CLKII is applied to the transmission end FIFO 614 through the AND gate 622, and the packet data PAKD from the transfer control section 400 is sequentially taken into the transmission end FIFO 614.

As will be described later, this termination gate signal TEG is not on during the entire period of the link packet area, but at least during the channel period of the address information (second
In the example of diagram G, from Ao to A.

11).

On the other hand, the status gate signal 5TATG is the status information channel period (AI in the example of FIG. 2G).

channel period).

Therefore, the termination gate signal TBG and the status gate signal 8
Transmission end FIFO 6 that operates to capture packet data PAKD only while any one of TATG is on.
14 will take in the data of A6~person and AlS channels. This is a function that selectively receives only the necessary information at the end of transmission. Of course, information other than the above may be taken into the transmission end FIFO 614. The processing device 300 can read the data stored in the FIFO 614 through the buffer 618t by sending out a read select signal that passes the address assigned to the transmission end FIFO 614.

Packet Control Unit 700 The packet control unit 700 is for generating timing signals necessary for transmitting and receiving packet data between the link packet area and the packet exchange area. For convenience of explanation, the case of transmitting and receiving data in the link packet area will be described below.

FIG. 10 shows a circuit configuration of an embodiment of the packet control section 700.

The start channel signal 5TCH and end channel signal TECH sent from the link control section 600 are applied to the start timing circuit 701 and end timing circuit 7o-2 of the packet control section 700, respectively. The timing circuits 701 and 702 are used to generate signals synchronized with the start channel and end channel of the link packet area, and timing signals delayed by an arbitrary channel amount from these signals. Based on these timing signals, timing signals necessary for transmitting and receiving data, which will be described below, are created.

First, the operation when transmitting packet data will be explained.

As described above, the status signal 8TATA sent from the link control unit 600 means a request to transmit packet data. When this request is received, the packet control unit 70
0 starts a hunt operation for an empty packet area.

First, the link packet area person's first channel person. The occupancy indication bits A and o (Figures 2F and 20) are ticked. When the idle signal IDLE is on (or @l"), it indicates that the link packet area is empty, and it is turned off ("o").
') indicates that it is blocked. When the idle signal IDLE is off, the AND gate 713 is closed and the transmission operation is not started, but waits until the first channel comes again.

When the idle signal IDLE is on, the output gate 705 of the output gate 713 is set, and its output Q is sent to the link control section 600 as the transmission gate signal SG. Upon receiving this transmission gate signal SG, the link control unit 600 sequentially transfers the data stored in the transmission PIFO 612 to the transfer control unit 400 as described above.
Send to. At the same time, the output Q of the flip 70 toggle 705 is passed through the OR gate 720, and the mode select signal MO
It is added to the transfer control unit 40G as a DSEL. When the transfer control unit 400 receives the mode select signal MOD8EL, the transfer control unit 400 transfers the incoming transmission data 8D from the link control unit 600.
Send out.

Further, the output Q of the clipflock 705 is sent to the transfer control section 400 as a busy-on signal BU8YON via an OR gate 719. This signal is applied to the busy control circuit 407 in the transfer control unit 40G,
The empty/occupied indicator bit A6° of link packet area A is set to indicate occupied.

On the other hand, check the reset signal BCC for a signal synchronized with the first channel As generated from the first timing circuit 701.
It is sent to the transfer control unit 40G as R8T. In response to this signal BCCR8T, the content BOCR of the block check register in the transfer control unit 400 is initialized to zero.

On the other hand, the shift flip-flop 703 is set by a signal at the next timing, and its output Q is sent to the transfer control unit 400 as a check operation signal BCCACT.

When this signal BCCACT is input, an operation is started in which the outputs of the block check calculator 415 of the transfer control unit 400 are sequentially set in the block check register 416.

Thereafter, when an end channel signal TECH indicating the end of the S/W packet area A is sent from the link control unit 601°, the end timing circuit 702 is activated. This circuit 702 is a check byte (second
A timing signal to transfer channel A, 4) in Figure G is created, and this signal is sent to the transfer control unit 4 as a block check select signal BCC8EL via the gate 718.
Send to 00. , When this signal BCC8EL is input, the block check selector 414 transfers the contents of the block check register 416 storing the check operation result to the check code channel number 4 (see FIG. 2G) in the link packet area A and sends it to the common transmission path. Send to. Further, the transmission flip 70 knob 705 is reset by the timing signal from the end timing circuit 702, and its output Q is turned off, so that the transmission gate signal SG and the busy-on signal BU8YON are generated.

and mode select signal MOD8EL are all turned off, and the transmission operation ends.

Next, the operation when the link bucket data sent from the originating node device goes around the loop transmission path and returns to its own node device will be explained.

As in the case of transmission, the first channel signal 8TCH is transmitted from the packet control unit 600 to the packet control unit 70 via the terminal bus.
This circuit 701 enters the top timing circuit 701 of 0.
starts. Further, the reception register 4 of the transfer control unit 400
The address signal ADDR, which is the output of 03, enters the coincidence detection circuit 710 of the packet control section 700. -Scatter product output circuit 7
10 detects whether the address signal ADDR and the address signal of its own node device generated from the address generator 711 match at the timing of the first channel Ao of the link packet e-region. In this embodiment, as is clear from FIG. 2G, since the originating node address is assigned to the first channel As, the fact that the address of this channel A and the address of the address generator 711 match means that This means that the packet data sent from the own node device has gone around the loop transmission path and returned. Therefore, at this time, the received data is loaded into its own node device and the transmission is completed.

First, if the above two addresses match, Antogame)71
The output of 4 sets the transmission end flip-flop 706. The output Q of this flip-flop 706 passes through an OR gate 721 and outputs a busy off signal BUSYOFF.
It is added to the busy control circuit 407 of the transfer control unit 400 as a transfer control unit. The busy control circuit 407 controls the first bit of the packet area A. . is set to 101 (displayed empty), allowing other node devices to use the packet area.

On the other hand, the timing circuit 701 determines the timing to turn on the termination flip-flop 707 at the timing when the link packet area person address information (channels A to A) is sent from the transfer control unit 400 to the link control unit 600. Applying the signal Apply this timing signal to the set terminal S and reset terminal R of 707. Also, the status information (channel person information) is transferred to the transfer control unit 40.
A timing signal that turns on the status flip-flop 708 at the timing when the status flip-flop 708 is sent from 0 to the link control unit 600 is generated by the 7-lip flop 723, the AND gate 716, etc., and this is applied to the set terminal S and reset terminal R of the 708. Apply.

The outputs of both flip-flops 707 and 708 are sent to the link control section 600 as an end gate signal TEG and a status gate signal 8TATG, respectively.

The link control section 600 receives the gate signal T as described above.
The period when EG and 8TATG are on, that is, channel A
, -A4 and person 1. The information is input to the transmission end FIFO.

Note that creating a timing signal that turns on the 7-rig frogs 707 and 708 only for a predetermined period as described above can be easily realized by using a counter or a shift register as the timing circuits 701 and 702. I can do it.

Next, the operation when receiving packet data sent from the originating node device will be explained.

In this embodiment, the destination node address is included in the third channel A (see Figure 2G) of the link packet area A, so when receiving data, the address information of the channel person and the address information of the own node device are used. A match with the address must be detected.

For this purpose, the timing circuit 701 first generates a timing signal synchronized with the channel A, and applies this to the AND gate 717.

On the other hand, the address signal ADDK sent from the transfer control unit 400 and the address of its own node device are compared in the match detection circuit 710, and if the two addresses match at the timing of the channel person, the output is sent to the AND gate 71.
7ft and is applied to the set terminal of the receive flip 70 and the switch 709.

If both addresses match at the above timing, it means that the sent packet data is information addressed to the node device itself. Therefore, in order to start the reception operation, the packet control section 700 sends the output Q of the flip-flop 709 to the link control section 600 as the reception gate signal RG.

The problem here is that it becomes clear whether each node device should receive all of the 7 (button) data at the time it receives the destination node address information of the third channel. In this case, it is necessary to also capture the source node address of the first channel A0 and the source terminal address of the second channel A1.
1st. Information on the second channel A6 e Al also needs to be temporarily stored. FI of the aforementioned transfer control unit 400
FO memory 409 is used to delay packet data by two channels, thereby allowing data to be received from the first channel A. When the reception gate signal RG enters the link control section 600 from the packet control section 700, the transfer control section 40 synchronizes with this.
0, the 1st channel As and the 16th channel AI enter the link packet area 60G as packet data PAKD and are taken into the receiving FIPO 613. On the other hand, the tying circuit 702 A timing signal synchronized with channel All of the status device of the system is generated and applied to the AND gate 722.

After the reception free lag frog 709 is turned on, the AND gate 722 opens at the timing of the channel person 1m, and its output is sent to the transfer control unit 400 as the status select signal 8TATSEL. Transfer control unit 400
When the status select signal 8TATSELe is received, the status information 5TATB indicating the reception status is placed on the channel AII and the packet data is sent to the reception register 404. As can be seen from FIG. 10, the above status signal 8TATB is a separate status signal 5TAT.
It is generated by delaying the AND output of A and the end channel signal TECH by a delay circuit 704 for a predetermined time. Also, as can be seen from Figure 9, when the status signal 5TAT is ANDed with TECH, the reception FI
The situation whether FO613 overflowed? : Crowded.

The above explanation has been about timing control in the case of sending and receiving data in the link packet area, but since it is exactly the same in the case of sending and receiving data in the packet switching area, the explanation thereof will be omitted.

Packet interface unit 800 Packet interface gsoo is the packetization device 11
It constitutes an interface between 00 and other devices, and controls the transmission and reception of data in packet exchange area D (see Figures 2c and 2D).

The configuration and operation of this interface section 80o are substantially the same as those of the link control section 600 (see FIG. 9), so only the different parts will be explained below.

FIG. 11 shows a frame configuration control unit in the hacket interface ss o o, and the other parts are the same as FIG. 9.

As is clear from FIG. 2c, in the case of this embodiment, a maximum of four packet exchange areas can be set in a frame. Therefore, it is necessary to prepare four sets each of the first channel register and the end channel register. Therefore,
Here, a four-word register file memory 822 is used. Start channel part 81G and end channel part 82
The configuration of 0 is the same, and the first channel register portion 810 will be explained here as a representative example.

Lower each leading channel number of the four packet switching areas
Initial settings are made in the register file memory 822 in order. This setting is realized by sending a write select signal WS specifying the address of the memory 822 and data Dr indicating each leading channel number from the processing device. The signal from the processing device 300 is sent to the interface section 8.
The data is input to the decoder 811 via 01t, where it is decoded and then set in the register file memory 822.

When the area is not divided up to the maximum division number of 4, the remaining register contents are set to t-0.

A node act signal MODEACT sent from the channel control unit 200 is applied to the decoder 811, and only when this is off, successive reading and writing of channel register numbers is possible. This node act signal MOD
As described above, EACT is used to control the operation of a node device or stop its operation.

When reading the contents of the register file memory 822, a read select signal R8 is sent from the processing device 3oo and is applied to the access selector 826. This access selector 826 has a /- act signal N0.
Only when DEACT is off, the read select signal Ry
f: Add to selector 823. The data read from the memory 822 is sent to the selector 823 and buffer gate 827.
It enters the processing device 300 via.

After the initial setting is completed, the node act signal N0DEAC
T is turned on and control of transmission and reception of packet data is started.

First, a signal CHNO representing a channel number sent from the channel control section 200 is applied to the zero detection circuit 825. When this zero detection circuit 825 detects that the channel number is zero, it inhibits the output of the -scattering product output circuit 824. As mentioned before, when no packet area is specified, the content of the register file memory 822 is "O'Kfi", and the match detection circuit 824 determines the output at the timing of channel number 〇 in the synchronization area. This is to prevent it from coming out.

On the other hand, the output of the zero detection circuit 825 is the output of the access counter 8
28 and resets the contents of the counter 828. However, the access counter 828 maintains a state of 0 during the synchronization region X of the frame. The contents of this access counter 828 are added to the access selector 826.

Since the node act signal N0DEACT in the on state is applied to the access selector 826, the signal ("0") input from the address color/receiver 828 is output as is.
3 and becomes a selection signal for the register file memory 822. Therefore, the zeroth word of this register file memory 822 is read out and applied to one input of the -scattering product output circuit 824. The other input is the channel number signal CH
NO is applied. When the two human power signals match, the leading timing circuit 802 is activated by the output of the matching detection circuit 824, and the subsequent operation is the same as that of the link control section 600.

Access counter 8 according to the output of timing circuit 802
The value of 28 is counted up and becomes 0.1''. Therefore, the first unit of the register file memory 822 is started, and preparations are made to detect the first channel of the second packet exchange area.

The above is a description of the detection of the first channel, but the same applies to the end channel, so the details will be omitted.

Frame Generation Control Unit 900 An example of the configuration of the frame generation control unit 900 will be described with reference to FIG. 12.

This frame generation control unit 900 is provided in one of the node devices (referred to as a frame control node device) of the node devices connected to the loop-shaped common transmission path, and is a transfer control unit shown in FIG. Transmitting/receiving section 400 of section 400
It is connected between the person and the transfer unit 400B.

The transmitting quad oscillator 901 serves as the primary oscillator for the transmission lock in the data communication system of the present invention.
Only the frame control node device uses the output of the transmission clock oscillator 901 as the transmission clock of the transmitting/receiving section.

The output pulse of the transmission clock oscillator 901 is first
It is applied to the O-address converter 902.

The reason why a decimal clock counter is used is that in the embodiment of the present invention, one channel consists of 10 bits. The output of this clock counter 902 is further applied to a clock decoder 903, which outputs a clock signal CLKo I=C used within the frame control node device.
LKoI[ and a timing signal for accessing the synchronization circuit 906 and frame memory 912, which will be described later, are generated. Like the clock signals CLKI and It in a normal node device, the clock signals CLK61, 1, for example, are clocked between 0 bit and 1 bit and between 5 bit and 6 bit among the 10 bits of one channel. 11, otherwise it will be 01, so it is four.

On the other hand, four-way signals CLKI and If are generated by the frame synchronization unit 100 based on the timing signals generated by the receiver 401 of the transfer control unit 400.

The signal RR transmitted from the reception register 403 is synchronized with the reception clock and is asynchronous with the output of the transmission clock oscillator 9010 described above. Therefore, this frame generation control unit inputs the clock signals CLKI, If, and the RR multiplied signal, and performs phase matching with the transmission clock CLKol=II.

For this phase adjustment, first, the synchronization circuit 906 receives the clock signal CLK1. from the frame synchronization section 100. If and the signal from the clock decoder 903 are applied, and here the reception clock CLK1. A signal is generated at an appropriate timing that avoids the timing before and after the rising edge of If and the timing before and after the rising edge of the transmission clock CLK.I.

On the other hand, the reception clock CLKI [and the channel act signal CHACT are applied to the AND gate 93o, fl, this (i
The output of D-game) 930 is added to receive channel counter 908. This is the reception channel counter 908
When counts a predetermined number of channels, a decoder 907 decodes this and generates an end channel signal ENDCH.

The count value of the reception channel counter 908 and the content PR of the reception register 403 are set in the synchronization buffer registers 909 and 917, respectively, at the output timing of the synchronization circuit 906.

Furthermore, the contents stored in the buffer registers 909 and 917 are set in the reception registers 910 and 918, respectively, at the timing of the transmission clock CLKoI.

The Mayuki clock decoder 903 receives the transmission clock CLKol.
A signal that is turned on from the falling edge of CL to the falling edge of CL J o I (that is, a signal that is turned on for 1/2 of one channel) is applied to the address selector 911 and the write gate 914. . Accordingly, the address selector 911 selects the receive register 9 of the two inputs.
The output of 10 is selected and applied to the address input terminal 912 of the frame memory. At the same time, the write gate 914 opens and the output of the receive register 918 enters the frame memory 9120 input terminal. Therefore, in the frame memory 912,
The contents of the reception register 918 will be written to the address indicated by the reception channel register 91G.

The frame memory 912 has x=txo bit, and 1
It has a capacity to store information with a number of words equal to the total number of channels in a frame. In other words, it has a capacity to store all information for one frame.

During the other 172 times in the l channel, from the falling edge of the transmission clock CLKol to the falling edge of CLKol, the address selector 911 selects the output of the channel counter 904 from among the two inputs. It is added to the address input terminal of frame memory 912. A transmission clock CLKon is applied to the channel counter 904, which counts the number of transmission channels. From the frame memory 912, the channel counter 909
The information at the address indicated by the value of is read out, and the information is sent to the transmit register 9 at the rising timing of the transmit clock CLK・I.
It is set to 13.

When the count value of the channel counter 904 mentioned above reaches a predetermined value (the final channel number), the value is reset by the output of the decoder 905.

On the other hand, the information read into the transmission register 913 is
It is applied to the transmit selector 916 along with the output of the synchronization pattern@generator 915. The transmission selector 916 sends out the output of the synchronization pattern generator 915 when the channel counter 904 indicates the synchronization area (channels 0 to 3 in this embodiment), and sends out the output of the synchronization pattern generator 915 when the channel counter 904 indicates the other area. Send the contents. The output RR of this transmission selector 916 is sent to the transfer section of the transfer control section 400. That is, the information RR received by the reception register 403 is sent to the transfer unit after being phase-aligned with the timing of the transmission clock by the above-described operation.

The frame generation control unit 900 has an abnormality monitoring function in addition to the above-mentioned phase matching function. In other words, if all the vacancy indication bits of all channels indicate occupancy for a certain period of time or more, it is determined that there is an abnormality in the system, and the vacancy indication bit [1-Forcibly This is a function to change the display.

This function is realized by components 919 to 929 of the circuit shown in FIG.

In the following description, the above-mentioned abnormality monitoring function will be described separately into abnormality detection in the circuit switching area and abnormality detection in the packet switching area.

Timing detection in circuit switching area B (see Figure 2B) is as follows:
This is performed in the channel control unit 200, and is performed in the circuit switching area B.
The line gate signal LING, which is on during the period, is sent out and is broken. This line gate signal enters the AND gate 923 along with the clock signal CLKI[, and its output is applied to the C terminal of the delay type flip-flop 919. On the other hand, the busy bits and leading pit information for l channels read into the transmission register 913 are added to the D terminal of the flip-flop 919. As a result, if the busy bit is on, flip 70 toggle 919 is set, its output Q is applied to AND gate 925, and when line gate signal LING is off, gate 925
and enters the busy counter 921. In this way, when the state in which the leading bits of all channels of one frame are on continues for several frames, the contents of the busy counter 921 are counted up by the number of frames. If there is even one empty channel in one frame,
Flip-flock 919 is turned off, and its output Q resets cipisy counter 921. When the count value exceeds a predetermined value, the busy counter 921 outputs an output when all channels are busy for a predetermined number of frames.
It is applied together with ING to an AND gate 927, and the output of that gate 927 enters the transmission selector via an OR gate 929. This makes it possible to forcibly turn off the busy bit in the circuit switching area of the information sent by the transmission selector 916 when complaints that all channels are busy continue for a predetermined frame.

Next, abnormality detection in the packet switching area will be explained.

The first channel signal 8TCH of the packet exchange area enters the AND gate 924 together with the clock signal CLKII)
, the output of which is applied to the C terminal of delay type flip 70 toggle 920. Information on the leading bit of each channel is added to this flip 70 tube 9200D terminal in the same manner as described above. 7 lip 70 knob 920 is the first channel signal 8
If the busy bit is on at the timing of TCH, it is set and its output Q becomes "1". If the output Q is "l", the AND gate 926 outputs the end channel signal TECH.
An output is generated at the timing of the busy counter 92.
Enter 2. If there is a channel that is empty even if it is L channel in the channels of one frame, the flip-flop 9
20 is reset, and its output Q also resets the value of the busy counter 922. When the all-channel busy state continues for several frames and the count value of the counter 922 exceeds a predetermined value, a busy-off signal is output from the AND gate 92B at the timing of the first channel, and this signal is input to the transmission selector 916. As a result, the busy bit in the packet exchange area sent from the transmission selector 916 is forcibly turned off.

According to the above-described method of the present invention, multiple channels in one frame are allocated as dedicated areas for transmitting connection control information, so data transfer channel setup and termination requests are not required when a transmission request is made. This has the advantage that settings can be canceled quickly when the settings are changed.

The above-mentioned embodiment has been described (hereinafter, when one channel is constituted by a total of 10 bits of 8 data bits + data validity indicator bit + channel empty indicator bit, it will be abbreviated as 10-bit method below).

However, when only the following terminals are connected, 8 bits for one channel is sufficient.

(1) Voice (telephone) information 7 bits) PCM + channel empty indicator bit (21 data 6 bits + data valid indicator pit + channel empty indicator bit (3) The packet uses only the first bit of the first channel of the entire packet. It is used to indicate occupancy, and the data portion of that channel is 7 bits.From the second channel onward, all 8 bits can be used as data.

The method of configuring one channel with 8 bits using the methods (1) to (3) is hereinafter abbreviated as the 8-bit method. FIG. 13 shows the bit allocation for one channel according to the 10-bit method and the 8-bit method. In the figure, B indicates a channel empty indicating bit, A indicates a data valid indicating bit, and V indicates an unused bit.

The methods described so far in this embodiment can be applied without essential changes even if an 8-bit system is adopted.

In the following, a switching means for implementing the present embodiment with one type of hardware by switching between the 10-bit method and the -8-bit method will be described.

Whether to adopt a 10-bit system or an 8-bit system is determined depending on what kind of terminals are connected to the network system shown in FIG. When the system is started up, either method is determined by a switch or a signal from the processing device 300.

In order to realize the above-mentioned switching between the 10-bit system and the 8-bit system, the frame synchronization section shown in FIG. 4 is changed as follows.

Synchronous bang generator 101. - Number circuit 102. Synchronous counter 106. Decoder 107. Clock counter 114.
A new decoder 115 for 8 bits is provided in addition to the existing 10-bit decoder 115, and is called an 8-bit 710-bit switching signal C or lower signal 0CTET. ) Change the settings. The signal 0CTET is obtained from the switch or processing unit 300 at system start-up. Decoder 115
In the case of the 8-bit system, the output clock signal CLKII is a signal that becomes KIK when the clock counter 114(7)i becomes 4.5.

Alternatively, by adopting a circuit system that can be used in both the 8-bit system and the 10-bit system, for example, the synchronous counter 1o6. The clock counters 114 are turned on and off to turn on and off the signal OC'TET.
It is also possible to make the bits perform any operation.

Furthermore, the entire circuit shown in FIG. 4 may be provided separately for the 8-bit system.

FIG. 14 shows an embodiment of a transfer control section to which an 8-bit/10-bit switching function is added.

The operation in the case of 8-bit system will be explained below.

Of the 8-bit data taken into the reception register 403 from the shift register 402 at the timing of the clock signal CLKI, the empty/occupied indicator bit Ao2 enters the selector 1400 together with the empty/occupied indicator bit AOO in the 10-bit system. If signal 0CTET is on, bit AO2 is A0
Output as 0'.

(t#), whether the 8-bit method or the 10-bit method, bit A00' is the vacancy indicating bit for that channel.

Signal BUSYON given to busy control circuit 407
.

set or reset by BUSYOFF,
Alternatively, the occupancy display signal (AOO") which has not changed at all is taken into the transmission register 412 at the timing of the clock signal CLK+I, and then enters the selector 1401 together with the vacancy display signal "AO2" in the 8-bit system. Selector 1401 sets bit AOO" to AO when signal 0CTET is on and it is not the second or later channel of the packet.
2". The signal indicating that this packet is not the second channel or later is an inverted version of the signal CHN2 representing the second channel obtained from the head timing circuit 701 in FIG. 10. Signal 0CTET
is off, that is, in the 10-bit method and in the 8-bit method, bit AO2 is
” is output as is as A02'.

When using the 8-bit system, passing bit AO2'' as is as A02N' from the 2nd channel onwards is 2.
This is to secure 8 bits of data from the channel onward.

In the end, I added two selectors 1400 and 1401 to 8
By using this in the bit mode, the processing of busy control, transmission/reception data, etc. in the transfer control section can be the same regardless of the difference between the 8-bit and 710-bit systems.

Air occupancy information pin) The 8-bit signal with AO2# is
transmission shift register 41 through the nickname selector 414
3 at the timing of the clock signal CLKm. In the case of the 8-bit system, a serial output is taken out from the 8th bit terminal in the middle of the 10-bit shift register 413 prepared for the 10-bit system. The selector 1402 is
When the signal 0CTET is on, the transmit shift register 414
The output of the 8th bit is selected and becomes the output of selector 1402, and is sent to transmitter 418 in FIG. Signal 0CT
When ET is off, the 10th bit output is selected and sent to transmitter 418 as well.

FIG. 15 shows an example of the configuration of a part of a terminal control section having an 8-bit/10-bit switching function, and shows the parts added to FIG. 8A.

First, when transmitting data from a terminal device, selector 1
500 is the signal 5 in FIG. 8A when the signal 0CTET is on.
It functions to output the output signal 5DOI from the flip-flop 516, which is preset to REQ, as a data valid display bit 5DO3' in the 8-bit system. This selector 1500 allows the terminal device to select 8 bits 710
If the data valid indication signal is output as the signal 5REQ regardless of the bit, the data valid indication signal will be output at the bit position corresponding to the system being used at that time.

Next, when the terminal device receives data, the reception selector 5
8 of the signals RD or IND selected by 20
The data validity indicating bit RDO3 in the bit system is output as RDOI' to the selector 15o1. As a result, the terminal device side can know the validity of data by detecting RDOI' regardless of the 8-bit/10-bit format.

As a result, by using the selectors 1500 and 1501, the terminal device can input and output the data valid indication signal to the same bit position in both 8-bit and 10-bit cases.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram for explaining the overall system configuration of the method of the present invention, FIGS. 2A, 2B, 2C, 2D,
Figure 2E, Figure 2F, Figure 2G, Figure 2H, and Figure 2J are schematic diagrams for explaining the frame structure in the system of the present invention, and the second construction diagram is an explanation of the operation ft of the circuit switching function of the system of the present invention. 3A and 3B are configuration diagrams showing an embodiment of the node device in the system of the present invention, and FIG. 4 is a configuration diagram showing an embodiment of the frame synchronization section in the system of the invention, 5A and 5B are block diagrams showing one embodiment of the channel control section in the method of the present invention, FIG. 6 is a block diagram showing an embodiment of the processing unit section in the present invention, and FIG. FIG. 8A, FIG. 8B, FIG. 8C, and FIG. 8D are block diagrams showing one embodiment of the transfer control section, and FIG. 9 is a block diagram showing one embodiment of the terminal control section in the system of the present invention.
FIG. 10 is a block diagram showing an embodiment of the link control section in the method of the present invention, FIG. 10 is a block diagram showing an embodiment of the packet control section in the method of the present invention, and FIG. 11 is an implementation of the packet control section in the method of the present invention. FIG. 12 is a configuration diagram showing an example of the frame generation control section in the method of the present invention, and FIGS.
This shows a case in which a bit system/8-bit system switching function is added. Fig. 13 shows an example of channel bit allocation in a 10-bit system and an 8-bit system. Configuration diagram showing an example, 1st!
Figure S is a configuration diagram showing one embodiment of the terminal control section. 100... Frame synchronization unit, 200... Channel control unit, 300... Processing device, 400... Transfer control unit, 500... Terminal control unit, 600... Link control unit, 700...・Packet control unit, 800...Packet interface unit, 900...Frame generation control unit, \J1 figure'lfJ z -RoF12 F3 figure! FJzcFigure 152E 2ndFFigure 8I-'Mad yfJz This time 2H figure v5zJ figure'lfJ z Engineering times, 1! Dan system Arrived at the meeting side, Douyaburuno V, 8, Ri! To@Chisumi ・、Hatobiji+17 ・Channel 1'& Tsu- 上上1fJ4 IM Ial 冨 s A 傑%5B fig = ￥J6 fig'yfJgD zuen 13 Wariguchi ■Tamaguchi

Claims (1)

[Claims] 1. It has a common signal transmission path and a plurality of communication node devices connected to the transmission path, and at least one of the node devices has means for repeatedly generating and transmitting a large number of channels at a constant period. In the method in which each node device performs data communication through the channels, a plurality of consecutive predetermined channels are used as areas for transmitting connection control messages among the plurality of channels, and the messages are transmitted at least to the other party. 1. A data communication method comprising an address of a node device, a connection control code indicating a distinction between a data transmission request and a termination request, and a channel number used for communication.