JPS5821945A - Data communication system - Google Patents

Abstract

PURPOSE:To perform the data communication with high efficiency, by providing the transmtting and receiving channel registers, a coincidence detecting circuit and a mode register at a terminal control part and then transmitting or accepting contents of the channel register to or at a common bus. CONSTITUTION:Each node device includes a transfer control part, a terminal control part corresponding to the terminal device, and a common bus that connects the transfer control part to the terminal control part. The terminal control part contains a transmitting channel register 502 which stores the number of the channel to be transmitted, a coincidence detecting circuit 5 which detects the coincidence between the contents of the register 502 and the channel number of each bus within a bus, and a mode register 504 which shows the result of connection between the register contents and each bus within a bus. The register 504 transmits the transmitting data to the transmitting bus within a bus or to an internal bus when the circuit 510 detects the coincidence. Then the receiving data is fetched from the receiving bus of a bus or from the internal bus when a coincidence detecting circuit 511 detects the coincidence between the receiving data and the contents of a receiving channel register 503.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is based on a data communication system, and in particular, connects a large number of terminal devices to a common transmission path, and applies IA to a method in which data kJA is received in a time-division manner between these terminals. .

In recent years, office automation machines (hereinafter referred to as ``9''), which are designed to improve the productivity of office workers, have been attracting attention. In the past, it was rare for an OA to perform one separate, supporting task for the patch office 4, but in the future, for example, 4
Rather than involving child files, e-mail, document collection, and so-called data processing, the automation of the four-shift office work is being constrained and slowed down.

With the rapid development of t-based multiplication communication technology such as moving blades, optical fibers, and light emitting diodes, the possibility that low-cost digital transmission can be applied to familiar networks is increasing.

With such a technical background, there is a lot of confusion, scolding of fax machines, and stories! , word processor, personal computer, each piece of data is 5tA4! Attempts are being made to realize a comprehensive network system that allows free data communication between terminals through common IM transmission sIK connections.

However, in order to realize such a network V, the following problems must be solved.

In other words, in this type of network system, a large number of node devices are connected to a common loop-shaped transmission path, and information is exchanged between the terminal devices connected to the node devices. When there are multiple terminal devices connected and information is to be exchanged between them, two channels of the loop-shaped transmission path are dedicated for transmission and reception, and information is transmitted via the transmission path. It is very wasteful to do so.

An object of the present invention is to provide a synchronization method that can address the above-mentioned problems.

In order to achieve such an object, the present invention connects a plurality of node devices each connected to a plurality of terminal devices through a common loop-shaped transmission path, and connects a large number of channels to this transmission path at regular intervals. In a data communication method that repeatedly transmits information and sends and receives channel information between terminal devices,
A common bus that connects each node device terminal control unit,
The common node is the 10th node that transmits the channel number being received.
)(S) and reception for received data from the transmission path)(S and
The terminal control unit has a transmission bus for transmitting data to the transmission path and an internal bus, and the terminal control unit has a register for storing the number of the channel to be transmitted, and the contents of this register and the first bus in the common bus. A detection means for detecting a match with the bus channel number, a mode register, and when a match is detected by the detection means,
Depending on the output of the mode register above, the transmission data is sent to the transmission bus in the common (common) bus or to the internal bus.
It is characterized by having a control means for taking in received data from a receiving bus within a common bus or from an internal node.

First, the overall system configuration of the method of the present invention will be explained with reference to FIG.

In the figure, 1 is a loop-shaped common transmission path C1, for example, an original fiber/() is used. 2 is a node device connected to this path, and its r1!L details will be described later. The node device has 32 to 64 fl1 per loop, for example.
m of which at least -III has the function of generating a frame consisting of one synchronization coverage area and an information channel area. Reference numeral 3 denotes a terminal device, such as a facsimile machine, a word processor, a personal computer, an electrician combiator, and a data terminal device such as I1 and I1.

This terminal m is per 11- node device, and the array is 8 to 3
291 is connected. Therefore, in the above example, terminals with a loop transmission path length of 256,111 to 2,048@ will be connected.Of course, the number of these devices is only an example, and the It goes without saying that there are no restrictions.

Next, the seven frame groove configuration in the time division multiplex communication system of the present invention will be explained.

In this #5 #jil method, C is the bit string information is transmitted to the above-mentioned looped transmission path 1, or a continuous pit cell with a certain number of bits, which is called a channel here, and the number of channels is a certain number. 4d and 9# are called frames. This frame is generated at a constant repetition period if the transmission sequence gt is constant.

A frame according to the present invention is composed of a synchronization area X and a 1#-1d area Y, as shown in 42 people 1.

For example, 4 channels are assigned as the synchronization area X and 11A
The H channel is formed from the I channel HIO bit (used as the M area) in this embodiment.

The repetition period of 7 frames is 125μl (8Kl) in this example.
It is surrounded by (g).

Therefore, data arrest is Kt-10MbG1.
The number of channels of the frame is 125 channels, 32Mb PIk
That's 400 channels.

A 10-bit bit pattern for synchronization is inserted into the valley channel of the synchronization area. This bit pattern is i#
This is likely to be the case with the less frequent bit patterns that appear in Sobato 111 reconnaissance area Y.

The information @ communication fi4 area Y has a different 7-ray AT4 configuration depending on the exchange and packet exchange Falongchi.

Fig. 28 Fi Ll = 1 gan converter, 7 frames at one time,
Figures 2C and 2D show the bottom of the frame groove when the packet Se speed gradient is large, and Figure 2B shows the 7V frame configuration when both pressures are mixed. The construction of each of the 7 frames will be explained in detail below.

Frame configuration when exchanging subtitles As shown in Figure 2B, the frame when exchanging l- is as follows:
Synchronization area X%-d j71J cape packet-machine A and times I
It consists of a range A and a range B.

The beginning of the 7th frame is a fixed synchronization character (a bit pattern of 0 bits per character) for identifying that it is the beginning of the frame.In the synchronization area X for transmitting t-f4 from the h-multiple channel. The next two areas are the connection control packet area A and the circuit switching line area B, but these are placed consecutively, and 6n can be placed in either order, and the above three areas can be placed in one frame as a whole. It is also possible to include something other than i.

The large connection control packet area contains the addresses of the destination node device and terminal device to which data should be sent, the originating node device, and the terminal j! Channel 4M in circuit switching area B, which is used for transmitting and receiving data, is used to transmit so-called control #f#Il in packets.

This switching control packet area A is composed of 16 channels A, .about.A1-, as illustrated in FIG. 2F. Each channel is formed from 10 bits, with the first bit A.
. is used to display the sky height of the connection control packet area A. In other words, the frame repetition period t'125 μm (
8KHj), it is possible to transmit a maximum of 8/(8) different communication t# reports as vessel control tIt information, but when using this large connection control packet area of 1e, indicates the empty state of this area by setting the A, bit to @o#t when it is not used. tS, this connection control packet area A is only used when setting a channel for data transfer between terminals and when canceling the setting, etc. This period is used only for circuit-switched channels.

2a-th pick of channel in connection control packet area A)
AI is provided preliminarily in this embodiment and is not directly related to the present invention, so the symbol @ is omitted.

The 8 bits from A to Aoo of each channel are data i'
FIG. 2G shows an example of the relationship between each channel A@~All of the control packet area and the information transmitted via that channel.

-A is used for rounding to transmit address information of a node device transmitting data to channel AI.

is used to specify one of the terminals currently stored in the node device. AH is the address of the destination node device when transmitting data t% AI is connected to the O node device, and channel A is used to transmit the address information of the destination terminal. @teeth,
It is used to transmit connection control messages that distinguish between data transmission requests and termination requests. Channel A1 is data 1
The specific channel number t in circuit switched area B used for carrying out the t11 transmission is used for the 11 II O transmission. Channels A and ~AtS are used to transmit various parameters, but they are not directly related to this invention, so their explanation will be omitted. Nini, this channel person~An
' can also be used to indicate the incoming call on the channel in use.

Channel A14 is used for transmission of check codes. IFlie transmits the result of constant OR processing on the data of the channel person ~ All as a check code, and the receiving fJ111 performs the same arithmetic processing on the same data and checks the correctness of the nine transmitted data. do. Channel person 11 is used for transmitting status information. For example, when the data destination node device receives data t, it carries predetermined information on this channel A and sends it back to the source, thereby causing the source node device to receive the data 6i1t4'. e can be done.

- 10,000, circuit switching area B connects multiple terminals thI through channel t specified in connection control packet area A above.
It is used by friends who exchange information with a mutual threshold of 1 m.

This rotation crosses the m-region Bloc for any channel B.

#4 is made from B, , B ham B . As shown in Figure 2H, each channel consists of 10 bits and C op
1 lower 8 pins) Bow to B... are allocated for data transmission. The first bit B... is used as an empty indication bit to indicate whether the channel is empty or has already been used for one time. The second bit B. is used to indicate whether the 8-bit data of the channel is valid data or invalid data. The valid/invalid bit I3@t of this OP# signal allows the data speed to be set to Al1, which is easily explained below in 1 hour.

As mentioned above, in the method of the present invention, the period t of one frame is selected to be, for example, 125 voices m (8KH), so the amount of data that can be transmitted in one second on one channel is 8 bits x 8 = 6
In the present invention, each channel is used as a unit, and even if a terminal handles extremely low-speed data, when there is a transmission request from a terminal, the 14th channel is assigned. Therefore, if the terminal data IIIJL is lined up, it will be 5
In the case of ultra-low speeds of 0b/1b, even if one channel is allocated, the data to be transmitted will only occur once every 64 to 15G frames, or about 8 times per second. Even if 7 frames are repeatedly generated, using the channel of that frame is enough to transmit ultra-low speed data in 10,007 frames at a rate of 1 tL. Therefore 1
When layering one channel, 7 frames with data on that channel and frames with no data at all are repeatedly generated, resulting in ξ. If there is, B@ indicates the own bit as valid, for example 11", and if there is no data, B.1 bit indicates 1, for example @l □
II is set. Therefore, B@, the @1"O period of the data represents the data speed. It is possible to send a message with a file size of 64Kb91 or more.
When transmitting 4-luck data money, the f-μ ridge channel can be used to deal with the valley surface. If you do it, I M
bpI (It is good to use one U16 channel for a copy containing D-encounter data.

Next, I will explain how to remove data using the 21st method.

Direct transmission from the terminal Kenkyu 6 ↓ Hanode A direct is the 1 of the opponent's 4th
Create a destination address from a III4-like address (9th and 9th digits are 髫鈷sigō). The address of the valley node is determined in advance by a known method such as assigning a fixed rc111 address.
Ru.

Next, it is empty in Channel B ~ BsCJ of Ichichi Kakitsune Area B.
If the display bits (Be・, B1・, B, ...) correspond to the fth channel (n, t=101), that channel?
tlk display (11" if lined up). As shown in the 42G diagram, the 1-city U-use packet should be 7 ohm!'j!
% reduction, I will give you a lecture on the 1j groan packet. At this point, the code indicating the search for the hunted channel A and 1ζ is stored in the channel A, and the value range corresponding to the value range (C is the data for the hunted channel tI number τ is stored) be done.

Once the 1i44 control packet has been created, it finds the empty 11iIl packet range Aτ and transmits the packet (this will be referred to as the #!1 packet).

The above-mentioned evil voice of the people in the area is as described in +giJ.
・It can be identified by seeing Jζ.

The 4t-waiting packet μ father 1d node interprets the contents of the packet, and first checks whether the terminal that has accepted the request is not in use, and if it is not in use, it is not given. It nine accents for channel 1 & issue (channel person so data)
is set to the terminal located at the above node. This-
Due to the setting of channel number ★, data sent through this channel t- than p1 will be delivered to the terminal. The response packet information indicating that the processing of the channel A foot is completed in the node device of the target is created.
This packet (referred to as the ntm2 packet) is sent to the transmitting node device.

Sending node! After confirming the delivery of the packet 1#g1, lJt waits for the reception of the second packet of response information.
After receiving the second packet - constant μ-ming and p sending +
At the end of N11114, a start instruction is issued.

On the other hand, after confirming the delivery of the Stripe 2 packet representing the response information, the N-node device immediately issues a start instruction to the terminal. At this point, an incoming call using the same channel has already been set on the terminal side m part of the 7tII hidden node device, and an end request has already been received! Information exchange between the two terminals is continuously performed at frame period intervals through a designated channel in area B.

When a certain frame is being generated and the data to be transmitted has not yet been generated at the terminal, the validity indicator bit (for example, B...) in the channel is set to @O# to receive 0IV4 node device. t- informs the user that the data in the 7 frames is invalid. In this way, by using the validity display bit, it is possible to perform automatic data resetting on a self-help basis.ft'X, M
As mentioned, it comes out.

When a [4 completion request is generated from the end of the data transmission fg 11414, as in the %# description, create packet information warning the completion request based on the 7 format shown in the 20th kA with -. This packet t# rut is transmitted to the receiving node device. Both nodes * 1ItW and 1 send a stop instruction No. 11 t- to the terminal, and l! 11! Channel t in use - Release. In other words, the fast old channel sets the first bit of the channel in use to @ojl, returning it to the empty state, and the receiver 111 releases the set channel.

The nine controls described above are executed based on instructions from the processing M&direct within the node A cliff described above.

Frame structure during packet exchange The frame during packet exchange consists of a synchronization chain acid X and a packet exchange i!, as shown in Figure 20% and Figure 2D. It consists of A-area.

The 1A reconnaissance area X is used to identify the beginning of the frame, and is similar to the 7th frame at the time of a line break.

Packet father JA area is 42D evil like all information person 11
It may be one packet 5e achievement area, or the second
As shown in Figure C, am I (4'ctk) is divided into keratopaternal conversion regions and used.

As shown in the dZJ diagram, each packet area is pre-assigned to information to be transmitted on the valley channel from 41 channels, as shown in the diagram.

Of course, the stripe diagram only shows one row, and the packet format and address assignment can be determined by other methods as well.

In this example, the first two channels D・ml) Ik are used to transmit the bucket) t-transmit tM, i.e., the originating address information is transmitted, and the next two channels DI # L) I are used to receive the packet and receive the packet through I11. In other words, the destination address information is
1 will be given. The addresses of the node devices are assigned to the channels D, D8, and the addresses of the terminal devices are assigned to the channels D, Ds.

Channel D, the following four consecutive channels D4 to D, are'
Allocated for data transmission. One of the last channels
:) 1σ channel L) L-tit, channel D・~D
t′L%jl allocated for the check code of the information of t→
[Byte Dt is allocated for status.

Note that the valley channel is composed of 10 bits, the same as the 5g2F code, and only the most significant bit of the first channel D is used to indicate the empty space in the packet exchange area. 8 bits determine the content of the customary message.Next, the operation of data communication using the packet conversion method will be explained.

In response to the Xa concealment request from the transmitting terminal, the 91-included IS source node Tetsuoki waits for the ASDF packet range to be received, uses the mapped range as a wealth indicator, and sends /(kerat information to the transmission path.

Each node w411IL checks the destination address D in the packet 1-# track, and if it does not match its own node address, directly forwards it to the other θ node. When the destination address of channel D matches its own node address, that node device performs a receive 1# operation.

The receiving node JJ&B transmits packet 1# to the receiving layer terminal connected to it, and also carries status information indicating the injured person on the terminal channel D of](Kekerato's ll1k). , and sequentially transmits it to the next node device along with other information. When the packet 1 # can travels through the looped transmission path and returns to the sending node device, this sending node device sets the channel DoO@ll address to its own address. Since it matches the node address of
The empty space indication bit D... of the packet area is set as an indication, and the transmission is completed.

The transmitting node device inserts Il! after the orbit. You can check the normality of the transmission by checking the status of the Kerat information.

Above, we have described the frame structure during one-line conversion using the present 9a light method and the foot exchange time, and the respective data communication 11i methods.In the present invention, data communication can be performed by appropriately switching between the two conversion methods. You can also do one 7
It is also possible to create data exchange fl & range and packet exchange area at the same time in the frame, and to perform data fission in such a way that the data range and packet exchange area are omitted.

Figure 142B shows a frame (47 frames) in the case of simultaneous VC realization of the line father fl&l-large and the packet father exchange function.

This frame's synchronization area X% - 4-way control area A 1 time! I
11 Each bit 7 format in the parent A-area B and the packet switching area is shown in Figure 42B~, (as it is the same as the 2D area, it is omitted from the explanation.
, D may be in any order, and may be divided into rows in the packet switching area.

The third AvjA shows an example of the overall configuration of a normal node device for realizing the data 4 concealment method according to the present invention.
o is a frame synchronization section, 200 is a channel control # section, 300
is the processing unit, 40G is the transfer control, soo is the terminal control
Required, 600 is link control unit, 700 is packet 11JI
Ihd, 80 G is the packet interface section, 100
G is a terminal device, 110G is packetization! I device, 120
0 is an optical loop transmission line, and 130G is an end path.

In this 1f4 area, the frame synchronization unit 100 identifies the same 1Ati4 area at the beginning of the frame from the received tg signal sent from the loop transmission path 120G, and clock timing indicating the beginning of the frame and the beginning of the frame content channel. i1 No. t-Create and send to other parts.

On channel t11J Ocho 200, he gave instructions for the 11 father exchange area of 7 reams, which was separated from channel j area in 7 rem 5, and then controlled the operation of one node and wiped out evil. I will do it.

The connection control section 4's program system, such as the IJ period setting process, is performed in the part where the connection control section 4's IJ period setting process is performed using the 4-Seikoku 300μ, the micro combiator, the main unit, etc.

The transfer control unit 400 receives 1g of human power from the loop transmission 1200 and sends/receives it to and from 4 predetermined terminals 1000, etc.
Rin, who performed the replacement highlight of No. 1g, loop transmission line 12
Create a transmission signal to 00.

The terminal control unit 5soo performs transmission and reception with the corresponding terminal control unit 1i1100G, f, transmission control unit 400k
(The transmission/reception data between D is controlled, and the channel sound and electricity in the %m6th frame are stored at the end of the process.

The link system # section 600 performs -d control of the line 5e and packet reception processing 4. The packet control unit 70G is a bucket)X! It has a basic command i that is essential to 1d and 1d, and performs tasks such as detecting address matches, searching for empty channels, and creating transmission/reception tie ζ blowfish.

Control with packetization bag 11110G when packet interface 5soo has one packet exchange range+i
control of signals, transmitted and received data, and storage of packets and area A.

The terminal path 1300 includes these A11lIelOO~5O
O004t-Connect and send/receive far from each other? 1 (serves as control).

In this kind of development, when a received signal comes in from the loop transmission line 1200, the transfer fee is ``$400 and the received signal is 1g''.
In tla4L, 7 frames IAffIS100,
The first synchronous f1 signal of the V-me is identified (from the receiving 1jlfli signal) and sent to receive frames and intraframe channels.

Channel control @5zoo creates channel number 1 according to the timing from the frame synchronization unit 100 and sends it to the terminal bus 1300.
It is determined whether or not the error occurs within the 4- exchange ml range from No. 4+g, and the same is sent to the terminal path 1300. Then, the link control unit 600 receives from the channel number signal from the channel control unit 200 that the 6th channel is at the end of the successive control packet range. It is determined whether or not it is possible to complete the process and sends the packet to the #tl# unit 70G.

Now, the escape device 30G detects a request for transmission g1e from the terminal head r1t100G and issues a request to the terminal control unit 500. In the terminal 11tIls+etitssoo, the empty input bit of each channel inputted by *L from the transfer control unit 49400 and the time Ils from the channel control unit 20G are transmitted.
@ symbol indicating φ in the v transformation region
Search for the empty command channel in the e-domain area, and when it is found, send the channel number signal at that time to the terminal system mm5oort.
c.Receive and store the transfer fee, and transfer fee #-400 plus 1d.
No. t - Sends the empty 4 bits of the channel to C1 vs. 6! 1! It is displayed and sent to the loop transmission line 1200.

In the place Jiji1*aOO, create a destination address as a predetermined fixed address for 1if4 reception from the terminal device 1000, and use the destination address as your own address 1. - Read out the empty channel ring tone received from the system # section 500, create one bond request code, etc.'f: Compile the connection control packet based on the monk dit control packet format and create the connection control packet 1 Link control 5ao
I will send it to o. At the same time, when the local device 30G issues a communication request to the link control unit 600fCFs, the backt system # unit 700 sends fjj! Beyond the continuation control Bakut area - Channel Og! Checking the 4 indication bit, if the empty car indication is 6, it sends a signal to the Gyuri system # section 400, sets the empty car indication bit of the first channel to m indication, and sends it to the loop transmission jl12GG. At the same time, the link control @600Kfi1 is sent to send the already set m1ld and am packets to the transfer control unit 400, and the packets are transferred to the loop transmission line 1200 as packet transmission [14 rhymes].

The connection control packet sent to the loop@transmission path 1200 in this way is received at the platform node 1d.The operation is such that the data in the area is sent from the transfer control unit 400 to the packet control usi1M15700, and there , checks the match between the destination address and its own address, and if a match is detected, 1 starts the link 600 and sends -i.
Itlljm unit 6 links the connection control packet data
00 has settled in, and the escape device 300 further reads it.

The processing unit 300 interprets the contents of the read-only connection control packet and determines the terminal length rIL100 for which the connection is requested.
Check whether G is in use or not, and if it is not in use, send it! A control packet trP is created including a response 1# track with the 1ft-destination address as the node, and is sent to the link control unit 600 along with the transmission 11 request and end. Hereinafter, in the same way as the sending node device described above, an empty connection *u# packet inquiry N
Look at "C1" and set the two eyebrow display bits to 1.7 Also, insert the created connection control packet t into that area and send it to the packet transmission path 1200.
In CI&T300, it was sent to the U.S. channel honorary title T--
Required for the end of Kunne fi11100012)/d end 11t
Control ffl$ 500 Ki & constant.

- In the fslif farm node device, the self-transmitted packets are loop-transmitted by the M1200t-- and returned to the 9:00 PM B11IK transmission control unit 400, where most of the data sent is 11! The packet IIJ Mito 700 determines that the address matches its own address, and the transfer control unit 4
00Kffi is sent to set the 04A indication bit of the next channel of the 1st control packet response area to the state.

On the other hand, when the 1 send 1 g 1 t J node device receives the Komakura 1-Obakut indicating the response sent from the Node glue node device, the Pakut-Misaki section 700 detects that the destination address matches its own address. Then, in the same way as described above, the connection control packet is received by the processing device 300 via the link control @ 600.The processing device 300 checks the response information 11 and sends the terminal 9! l
#ill Node A directly transmits 1 information to the loop transmission path 1200 and learns that it is 9. Similarly to 14 and 9, the 2 blocks of the preceding channel of the control packet value range Set the indicator to full display and issue a start command at 1G00 at the end of 4 b d! In the s + d visit node Eiro, the start finger from the processing device 30G is full of algae, and the prayer ends from dllo00 to 11!
Data is sent to the fourth WU1111 section 50011C.

The terminal control section 50o detects whether the set channel number matches the channel control signal from the channel system #1 section 20G, and if - Atsushi is detected, the terminal device 10
Transfer data t from 0G to transfer control gIs400, d
! D% The sent data is inserted into the corresponding channel and sent to the loop transmission line 1200.

On the other hand, in the first exchange node station, the transferred data is received by the transfer control unit 40G, and the end control unit sends it OOK. It is determined whether the signal matches the 0 channel ★ skin number from the channel system 4820G, and if - desire is detected, the % reception data is sent to the input terminal device 1000. At the same time, it is possible to send data in the same way from the receiving node device to the receiving node device.In addition, data can be sent from the receiving node device to the sending node device using different channels. It is also possible to perform transmission using t rt.

Next, in the 1Fs skin node setup, the terminal device 100
When the transmission 11 termination request is sent from G to the processing unit A direct 3oo, the processing device 30o sends a connection control packet tt instructing disconnection.
1i, and sends a message to the colleague mentioned above to the receiving channel side node device and instructs its terminal device m1000 to stop.

Or, in vc% transfer 1d-node 1, process #
4130G sends a channel release request to the terminal control unit 5-00, and when a channel call arrives at the number of the occupied channel (when the numbers match, the transfer control unit 400 issues a signal tone Xa for that channel). g! Set the line indication bit to C. Release the channel.

Note that in the % terminal system #$500, when the set n9 channel number matches the received channel scan signal, the terminal device 1oo
If the data has not yet been received from o, send the data with the validity indication bit set to non-display, inform the s'W hand that the data is invalid, and send it to any of the 1000 terminal devices. It is designed to handle processing speeds such as

In addition, in the transfer control section number OO, the link system # section 60
A check code is created by performing a predetermined calculation on the data of the channels of stripes 1 to 1441 of the Itori Misaki packet sent from G, and the code is applied to the 154th! The first part of the connection control packet that is inserted into the first channel and transferred, and the first part of the received connection control packet.

Perform a predetermined calculation on the data of the 15th channel, check the -pt of the received data, and send the IIs to #l16.
It has the ability to be inserted as status information into the 41st channel and transferred.

- In the unlikely event that packet 5e is to be sent, the packet interface gs o of the transmission node device detects the leading channel of the packet transmission area and sends it to the packet control unit toovc. The packet control unit 70G sees the empty channel indication bit from the 1 transfer control unit 400, and sends a signal to the transfer control unit 400 to send a signal to the empty channel indicating bit t-m of the first channel. Display. At the same time, packetization! Loop transmission M120 from 11111fiIS400, which is composed of 110G and set in packet interface section 800.
Outputs 0gi.

The receiver 111 detects the first application channel of the packet by using the channel signal at the packet interface 81100, and activates the packet +ulj control unit 700. In the packet 1111 part 700, it is detected that the destination address of the US9 packet data sent from the transfer '+11 control unit 40G is its own address, and the lll
3Ik to the packet interface 51100. The interface unit 110G receives the s-r packet data and then sends it to the salt treatment apparatus 300.

When the packet interface 11800 detects the end channel of the packet exchange area, the node device performs the end operation and determines whether it is sending 11! (When the Kerato data is sent to the loop and goes around N11200 and returns to C44, the packet control unit 700 receives the packet data from the transfer control unit in the same way as in 1, and combines the originating 1g address with its own address.) If it matches, the transmission control unit 4
00, and empty m & at the beginning of the corresponding packet.
Figure 3B shows an example of the overall configuration of a node device that uses node axes and generates frames to realize the data retroactive signal method according to the present invention. The difference from the Jila A diagram is that the transfer control unit 40G is divided into a transmitting/receiving unit 400A and a transfer part number 00B, and a frame generation IfrII control unit 90G is provided between them. It is.

This node device plays the role of the normal node device described above.
At the same time, 15t circulating around the loop transmission line 1200
The cost of generating a 74M frame is 6.

On the frame generation side #ll@900, the loop has been completed) V-mu 1 transfer 1 tltll 111 section 400 transmitting/receiving section 4 frame generation via GOA thIJfsJ Chung 90
Write one frame in the memory in 0, generate a clock for one-way transmission 11i, create a synchronization range pattern at the beginning based on the clock, read out the above memory in mirror order, and write the frame. to form. Transfer the Id(Nara) Ifil
Transfer 11 copies of III to $400B. The same excitation as in 4 and others is performed, and the i# information to the next node is sent via the transmission/reception unit 4GOA of the transfer control unit.

In addition, the frame generation control RS900 should have the ability to constantly monitor, that is, the vacancy indicator bits of one channel in each of the circuit switching area and the packet father jfl area should all indicate 4fi. It is certain that there is one
When it is detected that a delay of more than alIa continues for C, the empty/busy indicator bit ft5Ii of each channel serves to automatically display the empty signal.

Since the other operations are the same as those of the fold W in FIG. 3A, the explanation thereof will be omitted. Hereinafter, a detailed explanation will be given of a specific example of the formation of each part of the three-wheeler.

(1) 7-frame synchronization unit 100 Figure 4 shows frame synchronization 810G (-J
j! Enter the number that indicates the m column.

In the figure, No. 1ig TIM and No. 8ROυT are No. 1g created by the receiver and shift register as detailed in FIG. Loop myj! The serial received FD information sent from the first complex 1200 to the transfer control unit 40G is demodulated by the second 1114, and the data 50 % of tie building confidence - 1 =) TIM is f1i! will be accomplished. This tie ζ Fugu No. 18 TIM receives t′ in series.
# information is stored in the shift register sequentially. The parallel output of the shift register is counted by signal 8ROUT.

In frame synchronization 4100, a synchronization pattern is generated! 101
The synchronization pattern in the 7-frame synchronization area set in Soften and set the match trigger 70 and 103 (and goo) 104 & 1 when the -interval is detected.

This set of 70 clips and 103 clips, and gate 10! As soon as the synchronization counter 106 is operated through St- and the number of stitches for the subsequent number of stone bits is started, 11 of the synchronization counter 106 corresponds to the number of bits for the l channel (10 in this embodiment). Decoder 10
7, the AND gate 108 checks whether the contents 8ROUT of the shift register of the transfer control unit 40G are included in the synchronization pattern again. The match flip-flop 103 and the synchronization counter 106t are reset through the synchronization counter 106t, and a match between the contents of the shift register and the synchronization pattern is searched again as soon as each bit is received.

If the same pattern as the one in the shift register continues to change, the one-grain slip is still set, and at that time, the synchronous character counter 110Kff1 is output from the synchronous counter 106, and the 9th character matches the synchronous pattern. When a channel is received continuously, the number of characters is counted in the synchronous character counter 11G. As mentioned above, if the number of channels in the synchronization area is 4, then the counter 11G
When the first shift is 3 and the content of the synchronization counter 106 becomes 3, for example, when the synchronization character of the next 44 channels is detected, that is, a match is obtained over all 4 channels. Gold decoders 111, 107. Detection is 1 and when the timing is TIM, it is and goo)
112 to produce an output 1 synchronization 7 lip 70 knob 1
13t - Set, indicates 4 that synchronization has been established, and in the way the set is output, 109t - Match clip flop 103, synchronization counter 106, synchronous character counter 110t - All are reset, and output of ANDGOO) 104 to stop. And bar pattern detection *l
Ii meeting is stopped to prevent ζ7 from mistakenly regarding the P3 content of the following 4 information channels as a synchronous channel.

- The clock counter 114 is driven by the reception timing signal TIM and the shift register output 8RO
This is used to create a clock that indicates the timing at which the UT indicates the IIf information for one channel.

For this purpose, when the AND gate 112 detects synchronization OK, the content of the struggle counter 114 is forcibly set to the position 3 of the synchronization counter 106, and the synchronization counter 10
By making the 1st shift of 6 and +ti of the clock counter 114 the same, phase matching is achieved. On the other hand, the output of the clock counter 114 is input to the decoder 115, and when the value of the clock counter 114 is α1, the decoder 115 outputs the clock 1'11 CLKI, and when the clock counter '11sCD'dl is 5.60/ (, outputs the i'g CLK
Outputs the number CLK. With these CI and Kl, as will be described later, the output of the shift register is set to firefly 1! The information is transferred to the register, and the following four processes can be performed in units of information for every six channels. On the other hand, even when CLKI-II is out of synchronization, the clock counter 114 is always operating, so it is always output and does not interrupt the processing of other parts of the node table.

When the synchronization knob 70 and the synchronization knob 113 are set, the frame IA unit 100 transmits the channel 'III control module 20.
Channel act message to 0 @C) IACT'l! Activate the channel counter in the 0 channel control unit 200, start the number of stitches with the timing of clock No. 18 CLKIT, clock l1iT → the number of C1, 11, that is, the number of channels in the frame (in the same J&lJ captive area) (Excluding channel a)
t-itta. When the channel counter reaches a value corresponding to the number of channels in the information area (Y in FIG. 2A) within the frame, the end channel signal E is sent from the decoder.
The ND CH is sent back to the frame synchronization unit ~lOO, and the synchronization is performed through the computer game) 116.
3t reset.

Accordingly, synchronization detection as described above starts.
A check is made again to see if there is a synchronous character pattern at the position where 1 bit is received in the shift register of the week control 114400. Accordingly, a check is made to see if the synchronization area of the next frame is normally recognized 15 following the end of the previous frame.

Due to missing bits in the transmission information on the loop transmission path 1200, bit leakage due to noise, etc., there may be cases where no synchronization pattern is detected in the synchronization 1 failure of the next frame. In this case, the channel information in the frame is not correctly g*ed, so while synchronization is immediately reestablished, the process in the meantime is 4t-
It is necessary to take some measures such as stopping the synchronization, and for that reason, this synchronization error must be immediately detected.

Detection of this synchronization error occurs after the p synchronization rip-drop 113 is reset by the end channel 11iENI (ENI) C) 1 indicating the end of the previous 7 frames, the value of the clock counter 114 becomes 0, and 9 tying occurs. In other words, at the timing when all the information of the synchronization channel at the beginning of the synchronization area of the next frame is input to the shift register of the transmitting side '1118400, the coincidence with the synchronization pattern is not detected, that is, the coincidence flip-flop 103 is reset. Then, an output is generated from the AND gate 117, and the set output of the out-of-sync tree flop 118 is the out-of-sync 1g No. 8.
TOUT=Send to liH channel control #200. This knob 70 knob 118 is reset by the output of the own knob 70 knob 113 when the synchronization is completed.

(2) Channel control unit 200! The s5 figure shows an example of a concrete groove bottom of the channel system 4g200.

As mentioned above, when synchronization is established in the frame synchronization block 100 and the channel act signal CHACT is output, in the channel amsgoo, the frame synchronization unit 100 also performs AND GO by tying the four polarized signal CLKI. At 201t1, the channel counter 202 starts at the needle at-N.

The contents of the channel counter 202 are '1#' in the frame.
When the channel ridges in the channel ridge in the 4th area are reached, the decoder 203 outputs the end channel 11i ENDCH. When the channel act signal C)j AC'l'IN from frame synchronization IEIGO becomes active, the channel counter 202t is reset by performing the input 204t-, dl.

As will be explained later,
When node act knob 70 knob 205 is set, channel incoming call 1 is passed through AND gate 206t.
It is sent as the d-number CHNO to the 130G path.

On the other hand, the interface! 1i1207 is the processing device 300
The data written to the register selected from 1 data t-dy! The circuit for protruding sip, its specific 4
The arrangement is as shown in Figure 5B.

The ink 7 process circuit 207 shown in the diagram $5B includes a
Makoto tl1300 to 4th tree pass 130074, synchronization signal 8YNC, layer not arrived/number TMNO, register number REGNO% successively, input control signal/W, data D
&], and when the same #A signal 8YNC is input in the matching circuit 208, the terminal call assigned to itself from Odori Shuyogo TMNOt-Kan unincoming call Kamio@209 is received. Compare and when the two match, C in response to read/write control signal B/W.

A/Toge-) 210! or generate output from 2111
The write decoder 212t or the read decoder 213 is configured as A, and the process is completed! I! Write select 1f1 to the register corresponding to the register signal REGNO from the device 300.
No. W8 or read select No. 111 No. 88 is output.

At the same time, the sender 1 gate) 214 or the receiver 11 gate 215 is also selected, and the data D from the processing table is written to the nearness A order V register using the write select signal WS. Take out the 8th valley and send it to the 4th place. Note that what is specified by the register number REGNO is not limited to registers, but also memory 111i! t-
It can be whatever you have.

In FIG. 5A, the output channel register 216,
! ! ! IM end channel register 217, out-of-sync-clip flop 218ν and node act flip-flop 205 register signal REGN from escape device
This is selected by O.

A write signal W8 is sent from the device to the line start channel register 216 and the line end channel register 217 through the interface circuit 207t-4.
t or B8, the lowest channel of the A area of the frame and the highest channel layer number are predetermined. In addition, the clip flop 205 has a node Al
When creating ltkm, data D is set at the timing of write select No. 18 ws.

Then, the matching circuit 21 detects that the contents of the channel counter 202 match the first channel register 216.
When detected with 9, s! 2I# Interchange! l & area alip drop 22G't set. Maku Channel Kakunta 202
When it is detected by the circuit 221 that the contents of -1 end channel register 217, the detection IN number t-j is detected.
After the delay circuit 222 waits for a certain period of time, the trigger 70 resets the trigger 220i. When clip flop 22G is not set, node act 7 lip flop 20
5 opens the JbtL (Antgame) 228 in a set pattern, generates the line gate signal gLING, and completes the %terminal pass 1a.
A place to send to oo! In the fim300, in order to know the wiping of the synchronous αZrL down-flip 70 knob 218, the interface circuit 207t-1 sends the read select signal ttst-, buffer age-) 224tll@I゛C, the contents of the flip flop 218. If: Input and delay path 22
5, the flip-flop 21 is activated by a signal delayed for a certain period of time.
8t-Reset.

Also, register 216 or 217 (
The DG'3 content is read out through the buffer gate 226 or 221t.

(3) Escape device aOO FIG. 6 shows one of the concrete constructions of the processing location 3GG.

The l & ma equipment a equipment o has an escape part 300m and a conversion part 300B.
The processing 11S300A includes at least 1L set 301s memory 302 and I(s) 303.

Then, the processor 301ν and the memo 17302 are connected to the nine paths 303, and the r address strobe No. 11 A8Y
NC, address signal ADR8, read/write system nIt
No. 1 R/W and data D (I-V)
The g number is input to the conversion unit 300B.

Km@3008't'ti% processjj! 430OA>
- The upper bits of the address layer number ADR8 7 - Mosquito circuit 3
04, and at the timing of the address strobe signal A8YNC, the upper bits of the address are transferred to the address register 43.
Check whether there is an address pattern indicating access to the interface circuit set to 05, and -
If the pattern is n, create the same lA+a number 5YNC. Further, the lower bits of address Al))t8 are sent out as they are as terminal tQTMNO and register layer number -c.

Mae, lead number #li! No. 1 R/W is synchronous 1
At the timing of No. 11 19YNC, AND gate 306
through AND gates 3o6 and 30γ, and buffer gates 30B or 30G11.
Data D is sent and received at 1iv%.

The nine dan signals created in this way are used not only in the interface circuit of the channel control section 200 described above, but also in
It is also sent to the interface circuit of the system #1lsoo, the 9th link control unit 600, and the packet interface 5800.

(4) Transfer 1'ffu (IIlffl $400 7th
1 shows an example of a specific configuration of the transfer fee portion 400, which consists of a transmitting/receiving $40 OA and a transfer section 400B.

In the receiving fl#40OA, the information from the loop transmission line 1200 is received by the snow receiving wI401, and while demodulating the information, the information is extracted from the information (IT? tg issue T
Information is sequentially stored in the shift register 402 by IM timing.

Next, at the rising edge of CLKI from frame synchronization 1i10G mentioned above, shift register 4
02010 bits are set in the output money receiving register 403 in parallel.

On the other hand, the transfer unit 400B sends the valid indication bit and the 2 bits of the l1 indication pit of the output of the reception register 403 as they are to the reception 1d register 404, and also sends the empty head indication bit to the not gate 405 by 4 and 2 bits. Display Il
It is sent to terminal path 1soo as IDLE No. 1. father 5
1! The remaining 8-bit data 1 of the output of the register 403
The #can is sent to the bucket control unit 700 as an IN address ADDR for address verification, and is also sent to the -1 input of the status selector 406. Finally, the other input of the status selector 406 receives the status from the packet system #8 TATB and the status No. 1 indicating the presence or absence of the work 2- to be described later. In this status selector 406, Send data is selected according to packet control $700 to 0Xf-fix*v8TATSEL.In other words, when there is no signal, the receiving register 4030 output CJ11! is selected, and when signal 6111 is present, the other input status signal is selected. 8TAB etc.t-
Select J11.

- 10,000 status 7 V 8 TAT 8 EL Ura is, for example, caught in a situation where it is necessary to quickly change the status to the 16th channel while receiving a non-assertion control packet area, and status 1 g 8 TATBJ? and the output of the zero adjustment output 417. The selected output of the status selector 406 is 9!
1 is sent to register 404. Uke 1po register 404
Now, manual data is set using the clock CLKM from the frame synchronization section 100. Out of the output of the receiving register 404, the busy indication bit is inputted to the busy control period Nt40'lv, and the other 9 bits are inputted. ! ! The data RD (end of 4) is sent to the step 1300, and is input to the mode selector 408. Also, the 8-bit data information of the ei bias register 404 is output to the FIFO memory 40.
9t-mX input to register 1. In the FIl'O memory 409, the output sound register 4 of the reception register 404 is
The data is stored in 09-1 and 409-2 at the timing of CI and KI, and in 409-3 at the timing of CLK summer.

Therefore, the receiving 111 data output from the FIl'O memory 40G has a length of 4 and n9 times for 2 channels, and is input to the link control unit 600 through the packet receiving data PAKD. ξHere, the FIFO memory 409 was used for the first time, and the destination address in the control packet was the third channel.
sThe destination address is the own address t44J
This is because I need to get excited and absorb the received data.

The other input of mode selector 408 includes terminal path 13.
Transmission data 8D from 00 is input], and when the mode select rg signal MOD8jL from the packet control unit 700 is turned on, the selector 408 selects the transmission data 8D'fc14 and selects the mode select signal Nut)8g.
When L goes off, is % Uke 1? Select the output from register 404.

Busy City ++ 9407 is one of the received information when Busy On No. 11 BU8YON from the packet control unit 700 is turned on! Forcibly set the two-way display bit to the employment display, and Busy Off Ii! r No. BU8YOFF When turning $ off, the empty block display bit is forcibly set to empty display. At other times, the busy m199 circuit 407
There is a function that outputs the signal from the ci bias register 404 as it is.

Next, busy system # circuit 407 & mode selector 40
8 is set in the transmission register 412 at the timing of the clock CLKI. fsl! Of the output of the register 412, the 2 bits, the 'Hall indication bit and the valid indication bit, are used as they are for the sending and receiving register 413v of 5,400 people.
ζ input δ is input. On the other hand, the shallow 8-bit data report is input to the check selector 414 and the operator g+Q 415.

The check register 416 is a packet control unit 70.
Reset from 0 by li BCCR8T first IA at 0
Setting theory, check from bucket control unit 700 -
The operation starts with ta number BCCACT, which operates the AJ16415 and performs an operation between the output of the check register 416 and the output of the transmission register 4120, and as a result, the 0 operation that is set in the check register 416 at the timing of t clock CLKIr is t. We will use a method commonly used to check the 6-channel transmission clearing can by dividing by a constant #. These operations are repeated, for example, while transmitting data on channels 1 to 14 of the continuity control packet range.

On the l5th channel, packet Itlu111a part 700
Check select number 1 BCC8EL from selector 4
14, and in the selector 414, the % calculation - 415 is sent to the transmission register 413.
All pits of the zero detector 417ri and the calculation 4415 are sent to the specified t.
If lis tilt is 0, it has the ability to detect that it is tilted, and inputs L'C to the status selector 406 together with the 8TATB signal.

In other words, the s4 output 4417 detects whether there is an error in the data information by checking whether the calculation result of each bit of the data information of channels 1 to 15 in the continuation control packet area becomes zero, for example. By the way, Ill! The information is now requested from the 16th status channel in the packet area.

ij! iUke 111400AOd+1//x741g a, Kuku CLKllll from Treem synchronization 810G
The output t of the transmission register 412 and check selector 414 is set in the timer ζ of r, and then the content tp is set ζ.
Shift one bit at a time with /ItJeTIM.
It is transmitted to the loop transmission maze 1200 via the device 41st.

9%@UAs mentioned above, the one frame synchronization unit 100 generates clock tie construction even if one frame synchronization is not established, so the received information is always 1 to 4 sent to 9.
It's a lie.

G) Terminal system # section SOO Figure 8A 2 and ABB diagrams show an example of the specific configuration of the terminal control unit 5oo, and the 8th figure shows the basic part 1 8B.
The figure shows an empty channel selection section.

In the basic part of FIG. 8, the interface circuit 501
is composed of a circuit similar to that shown in FIG. 5B, and the processing
Sends and receives threshold data.

The transmission channel register 502 stores the channel number within the circuit-switched area to be transmitted, and the reception channel register 503 stores the channel number within the circuit-switched area to be received.

The contents of the mode register 504 are 4-bit information, of which 2 bits 504-1 and 504-2 indicate the path connection method at the time of transmission *! $04-1 is sent via a terminal path of 1300 yen via a loop@send wII1
When sending data to 1200, t-instructs %504-
2 is a terminal path 1 to another terminal control unit in the same node f&
300 indicates a case where data is to be transmitted via an internal path within 300.

The remaining two bits 504- of the mode register 504
-3,504-4 shows the path connection method at the time of -i ura, and the bit 504-3 shows the case where data is received from the loop t=i8 path 1200 via the receiving 1g path of the terminal path 1300; 504-4 is the same node f! This figure shows the case where data is received from other terminals within the same facility via an internal terminal path costing 1,300 yen.

These transmit channel register 5o2, receive channel register 5ossp, and mode register 504 can be set with data by the write select signal W8 from the interface circuit 5o1. The output t9 of the output select signal R8 is input to the ink 7 process circuit 501 via ports 505, 506 and 507, respectively.

Transmit and receive channel registers 502 and 5
03, as detailed in Figure 8B, the timing HTCL of clock CLKI after a hunt request is rarely
As the previous channel number CHN (l change frf) was updated on K-8 and B, an empty channel within the -1 exchange area appeared, and when running, it became difficult to finally register that channel number. .The output of the transmission channel register 502 is output by the AND gate 50g only when the output of the OR gate 524 which detects that either 504-1 or 504-2 of the mode register 504 is set by the transmission instruction is detected. Output 1 is sent to the sea pattern circuit 510.

Similarly, the transmission mode register 50 is set by the t agate 526.
504-8 out of 4 or 504-4 is set, and the output of the channel register sO3 is sent to the AND gate 509. IC times ml! Output to $11.

Note that registers 502 and 503 have an interface l.
Data from the processing device 300 is set via the pl path 501't, for example, when a Sakizuki 111J# packet t-i is received from the other party and the transmission/reception 1d channel number is specified there. Melt.

After data is set in the registers 502 to 504, coincidence circuits 510 and 511 detect a match between each of the transmission channel registers 502 & 503 and the channel arrival signal C) (No).

When the matching circuit S10 detects a match between the channel arrival signal and the sending 1d channel register 502, if the content of bit 504-1 of the card register 504 is 1, the AND gate 512 is passed and the mode signal is output. Sends MODI to terminal path 1300, and also sends AND GO)! ! 13
The contents of the sfJ Patsys game 1114tl #1 send sfJ Patsys game 515 are transferred to the shoulder car path 1300 via. - When the terminal device 1000 has all the transmission data, it turns on the transmission request signal 8RIQ to transmit I (Tub 151).
5 and 8-bit transmission data 8Dt-Se:/)t! At the same time, set the Komeura request flip frog 516 and press g1.
The output signal of 516 is transmitted as the presence @*indication bit to the terminal I (S 1B00 as a communication data SD) together with the dicic data information that the batsagate 514 has opened.
Send to llsiGO. As described above, in the transfer control unit 400, the 1 mode selector is operated by the mode signal MOD8gL corresponding to the mode No. 16, and the transmission data 8Dt-other node! Coincidence output of 14 circuits 51O to be sent to the device? :The signal t-1 delayed by the delay circuit 517 is sent to the terminal device 1000 as the signal 80 in the transmission 6 -1, the transmission 1! Request flop 516K
”Reset. Therefore, if a match in channel attachment is detected before the transmission data from the terminal device 1000 is complete, the send it request 7
16 has been reset, the transmission data 8DO valid member indicating bit is O, indicating that the transmission data t1 is invalid. 1! Terminal device 100011
If the 4th speed is healthy or slow, and the feed + g data is not J9I, C
c is for the non-employment demonstration, and the deceased tree fi filter 1000
There are no restrictions on the processing coupling of 111a.

Next, when a match is detected in the -* circuit 510, if bit 504-2 of the mode register 504 is set to 1, the AND gate 518 causes /(Rough Ab-)! $19t11
41, the above-mentioned dtst data is sent to the internal I(s) as internal s/' space data IND.

On the other hand, it is a coincidence that the output of the g channel register 503 matches the channel WI number from the kansue pass.
11, the next operation is performed according to the contents of the mote 9 register 5040 pits 504-3 and 504-4.

That is, the receiver selector 520 receives the received IJ data ftD# from the receiver I(S) and the receiver IJ data ftD# from the internal I(Sρ), and the selector 520
When bit 504-3 of mode register 504 is 112, the received data selection is selected, and when bit 504-4 is l, internal I (data INDt) is selected. Among the @n9 data, the valid display signal of the 0M young display bit is input to the data information Kurakaku fg A rough 1521 and applied to the M young display bit t and gate 522, and -w<1 511. As a result, the output of the receiver #14 receiver 520 is set to the receiver Ig buffer 521, and the receiver input is set on the set output of the receiver request flop!$23t4. I!Request 1gvILBEQ as 1-direct 1000If
- Sending and receiving the contents of the receiving patch tour 521;
Send it to 4th tree-1 1000 as eye data D. In the terminal device 1000, when the reception request No. 1 ILREQ is received, the reception (KOK customary aOKk- is sent back) and the reception M14.4C tripping tag 528 is reset.

In this way, 5t-data t-is transmitted to the terminal device 1000 only when the valid indication bit indicates valid by the AND gate S22.
04 Only when sent as complete data by this device -y
It is possible to send and receive data without being affected by the speed of the heating cart or noodle rack.

Next「ζ148B-Yoshi, ffi?-rnel迩f'ef
Let me explain by mu'@Ktsui. Although Figure 48B shows only the circuits related to the empty channel selection function during either transmission or reception, in reality, the circuits in Figure 8B correspond to transmission and reception. 2- It will be established.

In such a configuration, when a hunt request is sent from the processing f1130G via the interface circuit 501t, the hunt request trigger 5311 is opened at the timing of the clock CLKI.
277. When the hunt request 7 rippu 532 is set δ, the line gate signal LING indicating a reception in the hunt %tgls5ell- area and the empty channel IDL indicating that the channel of injury data is an empty channel 6 are sent.
B, hunt request 7, the output of the flip-flop 532, and input to the t AND gate s33, and when the above-mentioned hunt condition is satisfied and the run is executed, the output signal t from the AND gate 533 is extended by 4 for a predetermined time by the extension circuit 34, T-channel chalady.

Flip 70 flip 535t-set and reset request 7 rig flip 532; On the other hand 1
When the hunt display knob 70 knob 532 is set, the clock CLKIK opens to the digital gate 536 to obtain 1IN HTCLK', and this signal T-striped 8 person figure channel register 502 also! 03, and at that timing, channels 11 and 16 CI (NOt-Long time no see channel register 502 and nine enter 503, j
l! New. 4. As mentioned above, an empty channel is detected and
When the Hunt Hosui Ripp 70g 532 is reset, it stops register O input operation, so from the electric bridge perspective, the channel number corresponding to channel 12 is stored in the register. Become.

jI#1 circuit 5340 output No. 4 [Inputs into delay circuit 538 through OR gate 537, where it is delayed for a predetermined time by 4, then sent to busy No. 11 B08Y7 and sent to packet system 44700, and busy on Δ No. B08Y (converted to JN) .) of the corresponding channel being transferred with % transfer control 940G! 2! t-m show binding s flJA (04
Hunt Kura's legal status in Tree J & Kō is discontinued. Since iφ1 8t is established, the coincidence circuit 510 in the JIgA diagram is 5110-! ik
j! ! When the message is manually sent to extension@sei 538 and extended for a predetermined period of time by -enjou 538, it is also sent as busy No. 16 BU8Y, and the empty 1 display bit is changed to a command. Note that the one-way rotation jlS3g is provided to keep the tinging sharp.

7 Ritz 7 o Tsubu 535 is set 1 - Hunt is established and sinks, 70 sets come out Nyoha and goo) 531t - Close, mackerel's ﾾnt praise Xt - Fly, 2 channels ^n)
tli/f is stopped.

- 10,000, after the data transmission and reception are completed, the 9th channel is released. According to the instruction from the #1 #μm tin holder 30G, the 2nd select from the interface circuit J path 501 is performed. No. W8tfs issued, 1nd game) 540t-query and release lI request 7rig 7og 541t set by tying of Rita Tsuk CLKI. And what is the content of the channel register 502 or 503 of the 8th person and the channel No. 41 No. f1 CHNO? Wait for the song to be detected, -*A match is detected in the circuit 510 or 511, and the signal C is detected.
When 01N-86 or C0IN-R is output, the output from the AND gate 542 is sent to the delay circuit 543 for adjusting the tie-building shrine for a predetermined time J! ! After stretching, it is OK to show the sky.
DL) imUKt Packet control - syooga is output, busy off signal BUOYOFFt - Transfer control section 400 is sent, and the bit 1IkfR of the occupied channel is temporarily set to empty.

At the same time, the release water nourishment tree 70g 541 and the acquisition of the empty channel are Tsubu! 535 and release operation t'pt-complete.

In addition, in order to avoid simultaneous hunt request foreshadowing for the terminal control units with a value of - in the same node device, the grogtsum control in the processing area is made to always perform only one operation, and 'lo This prevents multiple terminal control units from hunting for a channel.

In the above-mentioned 夾mH, we will explain the case where only the fil channel is occupied to transmit or receive gI. Also, the alsc diagram is the shoulder system in this case #
The main part of the basic part 1! It shows one row of Sakaki Sei.

In fact, one channel register 5! $1,552 is ai
It is also used for H and reception, and the contents set in these registers and the channel iEf number small number CHNO -wct--Kuichiro 55! S, 556 detects the match, and when a match is output in the circuit with a deviation of V%, the OR gate 557 outputs it.

On the other hand, the speed of the terminal interface for sending and receiving %! 4! In the rounding of 1, 5SSjIP and 559, which each send a FIFO message for lfM and reception, are set in ff6A &, 6゜The FIFO memory 558 of At the timing of l'II request simple S le IiQ,
Along with the transmitted data 8D, an indicator bit M is stored indicating that the data is valid.

When a match is detected as described above, the detection signal tM
#! For a predetermined period of time, the circuit 560 generates device data stored in the i'IFo memory 558 using the delay number 1. At this time, if data is to be sent, the mode register 504 In response to the same bits 5G4-1 and 04-2, the same #- as shown in FIG. 8A is performed.

On the other hand, when receiving data, the mode register 504
(According to V3 of D bits 504-3 and 504-4, 1 received data RD or internal path data INDt-7 is selected by V vector 520 as described in FIG. 8A, and the selected data is valid. 6 Toki Mori, its data trIF
The contents are sequentially stored in the O memory 559, and the contents are read out in a predetermined tie configuration and sent to the reading terminal device 100G as a reception data file D. Also, corresponding to the channel register 551, an empty data field as shown in FIG. 8B is stored. If a circuit is provided with the output signal HTCLK-1~i (1'CLK-rst) of the controller 536, it is applied to the channel register SSt~552 and its Channel numbers 0HNO are sent to the channel registers 551 to 551 one after another at the timing.
552 and update it.

Further, the OR gate 563 calculates the logical sum of the outputs of each bit of the mode register 504, and only when any bit vC1 of the mode register 504 is set, the outputs of the channel registers 551 to 552 are output to the AND gate 563.
3 to 554 and are output to matching circuits 553 to 554. In addition, the coincidence output 00TN of the coincidence circuits 555 to 556
-1 to C0IN-n are applied to each AND gate 539 and 542.O Also, the output obtained by taking the logical sum of the outputs of each delay circuit 538 using an OR gate is sent out as a busy signal BUSY, and the output of each delay circuit 538 is outputted as a busy signal BUSY. Similarly, the logical sum of the outputs of 543 is taken and the output is used as the blank display OK times signal DL EO
Also, by the read select signal R8 from the interface circuit 501, )(rough gates 561 and 562
In the above-described embodiment, by using the mode register 504 and the internal path, It is possible to communicate between any two cabinets in the control unit at the end of *ao4 in the office, but the detailed explanation of Jin's first del will require @speed control $400 and multiple terminals. Control part! 5OOA
,! With 5OOB! ! ! The turtle terminal path 1300 is necessary for those connections! Na/(s, that is, mode 11 MiJDE O/(s IJOI, transmitting path 1302 for transmitting data SD, receiving path 1303% for receiving data RD s/(s/(s) internal path 1304ν for data IND and channel number Path 1 for signal CHNO
It has 305tW.

Terminal control unit 500A and 5GOB in the same node station
When communicating in the cabinet, the terminal control unit 500A)! Beauty!
50B O transmission f'%$$kV register sO2 and reception channel register 5oao value in each group -
Set c.

Next, the method for setting channel #- will be explained in steps 0-1m. One terminal control unit of the transmission 1d4, for example! $O
In OA, search for empty channels, and when an empty channel is found, the channel number Jt transmission channel register 502
Set to . The processing device 300 reads the 9 channel number set in this V raster 502, sets the same channel number in the reception channel register 503 in the same terminal system gtssooA, and also controls other terminal control 7s.
! i in jOOB! ! 1 and also set in reception channel registers 5Q2jiP and 503. Also, treatment d;
4ri/L8 o o, dermatology S part, 500Aff
In the mode register 504 of i, the receiving section tlJ
t path 130B, transmission 1m is -a with internal path 1304
t- as indicated, pits 504-2 and 504-
3 is set to 1, and in the mode register 504 in the terminal control 11s500B, the received llI is set to the internal path 1304. Sending tgva is as instructed by the sending IJI path 1301, bit 504-1 and! $04-
Leave it at 44-1.

With this, J7% terminal control unit 500 BO sending 1ts590
The transmission information from B is %? as shown in bold # in the diagram @8D.
5 (Ii/(S1302) Transfer control product 4.00
Similarly, the mode signal is sent to the transfer control 4400 by exuding the path 1301.

On the transfer side #tiS40G, when the signal is turned on, the mode of the path 1301 is set to transmit t#1lt-, and it is put on the channel of the Kuwa signal and sent to the loop transmission line 1200. I completed 12001 laps on my way out!
#II is taken in by the transfer control unit 400] Intake 1 reception path 130
3t- to the receiving section 591 of the terminal control section 5GOA.

On the other hand, from the terminal control unit 5GOA to the terminal control unit! When sending all information to 100B, as shown by the thick line in the g80 diagram, the terminal control unit! 5OOAO sending 5rs 590A to sending information 1i
Send to internal path 1304 and send to internal path 1304 of
0 data is received by the terminal system m5500BO reception ff1i591B.

Moreover, the dotted line in the figure shows the route No. 1 in the opposite case to that described above.

The link control unit 600 link system #ttlS 600 transmits and receives packet data (hereinafter abbreviated as link packet data) in the unified control packet area A at the time of the 11155 conversion function j! This link - 1 #To 6000 configuration, II! l
It's packet exchange 5! Except for the +4, drive, and 1-end interfaces of the device that transmits and receives data during I&F, everything is the same.

Figure 119μ shows the configuration of the link control g1 unit 600o as an example. In the same figure, 602 and 603 are registers 69, and the interface unit 5oit- from the processing device ms o o described in q.
Through this, the starting channel number and completion channel code of the d craftsman (hereinafter abbreviated as link packet area) are initialized. Therefore, in the case of a frame configuration such as 2nd Bd, for example, channel number 5 is set in the link start channel register 602, and channel number 2Go is set in the link end channel register 60B. When setting data representing a channel number in each register 602, 603, a write select signal W8 that specifies the address t-i assigned in advance to each register, and data D representing the channel number t to be set.
5AfA is applied by applying 5AfA to the register. Furthermore, when the read select signal R8 specifying the address of each register 602 and 603 is applied, the data for channel number t-X stored in each register becomes /(roughage)608, 609t-, respectively. read out via

The outputs of both registers 602 and 603 are sent to the channel control unit 2.
Channel i1v sent from 00 through the terminal path
Along with the information track CHNO, each match detection circuit 604.6
Added to 0!5. - The intermittent detection circuit 604 outputs an output code when the contents of the register 6020 and the channel arm number information 11 CHN O match, and the start timing circuit 606 is thereby activated. This tie construction circuit 606
outputs 1〆8TC)It to the tie ζ knob synchronized with the request CLKI in the first channel. On the other hand, the 1-huan detection circuit 605 outputs an output signal when the contents of the register 605 and the channel honor information 1licHNO match, and this causes the end tying circuit 607 to be activated. The circuit 607 provides a timing t synchronized with the clock [lCI, Kff in the termination channel.
No. 5 TgCHt-output.

Upon activation of the head timing circuit 606, the advance distribution channel rII No. 8TCH is sent to the later-described packet controller 8700 via the fourth terminal path, and the packet data transmission/reception control 11t is started.

Furthermore, by activation of the termination tie construction circuit 607, the termination channel number TECJ is similarly sent to the packet control unit 700, thereby completing the packet transmission/reception control.

631 is the output t-peak-zero detection circuit when the channel number CHNO is zero 6), and when this output is received, -m side output tf
The f1g16G4,5oso output 7JIJi stop circuit 631 is provided when the link packet area AI is not specified at all, the registers 602, 6
In order for the contents of 03 to become 0, the synchronization area xoia
A match was detected with the first channel number O, and it was mistakenly called Thai Telephone No. 1.1 8TCH.

Used to prevent TECH from appearing.

Next, the packet data transmission operation will be explained.

A packet to be sent is created by the processing device 300.
FIFO for transmission via interface 6011-d
Buffer memory circuit (hereinafter abbreviated as IFO) 612
It is read in sequentially. This post, as mentioned above,
A write select signal WS assigned in advance to the transmission FIFO 612 to specify n9 address t, and packet data Dk.
J: By applying the input function FIi't) to 612 J)
! 1 after writing of packet data is completed
A transmission request No. 111 is sent from the processing Jl device 30G.
This is applied to the ARITUB 70 TUGS 610 via the interface TTLS 601KFI. The AND gate 623 is opened by the output Q of this tree frog.

When the contents of the first channel register 6011 and the channel number CHNO match and the tip tie circuit 606 is activated, its output is sent to the first path as the first channel signal 8TC)1, and at the same time, the AND gate 62
3 is applied. This AND gate 623 outputs the status 11v8TA via the OR gate 625.
Sent as a TA. This status number aTAT person is sent to packet mode mfl17gg, and tinging fd
By multiplying it with '8TCH, it is reported that a p-transfer request has been issued.

Further, a p trigger 611 is set by the output of the upper ml timing circuit 606, and its output Q is applied to AND gates 626 and 628. As a result, the transmission gate signal SGo sent via the shoulder car path tm is only marginal.

On the other hand, the packet 11114 part 70G looks at the 1 link packet area AO destination bit and confirms that it is empty, and then sends it to the fs Ura gate [B No. 8G meeting].

This transmission signal BG passes through the AND gate 626 and is applied to the AND gate 62o. Therefore, while the transmission gate signal 8G is on, the clock signal CLKH is R.
1MF11?061211C input], the packet data stored in the transmitting FIii"0612 in synchronization with 27 is sent out through the 621. This sending data 8D is sent out via the sending path. It is added to the mode selector 408 of the aforementioned transfer fee #1S400.

Also, the transmission request flip-flop 610t is reset by the transmission signal rg 8G. This is a foreshadowing that Hisashi is waiting for his first request.

When the contents of the link end channel register 603 match the channel number CHNO, the ting circuit 607 outputs the end channel 11! as described above. No. TECHt- is sent. This end channel signal 'rgcii is the end channel signal 'rgcii'.
- to the packet control unit 700. Packet control 1
At 1s70G, as will be described later, the packet data transfer is completed and the transmission signal No. 115 SGt is turned off. As a result, sending 11FIF (Goo which was prioritized by X112) 6
20, 627 is closed, and the transmission operation of the packet data of the size of the link packet area is completed.

Next, the reception of packet data sent from the other party's node atit will be explained.

Similarly to the above, in the node device that receives data, based on the instructions from the processing table 30G, the destination channel and end channel of the link back g4 craftsman are stored in the register 602.
, 603, respectively. When the source channel arrival number set in the same manner as described above matches the channel number CHNO sent via the terminal path, the first channel signal is sent to the 8TCHf packet+i control address 700. As described later in the packet fBlj11 section 70G, when a match between the destination address and the address of its own node device is detected, the receiving gate 1119RGt- is turned on.
28, and the transfer system # section 40G is added to the t)Opacket/)day/PAKDU receiving f#FIF0813. Tsuritsubu flop 611 first fi? Since it is set by Yanel's timing, the cyanto gater 28 is opened by the output Q.

Therefore, the reception gate 1M number aG is applied to the AND gate 621 through the gate 628. This reception fit gate 1
While the clock signal G is on, the clock signal CLKTI enters the reception rIl'0613, and the packet data l'AKl! is synchronized with ζn! Revenue! 0 included 1t'L. 5JFIFO61
The nine packet data stored in No. 3 are read out by the processing device 300. When a read select signal R8t designating the address of this reception FIFO 6131 is applied, the packet data is sequentially read out to the gate buffer 617t and the gate 130G.

On the other hand, the receive FIFO 613's overflow Mt''
Brave Ij! The r issue ends with a tie of 4! ! It is applied to AND gate 624 together with the output of 14607.

At the timing of transmitting the end channel signal TgCH, the data stored in the receiving fl FIFO 613 is overflowing.
! If it is 1, the AND gate 624 generates an output, which is sent to the packet controller 700 as a status signal 8TATA.

When a replacement packet area (see Figure 2B) is detected, the flop flop 611 is reset (by the output M of the IgI 607), and the #! The reception process!l is completed.

“1 bit in the status register 615 is set to on by the change in the output of the AND gate 628 being turned on or off.
By reading the specified read select f1 number R8t-yatfjL through the same top gate buffer 61Q of the register 615, the data reception time can be determined. The completion of this reception can also be notified to the processing table 3oo by imprinting processing or the like. Status register 6113-10 read select +lt signal R8 is applied to the reset terminal of register 615 through slow g circuit 616.

Therefore, after the contents of register 615 are read out, the
The target is set.

Next, we will explain the process by which the packet data sent out from the node device goes around the loop-shaped common area path and returns to its own node device.

When the link control unit 60G receives the first channel No. 11 8TCHt-, the 0 address that detects the match between the originating address of the channel with the most paddy and the address of its own node device is sent. This means that the received data is the same as the data sent from the own node device after going around and returning.When the two addresses match, the packet control unit Wood sends the data as described below. End Goo No. 115 TEGt-
Send, this is terminal path 1&! Through this, 1 link control unit 6GOK is added.

This end gate signal TEGrj passes through the NOR gate 629 and ANDGUT) 630t- and enters the AND gate 622. The normal rounded clock signal CLK is passed through the above-mentioned AND GO) 622 and added to the transmission end FIFO 614, and the packet data PAKD from the speed control section 400 is pushed into the transmission end FIFU 614.

As will be described later, this termination gate signal TEG is not on for 6 hours in the link packet area λO-, but is instead on for at least 1 channel period (4 hours) of the address information.
In the picture of 2G diagram, it is A. to A.

(O channel period).

- 10,000, status gate: No. 8 ['ATG is set to be turned on only for the channel period of the status information (12G channel period in the example of the figure).

Therefore → agate signal TEG and status gate 11i
! The transmitter 1 operates to input packet data (PAKDt-4t#) only during the period when any of r No. 8 TATG is on.
1JI completed FIFO614 is % A@ ~A@ and A11
This means that you can look into the channel O data of . At the end of the transmission, send only the necessary information 4R sentences 1g to 6 times. Of course, please include any information other than the above. 1-End! 'IFO
614 may be sent to the treatment facility 300? 1 By escaping the read select note Vt indicated by the address 1 sub-set in the IFIiFO 614], this 0
Data stored in FIFO 614)6
It is difficult to read through 18t.

Packet system # section 70G This section is used to generate timing signals necessary for transmitting and receiving packet data in the packet system #1 KI700t-j, link packet controller, and packet exchange area. Me O [Higashijo, Below, the case of data transmission and reception 16 in the link packet area will be described.

FIG. 10 shows an example circuit 1m of the packet control unit 700.
Indicates completion.

Link 11ylin Iku 600 is also transmitted through the first channel 1m No. 8'rCH and the end channel No. 111 TEC
H is the start timing 1g of the packet control section OO! Ω can be seen in the circuit 701 and the end tie ζ puffer circuit 702, respectively. The tying circuits 701 and 102 of C output the 111 signal synchronized with the first channel and the 4th channel of the t-link packet area, and the tie-building signal which is filled by the 0 channel. The agt of the data explained below is based on the tie-open signal of
The tie electric ring + g number necessary for ti is made.

For the first time, a moth learns about the behavior when transmitting packet data.

As mentioned above, status 1 8TATA sent from link control ss o is packet data O sending.
It means s-seeking. If this request is 9 times, packet Wj
J#st o starts a hunt operation for the empty packet ml area.

First, check the contents of the empty signal IDLE of the link packet and head channel A of the acupuncture area A (see Figures 2R and 2G). 11”), it indicates that the space for the packet is empty, and OR<@o
＃＞Noto1! is based on the idle 11i call IDI, and when E is OR, the AND gate 713 is closed], and the transmission operation is not started, but waits until the first channel comes again.

When the idle signal IDLg is turned on, the output of the AND gate 713 sets the transmission flip 7 signal 705, and its output Q is sent out as the transmission signal SG on the link rtt (Istmeootc). /
The control system 5seoo receives this transmission gate signal 8Of: and sends the 4-bit data t-sequentially of the Kd signal FIFO 612 to the transfer control unit 400 as described in ll11r.1 At the same time, the output Q of the above-mentioned Turi lag flop 705 is 720t.
- Transferred as Mode Select Mitsu No. 1 MOD8gL - Added to @9400.

The transfer control unit 400 is mode select)
When the link controller 600 enters, the link controller 600 sends the incoming transmission data 8Dt.

Further, the output Q of the 7-lip flop 705 is sent out to the speed control unit 400iC as busy on No. 16 BU8YON via the OR gate 719t.

This signal is applied to the busy control circuit 407 in the link packet area A.
2j! ,, % display beep) Ae*k Set to R.

On the other hand, the signal t check reset No. 1d BC generated from the leading timing circuit 701 is synchronized with the leading channel A.
It is sent to the transfer control unit 40G as CR8'r. This 1st BCCtt8T p@send 1tll#400WC
8BCC& of the kFjb block check register is initialized to zero. On the other hand, the shift flip-flop 703 is set by the IH signal at the next timing, and its output Q is sent to the transfer control s40G as the check operation signal BCCACT: Send- G, if this No. 11 BCCAC'l' enters, it will turn amQl
# operation is started to set the output of the block check calculator 418 of lffl$400 to the +g order in the block check register 416.

Thereafter, when the end channel signal 'r E CH indicating the end of the large link packet area is sent from the link control # section 600, the end tie ink circuit 702 is activated. This Igl 702 is the check byte after the data area (channel person t* in s20 diagram) t' the tie to be transferred ζ
Create the Fugunuma number t- and send it to the transfer 111J control number 00 as the P4C check select IN number BCC8EL via the ANDGOO) 718t-. Koi d No. B
CC8B! When iL enters, block check selector 41
4 transmits the contents of the block check register 416 storing the check operation result to the common transmission path on the link packet area-sized check code channel A1- (see diagram 42G). Also, the end tying (according to the tying ink signal from the tying circuit 702) sending 1d clip 7a knob 705
When the output Q of the signal is set to 9, the transmission dart signal 8G, busy-on +Ii No. B08YON, and mode select Ura No. MOD8EL are all OR, and the transmission operation is completed.

Next, the link packet data sent from *+g node A is loop transmitted I! 2), and its own node device K
I'll explain with a picture of a chicken made by wJ when I got M.

As in the case of transmission, the leading channel No. 171 8TCH enters the leading tie ink circuit 701 of the packet control unit 700 from the link control tMI 600 via the terminal path t-, and this circuit 701 is activated. Further, the address signal ADDR, which is the output of the reception register 403 of the transfer control section 400, enters the coincidence detection circuit 710 of the packet control M7oo. - The clause detection circuit 710 is the tie ink of the channel A of the very beginning of the Ri/Kupakket territory craftsman with 1 address No. 48 person 1) DR,
In the actual example of detecting whether or not the address signal of the self-O node device generated from the address generation 5711 is short, as is clear from the diagram A-2G, the first channel A.
Since the originating node address is 11, Jin's address of channel number 5 matches the address of address 7 of address source -711. I went around the loop@處路 and came back to enjoy S9. Therefore, at this time, the data sent by the father is directly inserted into its own node A, and the data is sent to the node A.

First, if the above two addresses match, the t-and gate 71
Pushed into the output of 4 ufd completed 7 Rig 70 Tub 706 set 15n, Ru, C's 7 Ripfrog 7 (Nj's Q is orag) 721t-through, busy or IK No. B
08YOFF is seen in the busy control circuit 407 of the transfer fee # section 40G. Busy control I11 circuit 4G7
1s,, link packet area AO prefecture A...t-
@O" (empty display), so that the regrettable node device can be used for the Pacut territory @At-Nan.

- The tie ink circuit 701 turns on the end clip flop 707t when the address information It (As-As channel) of the linker craftsman area is sent to the tie ink sent from the transfer control 19NS400 to the link system # section 600. The timing 17i is applied to the set terminal S and reset terminal S of the signal t-707. Status clip frog 70 to tie ink sent to link Fltl # must 600
8'1 ON Timing inertial signal 7 Lipfrog 723, AND GO) 7164 is used to mark the set terminal 8 and reset terminal of 4L gold 708.
Speak.

The outputs of the clip flops 707 and 708 are sent to the link 11i control circuit 600 as the end gate It1 TEG and the status signal 5TATG, respectively.

In the link control unit 600, as described above, the above group) 1ii
During the period when No. 1'rEG and 8TATG are on, Rimashi, Teyane A/A・~A- and AHO information are included.
OK, it moves like it's vomiting.

In addition, as mentioned above, Tsuritsubu 70 Tsubu 707° 7081
- Creating a tie ζ puffer signal that turns on only the predetermined 0jjA can be easily accomplished by using a kakunme or shift register t as the tie powering circuits 701 and 702.

Next, the 0 excitation order when receiving the backt data coming from the originating IM node will be explained.

In this embodiment, the link packet chain acid AO43 channel A (see Figure 2G) contains the source node address t, so the data *i 41! If so, detect a match between the address t* of the 1st channel and the address of the own node device and 2! i-I have to-.

First of all, for the benefit of Jin, the timing episode 6'101 is on the timing system that is synchronized with the channel ^8 above.
#JMJ to t&gegoo 717 - 10,000, farewell it
f1m Zheng 40G sends Andres fil vague A DDR and the address of own node device are compared by the first detection circuit 71G n1 If both addresses match in the proverbial tie ink of the above channel, Its output passes through AND gate 717t- and receives 1mt7
Marked on the o set cup) M4 is placed.

The above tie ink for both addresses will be sent to I! This means that the 9 packet data is the information of the own node device light. Therefore, for the rounding packet control ts700 and control # section 600 to start the reception operation, the output Qt of the knob 70 and the output Qt of the knob 709 - the receiver 111 game)
Send as tit number RG.

The problem here is that each node ** will know whether or not to receive I (kerat data) or not. 143 channel's 4th destination node address 1# will be received and sent at the time of execution, but
If it is judged that Uke + G is good, -41 channel person /
Source node address and s42 channel AsO addressed to 14
This means that it is necessary to include the original terminal address as well.

For this purpose, the second channel A・# A@OI#
Bucket data 1 must be stored temporarily in the transfer control unit 400 and OFIFO memory 409 described in 4J.
&: 2 channels are used to spread the data from the m1 channel to the party glt town. ritJs bakut system #11700), Uke 1
When ggut + IM RO enters the link control unit 600,
In synchronization with this, the transfer control 9400
From lX16 channel AI (Kerato data PAND
Enter the link control unit 600 as 9, receive 1!1 FIFO 6
13/C and tnc included.

-Man, tying I! ! l error 702, tie ink No. 18 synchronized with channel AH of status byte of link packet area A, this nf near/toged door 2
to be applied. After the receiver 117 logic drop 709 is turned on, the AND gate 722 is narrowed by the tie ink of the channel As-, and its output is transferred as the status select No. 16 8TA'L'8EL 1111#dts400
Send to. In the transfer control 440G, the status select number 16 8TATaELt-When received, the status 1# report 8TATBt which indicates the reception status is sent to the above channel Al.
1 and sends the packet data to the reception register 404. As can be seen from the figure mG10, the above status byte number 8TATB is the logic 4 output tj! of another status byte number 8TATA and the end channel + d ambiguous 'I'ECH! By delaying the reading iA in the delay circuit 04 for a predetermined period of time, it is deducted. Also, the status code 8TATA is the status t of whether or not the receiving PIF0613 has overflowed when tTic)i and the platform t are taken as shown in the 9th section.
-Represents.

That's all oak! A is fs of link packet value artisan data
We have described the tie ζ blowfish 1 control in the case of receiving I'IlO, but it is also possible to completely i!
! ji, b, O, and the explanation thereof will be omitted.

Packet interface ss o.

The packet interface 9800 is
100 and other devices; data OXa reception (1 control session is carried out) in the packet exchange value range D (see FIG. 2C, cause 2D);

The configuration and operation of this interface 5800 are approximately the same as those of the link control 4600 (see Figure 9).
Only the different cities will be explained below. Figure 11 shows the frame TG or control S in the packet interface @800. Other parts are 1s9.
It is the same as the figure.

The packet switching area is clear from the g2c diagram.
In the case of the Im example, setting in the maximum number area t frame is 6 in the town uB. Therefore, it is necessary to prepare four sets each of the first channel register and the end channel register σ register. Therefore, here, the four-word register file memory 822t-
I am using it. First channel part 8104! : 4 completed channel part 82012) II is the same as 6. Here, as an example of subtraction, the first channel register part 810,! i! Do wings.

The first channel codes of the 41st packet exchange are set in the register file memory 822 in sequence from the youngest to the VJ stage. This setting is effected by a write select signal WS for determining the address of one memory 622 and data Dt indicating the arrival amount of each previous channel from the processing device. The signal l from the processing device 30G enters the decoder 811 via the interface section 801, is decoded here, and then set in the register file memory 822. i
&Oita-a41'' If the evA area is not divided, set it to -#t-0 in the decrement register.

Only one node act (N0L)EACT sent from the channel control unit 200 is applied to the decoder 811, and only when this is off, the channel register signals arrive one after another, making it possible to get into trouble.・This node act hidden vN
As mentioned above, UDEACT is used for rounding to control the no-rgi device to start or stop the WB operation.

When the contents of the register file memory 822 are read, a read select signal EL8 is sent from the 518I4 device 300 to the right and is applied to the access selector 826. This access selector 826 applies a read select signal a8 to the selector 823 only when node act No. 16 N0DEACT is off. Memory 822 p1! The retrieved data passes through the selector 823 and the buffer gate 827 and enters the I&JI recording device 30.

After the initial settings are completed, Nodeac X1 N0DEAC
T is turned on, and control of packet data transmission/reception is started.

First, the signal CHNO, which is sent from the channel control m5zoo (1) and represents the amount of arrival at the channel, is sent to the zero detection circuit 826f/Cm.
Can be seen. Co? When the detection circuit 825 detects that the channel arrival amount is zero, the detection circuit 825 suppresses the output of the -line detection circuit 8240. As stated in the Imperial document, when no packet value range is specified, the register file memory 822
The circle 8 is set to 10# to prevent the -wc side output circuit 4 from outputting an output at the timing of the channel number O in the synchronization range.

-1, zero detection - The output of the path 825 is the access counter 8
28 reset i manually, counter 8280 inside it-
Reset. In other words, the access counter 828 is Oo-t-aS during the period of 1!1jlA area X of the frame. The contents of this access counter 8280 are seen by the access selector 826.

Since the access selector AZARCT is applied with the node act signal NOL)gAcT, the 1d number ("0") t input from the address counter 828 is output as is.The output of this access selector 826 is sent to the selector 823. register 7 isle memory 8
22, selection number 1d. Accordingly, the lever register file memory 8220sO# is read out, - Kinyoko output circuit 8
The input of -1 of 24 is marked. To the other manpower? An channel number signal CHNO is applied. Ryojin Riki 1
If the g number matches -&Kitase! ! The leading timing circuit 802 is activated by the output of the l path 824, and subsequent operations are performed as the link control @6000 operation and IWI.

The output of the tie 111M802 counts up 1 shift of the p-ac 7 scakunta 828 and becomes 1.

Therefore, Arashi is now preparing to detect the first channel t of the 2nd packet father exchange area when the 81st # of the register file memory 822 protrudes by 3%.

The above is an explanation of the detection of the first channel, but for the end channel, the details are omitted.

Frame generation control unit 90G Frame generation control unit 9000-a certain one tsjl1
Refer to Figure 2 t-S and gn.

This 07 frame generation control $900 is applied to one node of the node devices connected to the loop-shaped common transmission path.
<This is provided at the frame control node a) and the transfer 1u control tl$400 shown in Fig. 7 is provided.
2) The I & signal clock oscillation 901, which is caused by the threshold between the fs receiving 440OA and the transmission TMS 400B, is the primary source of transmission lock in the data communication system of the present invention. The output of the transmitter 901 is used as the transmission clock for the transmitter/receiver Ms.

The output pulse of the sending clock data 901 is first 1.
The zero base is attacked by Tsukukakunta 902.

Although the 10m Kurotsukukakunta is used, in the implementation row of the present invention! This is because the channel has more than 10 pits. The output of this clock counter 902 is further stamped on a clock counter 903, where it is used in the frame control node device to generate four clock signals CLK.I, CI, K.
alI and sacrifice synchronization-ll! 906 and frame memory 91212) A tie signal for access is generated. The above Rimatsuk + No. 11 C1,! , I[ are four-way signals CLK1 . I [and 1w100 million, for example, out of 10 bits of 1 channel, O
Between bits and 61 bits, and 6%/% of 6 bits and 6 bits, respectively @l#, and other than that @01
This is a simple answer.

On the other hand, based on the tie ink No. 11 generated by the speed control unit 4000 reception-401, the frame synchronization unit 100 (
bA4ria tsu1+1! NtCLKI, II.

And the sake number sent from the reception register 403 is,
It is synchronized with the receiving clock, and the sending clock of the speaker is 15 A.
m! It changes asynchronously with the output of 901. Therefore, this 7 frame generation Ivllnt! In lI, the above link If! I
9 CL K I # u s B R notes etc. t and a
The transmission clock CLK@I is phase-aligned with the transmission clock CLK@I, if.

To round off the phase adjustment, first, the clock from the claim synchronizer 5 1IIt! ! The signals generated in the tie ζ under and 5Ja (11 clocks CLKdO rises) are rounded up and the signals generated in the tie ζ puffer and taσ are uniformly tied.

On the other hand, the received signal CLKI and the channel act signal CHACT are applied to the AND gate 930 and the tζO gate is applied to the AND gate 930.
) 930 (2) Output is 11! ! channel kakunta 90
Added to 8. When the channel kakunta 908 counts the predetermined channel at-, the decoder 907 outputs the end channel signal ENDC.
) it - occurs.

The contents of the dfm direct and reception register 401 of the dog control channel kakunta 908 are determined by the output tie voltage of the RR1 engineering subcircuit 906.
It is set to 17.

Furthermore, the buffer registers 909 and 917Ilc4
The contents of t'L9 are sent to 1d clock CI, and... are set in the reception registers 91G and 918, respectively, at the timing of .

The rising lock decoder 903 outputs the clock CLK・!
A vague value that is turned on from the falling of O to the falling of CLK @
A signal t that is on for 1/2 of the time of the %ml channel
The address selector 911 and the write gate 914 are mated. Accordingly, the address selector 911 selects four outputs from the two inputs 5'G) receiving register 910 and selects the output from the address input terminal 9 of the 7 frame memory.
Add to 12. At the same time, the light gate 914 is rounded and the receiver 1
The fI register 9180 output enters the input data chain of claim memory 912. Therefore, the contents of the receive register 918 are stored in the frame memory 912 at the address indicated by the s i+71 channel register 9100.

The frame memory 91m has 1stio bit and 1
The sardine channel of the frame has 1 ft. of TSA that can store 1 ft. of i#*t. In other words, it is possible to store all the information for 1 frame - 1/2 of the other 1/2 channels in one channel fsi! Clock CL K
From the falling edge of en to the falling edge of CLK@I, the address selector 911 selects the output of the channel counter 904 from among the two inputs, and selects the output of the 7-frame memory 912.
Add to the address input terminal of. Above channel kakunta 9
04 is applied with the feed 1W1 signal CLKaK, and the channel a'f for sending is in operation. In the frame memory 912υ island, the address 11 indicated by the channel kakunta 9090 value is extracted, and the transmission clock C
At the rising edge of I and Kel, IIs is set to register 913.

When the number of stitches 11 of the channel counter 904 mentioned above is suitable for a predetermined value (last channel scan code), its +t trX is reset by the output of the decoder 9050. On the other hand, the above 2
! 11 register 913r(d)I! I feel like I'm being pushed out
In addition to the output of the 1 synchronization pattern 915, the 1M selector 91g is added to the transmit selector 916, and the channel cuff 904 is in the synchronization area (0 in this example).
channel ~ 3 channels) is displayed.
J period pattern generation 5915 (2) Output ta is output, and when other chain acids are indicated, the contents of the transmission register 913 are transmitted. This transmission selector 91612) output ha
a, Transfer control corridor 40G @include S<transmission rule. In other words, the information *aa received by the reception register 403 is phase-aligned with the timing of the input signal by the above-described operation, and then is sent to the sending section ikf'L.

In addition to the above-mentioned precautions for phase alignment, frame generation #Ill 90G is abnormal! ! ! Look at it. In other words, when the condition in which all empty d1 bits of all channels indicate ship display continues for more than a certain threshold, it is determined that there is an abnormality in the system. 6. This function is used in the 12th
Among the circuits shown in the figure, the function realized by the structure of 919 to 929 (Iri 411) will be explained below. This will be explained separately from abnormality detection in the exchange area.

The timing detection of the turn exchange vA area B (see FIG. 2B) is performed by the channel I control 8200 ::JP, and the timing of the turn-on exchange area BO period 1- and the turn-on gate po No. LIN
G is sent. The output of this circuit gate Δ is applied to the AND gate 923 along with CLKII which is set to clock 1, and to the C terminal of the gate 919. - 10,000, including old register 913 & Cd Izushire fI
The information of 111 bits of busy bits for -1 channel and the leading bit of the relay is added to the D terminal of the above-mentioned trip lop 91G. This -button pidgey bit is on and 6tL is 7
Lipstick 91G is set, its output Q is marked MJ on AND gate 925, and the output signal is output (if No. 1).
When ING turns off, it passes through gate 925 and enters busy counter 921 . In this way, after all the channels in one frame; seven frames in which the A pit is on continues, the busy counter 921o Uchitani is counted up by the number of frames.
Even on the channel, when the channel of Sora Rokusho comes up, frig 7o
When the knob 91G is turned off, the p busy counter 921 is reset by its output Q. When the busy counter 921 exceeds a predetermined value, the busy counter 921 registers Ns when the total of all channels busy is equal to a predetermined +l [number of frames].
The output signal of C, which outputs an output to the meeting, is the line Goo) 1tL No. L
It is applied together with ING to an AND gate 92γ, and the output of its GUT) 927 enters the transmission selector via an OR gate 929. As a result, the percentage feed 111 selector 91 only when frames in which all channels are busy continue as a set frame.
It is possible to forcibly turn off the busy bit in the circuit switching area of the information sent out.

Next, abnormality detection in the packet exchange area will be explained.

Top channel 464' of packet switching area! 8TCH is connected to AND gate 9 along with clock tM-4CLKT1.
There are 9 people on 24, and the output is 920
Added to OC4 children. This flip 7 subjects '7920
The information of the first bit of the valley channel is added to the D11 child section at the same speed as above. Clip 70 Tsug 920 is the first channel No. 11 8TC)i.

When the busy bit is on, 6n is set to 1.
Then the output Q becomes @ 1 #. When the output Q is 11"O, the AND gate 926 terminates the end channel 1g T E C
H, Thai scolding produces output % This is busy counter 9
Enter 22; bs If on the instep of the channel of one frame,
! Even in the channel, when the channel of Soshushu is turned, 7 rig 7e
The r knob 92G is reset, and the busy counter 9220 is also reset by the sootB force ζ. How many frames are all channels busy?
When the tftx value reaches a predetermined time, a busy-off IJ number is issued from the AND gate 928 at the timing of the earlier application channel and enters the transmission selector 916. The history hit in the packet exchange area sent from the C-register transmitter 916 is forcibly turned off.

In the embodiment described above, 8 bits of data + data fertility indication bit + channel g! , II! The case where one channel is configured with a total of 10 display bits (hereinafter abbreviated as 10-bit system) has been described.

However, when only the following undesirable terminals are connected, 8 bits for one channel is sufficient.

■ Audio (voice) r'ftm 7-bit PCM + channel empty l & fill-in bit (2) data 6-bit + data w9JJ fill-in bit + channel g! The data section of the 17th channel is made up of 7 bits, and only the 1st bit of the 111th channel is used to indicate the total number of bits in the packet. From the 2nd channel onward, all 8 bits can be used as data.The method in which one channel is made up of 8 bits using the 8-bit method is hereinafter abbreviated as the 8-bit method.Figure 13 shows the 10-bit method and the 8-bit method. by l
In the diagram showing the channel bit allocation, B is the channel vacancy display pit, M is the data valid display pit),
The bits not used for veil are shown.

The method described so far in this book *Run example is that even if you adopt 8-bit Manbu, you will not be able to buy f#, and you will still be able to get out of town without any change.

In the following, a switching means for using a 10-bit method and an 8-bit method with a single type of hardware will be explained in one practical example.

Whether to use the 10-bit system or the 8-bit system is determined by what kind of terminals will be used in the network system shown in FIG. When the system is started up, the switch is determined by the signal from the IIji device 3 device 0.

In order to realize the above-mentioned switching between the 10-bit system and the 8-bit system, the frame synchronization section shown in FIG. 4 is changed as follows.

Synchronous bang generation order 101. - Toshikazu 102, synchronization kakunta 106, decoder 1o7, clock counter 114%
In addition to the existing 10-bit decoder 115, a new 8-bit decoder is installed, and switching is performed using an 8-bit/10-bit switching signal (hereinafter abbreviated as signal OCT switch). 0CTET Mori, when starting up the system,
obtained from the switch or oversalt device 300. The I-check signal CLK■ output from the decoder 1150 is set to 45 in the case of the 8-bit system.
1C14C is the 1H issue. By adopting a circuit system that can be used in both 8-bit and 10-bit systems, for example, synchronous kakunta 106, clock kakun! It is also possible to make one each of 114 and perform l1llrp with a shift of 8 pits/10 bits by turning on and off the signal 0CTET6.Furthermore, the entire circuit t8 shown in FIG. 4. Set it up in a separate area for the bit method.

Figure 14 shows the addition of 8-bit/10-bit switching bait.
An example of a transmission control section is shown.

- Hereinafter, the operation in the case of 8 pits will be explained.

Out of the 98-bit data that is transferred from the shift register 402 to the reception register 403 at the timing of clock g1 CLKI, the %q*R indication bit AO2 enters the selector 140G together with the empty 4 indication bit AGO of the 10-bit system. When No. 16 0CTET is on, bit person 02 is output as AOO'.Whether in the 1, p, 8-bit method or the 10-bit method, the empty indication bit of that channel is written as bit AOO'. It turns out.

st1 BU8YO given to busy control circuit 407
N, BIJ8YOFt KL j) -k 9 is reset, or there is no change at all. After that, set the selector 1401 to %88 bit time empty*assumed bit AO2.
Enter with '. Selector 1401 receives signal oc'rg'r
@COA outputs bit person 00# as AO2' when it is on and 6s, and it is not the second or later channel of the packet.
As a signal indicating that the channel is not the second or later channel of the ket, there is a signal CHN2t representing the second channel obtained from the prior-application input Io] connection 701 in FIG. When the signal OC'rET is off, that is, in the 10-bit system and in the 8-bit system, bit AO2"t-AO2'
Output as is. At 8-bit Manbu time, after the 2nd channel of t packet, bit AO21t - that tt person 02
’ as 1&! The reason for this is to secure t-8 bits of data from the second channel onwards.

In the end, I added two selectors 1400 and 1401 to 8
By using this in the bit mode, the O processing such as busy control #% transmission/reception data in the @transmission control section can be the same regardless of the difference in 8-bit/10-bit format.

The vacancy information bit AO2' is passed through the check selector 414 and the 98-bit one word is transferred to the dl shift register 41.
3, the clock signals gCI and KIN are included in the tie connection. For the 8-bit system, the selector 14o outputs a serial output from the 04th bit in the middle of the 10-bit shift register 413 prepared for the 10-bit system.
2 is the first signal 0 When CTET is on, the 8th bit output of the transmission shift register 413 is selected and the selector 1402
The result is % i in Figure 7! 1 transmitter 418.

No. 1d (JCTE'f' is off at 0%) The appearance of the 10th bit is determined and similarly sent to the transmission di141g.

Figure 1S shows a part of the final control section with %8 bit/10 bit cut II & total control, and shows the part that should be added to the general diagram.

First, select #1 to send data from the terminal device.
500ri River No.
It functions to output data as valid data display pin (8DO3' in 8-bit format). With this selector 1500, the data presence indication signal is determined regardless of the terminal *i*as bit/10 bit? :1 is output as No. 8REQ - data valid indicator No. 11 is output at the bit position corresponding to the system being used at that time.

Next, when receiving III terminal f& equipment data, the reception register 520 selects the 8-bit signal of the good signal D or END, the data valid indication bit BDO3.
is output from the selector 1501 as RDOI'. As a result, the end device receives 8 bits/10 bits.
Regardless of the bit system, if RDOI' is detected, the validity of the data can be known.

In the end, the terminal fAm using 1 selector 1500.1501 can input and output data valid indicator No. 15 at the same bit position even in the case of a 6-bit/10-bit thread.

As described above, according to the present invention, an internal bus is provided,
Through this, information is exchanged between terminal devices of the same node device. Therefore, information exchange between these terminal devices can be transmitted using only one channel of the transmission path.

Diagram SO Simple:・Explanation Figure 1 is a schematic diagram for explaining the overall system configuration of the method of the present invention, Figure 2, Figure 2, Figure 2B, Figure 2C, Figure 2D, Figure 28, Figure 2F. , Fig. 2G, and Fig. 2H Fig. 1425 are schematic diagrams for explaining the frame structure in the method of the present invention, and Fig. 2I is a palindrome A@rejection o*fII of the final do method.
Figures 3A and 3B are explanatory diagrams for explaining the method of the present invention. /
Figure 5B is a configuration diagram showing an embodiment of the channel control # section in the system of the present invention, and Figure 6 is a diagram showing the salt treatment equipment section in Book-4. FIG. 7 shows transfer control 1so in the method of the present invention.
-41Jglffi, g8Ad, 48B showing actual ms
d, 8CJ, iggB is a configuration diagram showing an embodiment of the terminal system # section in the method of the present invention, and FIG. 9 is a link control section 〇-actual ls? in the method of the present invention. Figure 10 shows an implementation of the packet control unit in the method of the present invention.
Composition showing -%
2WJri Figures 13 to 15 are diagrams showing an example of the claim generation control section in the present invention system, and Figures 13 to 15 are diagrams showing a pigeon house with an In-bi, To-way (8-bit, and To-method switching function) in this @Ming method. Figure 13 is an explanatory diagram showing an example of channel pit allocation in the fIO bit method and the 8-bit method. FIG. 15 is a block diagram showing one embodiment of the terminal control section.0 100-7 frame synchronization section, 2QQ... channel control
N, 30 O”4311!fl, 400...Transfer side production unit 500/One terminal side #8fi, 600...Link control unit 700...Packet control i11 unit, 800...
Packet interface section, 900--frame generation control section.

1000...Terminal device.

Figure 1 San 5 No. 3 11 ward

Claims (1)

[Claims] A plurality of node devices, each connected to a plurality of terminal devices, are connected through a common loop-shaped transmission path, and information on a large number of channels is repeatedly transmitted to the transmission path at a fixed period. ~ Channel information is transmitted between the terminal devices. In a data communication method for transmitting and receiving, each node device includes a transfer control unit that takes in information from the transmission path and transfers information to the transmission path;
The common path includes a terminal control unit provided for the terminal device, and a common path that couples the transfer control unit and the terminal control unit, and the common path includes a first path for transmitting the channel number currently being received, and a common path for connecting the transfer control unit and the terminal control unit. The terminal control unit has a reception path for data received from the transmission path, a transmission path for data sent to the transmission path, and an internal path, and the terminal control unit includes a register that stores a number of a channel to be transmitted; a detection means for detecting a match between the contents of the register and a channel number of a first path in the common path, a mode register indicating a connection with each path in the common path, and a match detected by the detection means; Depending on the output of the above mode register, the transmission data is sent to the above common node (transmission within the space) (is (・(ma internal)), and the received data is sent to the common node (sent within the space). 1. A data communication system characterized by having a receiving path or internal)