JPH0458525A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH0458525A
JPH0458525A JP17096290A JP17096290A JPH0458525A JP H0458525 A JPH0458525 A JP H0458525A JP 17096290 A JP17096290 A JP 17096290A JP 17096290 A JP17096290 A JP 17096290A JP H0458525 A JPH0458525 A JP H0458525A
Authority
JP
Japan
Prior art keywords
silicon
growth
polycrystalline silicon
film
contact hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17096290A
Other languages
Japanese (ja)
Other versions
JP3018408B2 (en
Inventor
Toru Aoyama
亨 青山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2170962A priority Critical patent/JP3018408B2/en
Publication of JPH0458525A publication Critical patent/JPH0458525A/en
Application granted granted Critical
Publication of JP3018408B2 publication Critical patent/JP3018408B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To manufacture this device without leaving a silicon lump on an insulating film by a method wherein a growth process and an etching process are provided and a polycrystalline silicon thin film is grown selectively only inside a contact hole which is opened in the insulating film with which a substrate to be grown is covered. CONSTITUTION:A single-crystal silicon substrate 9 is covered with a silicon oxide film 10. While a wafer having a contact hole 11 exposing the single-crystal silicon substrate 9 is used, a polycrystalline silicon film 12 is deposited selectively on the single-crystal silicon substrate 9 inside the contact hole 11. At this time, an etching operation is executed in order to remove silicon lumps 13 on the silicon oxide film 10. A growth process and an etching process which are described above are repeated two times. Thereby, it is possible to realize a perfect selective polycrystalline silicon growth operation by which the polycrystalline silicon film 12 is grown only inside the contact hole 11.

Description

【発明の詳細な説明】 〔産業上の利用分野) 本発明は半導体装置の製造方法に関するものであり、特
にコンタクト孔の穴埋め等、シリコン基板上の開口部に
選択的に多結晶シリコンを埋設する方法に関するもので
ある。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular, a method for selectively burying polycrystalline silicon in an opening on a silicon substrate, such as filling a contact hole. It is about the method.

〔従来の技術〕[Conventional technology]

選択多結晶シリコン成長は、第4図に示すように被成長
基板上を被った絶縁膜18に開いたコンタクト孔11内
のシリコン19上にたけ多結晶シリコン膜12を堆積さ
せる成長法で、バイポーラトランジスタのエミッタなど
の配線の引出しやコンタクト孔の穴埋めによる平坦化の
技術として重要である。
Selective polycrystalline silicon growth is a growth method in which a polycrystalline silicon film 12 is deposited on silicon 19 in a contact hole 11 formed in an insulating film 18 covering a substrate to be grown, as shown in FIG. It is important as a flattening technique for drawing out wiring such as transistor emitters and filling contact holes.

選択多結晶シリコン成長は、多結晶シリコン12をジク
ロロシラン(S iH2Cl 2 >等のシラン系カス
を熱分解するか、あるいは水素(H2)で還元して堆積
させると同時に、絶縁118上のシリコンのみをエツチ
ングするように塩化水素(HCI )も適i流すことに
よって実現できる。
Selective polycrystalline silicon growth is performed by depositing polycrystalline silicon 12 by thermally decomposing silane-based scum such as dichlorosilane (S iH2Cl 2 ) or reducing it with hydrogen (H2), while at the same time depositing only silicon on the insulator 118. This can be achieved by flowing hydrogen chloride (HCI) in an appropriate manner to etch the etching process.

これは、多結晶シリコンのエツチング速度が下地が絶縁
giaとシリコン19の場合とで異なることを利用した
もので、塩化水素の流量を適当に選ぶことによってコン
タクト孔11内のシリコン19上の多結晶シリコン12
には成長条件になるが、絶縁膜18上に堆積するシリコ
ンにはエツチング条件にすることができる。しかし、コ
ンタクト孔11内にのみ多結晶シリコン12か成長する
ような完全な選択性をもつ条件範囲か狭いため、絶縁[
18上に全くシリコンを残さないというのは現状では難
しい。
This takes advantage of the fact that the etching speed of polycrystalline silicon is different depending on whether the base is insulating GIA or silicon 19. By appropriately selecting the flow rate of hydrogen chloride, polycrystalline silicon on silicon 19 in contact hole 11 can be etched. silicon 12
However, the etching conditions can be applied to the silicon deposited on the insulating film 18. However, the range of conditions for complete selectivity such that polycrystalline silicon 12 grows only in the contact hole 11 is narrow, so the insulation [
At present, it is difficult to leave no silicon on 18.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の選択多結晶シリコン成長では、完全には
選択成長することかできず、絶縁膜上にシリコン塊が点
在するという問題点を有する。特に厚い多結晶シリコン
の膜を成長させるときにこの間離が顕著で、長時間成長
させるため絶縁膜上にシリコン塊が多数存在し選択性を
保つことか誼しくなる。
The conventional selective polycrystalline silicon growth described above has the problem that it is not possible to achieve complete selective growth, and silicon lumps are scattered on the insulating film. This spacing is particularly noticeable when growing a thick polycrystalline silicon film, and as the film is grown for a long time, many silicon lumps exist on the insulating film, making it difficult to maintain selectivity.

本発明の目的はシリコン塊を絶縁膜上に残すことのない
完全な選択多結晶シリコン成長を実現させる半導体装置
の製造方法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that realizes completely selective polycrystalline silicon growth without leaving any silicon lumps on an insulating film.

〔課題を解決するための手段〕[Means to solve the problem]

前記目的を達成するため、本発明に係る半導体装置の製
造方法においては、成長工程と、エツチング工程とを有
し、被成長基板を被う絶縁膜に開口したコンタクト孔内
のみに多結晶シリコン薄膜を選択成長させる半導体装置
の製造方法であって、成長工程は、成長ガスとエツチン
グガスとを同時に流して多結晶シリコンを前記コンタク
ト孔内に選択成長させるものであり、 エツチング工程は、エツチングガスを流して絶縁膜上の
シリコンのみを取除くものであり、また前記成長工程と
、エツチング工程とは、交互に組合せて行なわれるもの
であり、この組合せにより前記コンタクト孔内のみに膜
成長させるものである。
In order to achieve the above object, the method for manufacturing a semiconductor device according to the present invention includes a growth step and an etching step, and forms a polycrystalline silicon thin film only in a contact hole opened in an insulating film covering a growth substrate. A method for manufacturing a semiconductor device in which polycrystalline silicon is selectively grown in the contact hole by simultaneously flowing a growth gas and an etching gas in the growth step, and in the etching step, a growth gas and an etching gas are flowed simultaneously. This method removes only the silicon on the insulating film by flowing it, and the growth step and the etching step are performed in alternating combinations, and this combination allows the film to grow only in the contact hole. be.

〔作用〕[Effect]

本発明の選択多結晶シリコン成長は、従来の成長方法に
よる成長処理に加えて、塩化水素(HCl )のみを流
すエツチング処理を行なう工程を有し、それらを交互に
組合せて膜成長させるものである2 〔実施例〕 次に本発明について図面を参照して説明する。
The selective polycrystalline silicon growth of the present invention includes a process of performing an etching process by flowing only hydrogen chloride (HCl) in addition to a growth process using a conventional growth method, and a film is grown by alternately combining these processes. 2 [Example] Next, the present invention will be described with reference to the drawings.

(実施例1) 第1図はポリシリコン等の種々の成膜に使われている気
相成長装置を示したものである。架台3上には、1回の
成長で数十枚の被成長基板4を処理するための縦に長い
内外管1.2の二重構造とした円筒ドーム形の石英製炉
心管を配し、その回りは抵抗加熱炉6で囲われている。
(Example 1) FIG. 1 shows a vapor phase growth apparatus used for forming various films such as polysilicon. A cylindrical dome-shaped quartz furnace core tube with a double structure of vertically long inner and outer tubes 1.2 is arranged on the pedestal 3 to process several dozen growth substrates 4 in one growth. It is surrounded by a resistance heating furnace 6.

内管2の中心には基板ホルダー5が、被成長基板4をあ
る間隔で水平に積み重ねるように保持している。基板ホ
ルダー5の下端中心軸は、架台3の下まで伸びており、
下端中心軸のまわりに回転できるようになっている一t
た架台3の下からは、縦長の細いガス導入管7が内管2
の壁に沿うように伸びており、そのガス導入管7よりジ
クロロシラン(S iH2CI2)等のシラン系ガス、
水素(H2)が各被成長基板4に向かって放出され、そ
の上に選択的に多結晶シリコン膜を成長させる。成長に
関与しなかったカスは、カス排出孔8を通って排気され
る。
At the center of the inner tube 2, a substrate holder 5 holds the growth substrates 4 so as to be stacked horizontally at certain intervals. The lower end center axis of the board holder 5 extends to the bottom of the pedestal 3,
It is designed to be able to rotate around the central axis at the bottom end.
From below the frame 3, a vertically long thin gas introduction pipe 7 connects to the inner pipe 2.
It extends along the wall, and from the gas introduction pipe 7, silane-based gas such as dichlorosilane (S iH2CI2),
Hydrogen (H2) is released toward each growth substrate 4 to selectively grow a polycrystalline silicon film thereon. The dregs not involved in the growth are exhausted through the dregs discharge hole 8.

第2図(a)に示すような被成長基板4として、単結晶
シリコン基板9を500nn厚のシリコン酸化M、10
で被い、さらにシリコン酸化[10に1μm×1μmの
大きさの単結晶シリコン9を露出させたコンタクト孔1
1を設けたウェーハを用いた。
As a growth substrate 4 as shown in FIG.
Contact hole 1 in which single crystal silicon 9 with a size of 1 μm×1 μm is exposed in silicon oxide [10]
A wafer provided with No. 1 was used.

成長時の圧力は、30TOrrで、温度800℃でジク
ロロシランを3003CC11、塩化水素を150se
ci 15分間流し、コンタクト孔11内の単結晶シリ
コン9上に選択的に多結晶シリコン膜12を10onI
N堆積させた。しかし、第2図(b)に示すように、シ
リコン酸化膜10上にもシリコン塊13が残り点在する
なめ、それらを取り除くために、次に一部ジククロシラ
ンを止め、塩化水素のみを300sccn mして15
分間エツチングを行なった。それによりコンタクト孔1
1内の多結晶シリコン膜12をエツチングすることなく
、シリコン酸化膜1Q上のシリコン塊13のみをエツチ
ングして取り除いた。
The pressure during growth was 30 TOrr, the temperature was 800°C, 3003 CC11 of dichlorosilane, and 150 se of hydrogen chloride.
ci for 15 minutes to selectively form a polycrystalline silicon film 12 on the single crystal silicon 9 in the contact hole 11 at 10 onI.
N was deposited. However, as shown in FIG. 2(b), some silicon lumps 13 remain on the silicon oxide film 10, and in order to remove them, dichlorosilane is partially stopped and only hydrogen chloride is added at 300 sccn m. then 15
Etching was performed for a minute. Contact hole 1
Only the silicon lump 13 on the silicon oxide film 1Q was etched and removed without etching the polycrystalline silicon film 12 in the silicon oxide film 1Q.

以上のように、成長工程とエツチング工程との1回の組
合せで膜厚100nnの完全な選択多結晶シリコン成長
を実現した(第2図(C))。
As described above, complete selective polycrystalline silicon growth with a film thickness of 100 nm was realized by a single combination of the growth process and the etching process (FIG. 2(C)).

絶縁膜であるシリコン酸化膜10上に点在するシリコン
塊13は、大きく成長してしまってからではエツチング
して取り除くことは難しいが、このように成長の初期の
段階ではエツチングガスを流すことによって容易に取り
除けた。さらに、これらの成長工程とエツチング工程と
の組合せを2回繰り返すことで、200nnの多結晶シ
リコン@12か、コンタクト孔11内にのみ成長する完
全な選択多結晶シリコン成長か実現できた(第2図(d
))。
It is difficult to remove the silicon lumps 13 scattered on the silicon oxide film 10, which is an insulating film, by etching them once they have grown to a large size, but they can be removed by flowing an etching gas in the early stage of growth. It was easily removed. Furthermore, by repeating the combination of these growth steps and etching steps twice, we were able to achieve either 200nm polycrystalline silicon@12 or completely selective polycrystalline silicon growth that grows only within the contact hole 11 (second step). Figure (d
)).

(実施例2) 第3図(a)〜((1)は多層構造を示す被成長基板4
に用いた例を示すものである。第3図(a)において、
被成長基板4は、単結晶シリコン基板9上に、下からシ
リコン酸化M14−100nn 、多結晶シリコン!!
g!15−100nn 、シリコン酸化M1G−40O
n11、窒化膜17−100nnの4層を堆積させたの
ち、窒化膜17、シリコン酸化膜16を貫いてコンタク
ト孔11を多結晶シリコン[5が露出するように開口し
たものである。この構造は、多結晶シリコンを動作領域
とするトランジスタであるT P T (Thin F
ilmTransistor)の配線コンタクトのもの
である。また、絶縁膜として、実施例1がシリコン酸化
膜なのに対して実施例2では窒化膜を用いた。
(Example 2) Figures 3(a) to (1) show a growth substrate 4 having a multilayer structure.
This is an example used in the following. In Figure 3(a),
The growth substrate 4 is a single crystal silicon substrate 9, and from the bottom, silicon oxide M14-100nn, polycrystalline silicon! !
g! 15-100nn, silicon oxide M1G-40O
After depositing four layers of nitride film 17 to 100 nn, contact hole 11 is opened to expose polycrystalline silicon [5] through nitride film 17 and silicon oxide film 16. This structure is based on TPT (Thin F), which is a transistor whose operating region is polycrystalline silicon.
ilmTransistor) wiring contact. Further, as the insulating film, a silicon oxide film was used in Example 1, whereas a nitride film was used in Example 2.

この被成長基板4に、多結晶シリコン1912を窒化M
17には成長させることなしに多結晶シリコン膜15上
にコンタクト孔11内を300nl埋めるような選択成
長を試みた。実施例1と同じ装置を用いて、また圧力も
実施例1と同じ30Torrで行なった。
Polycrystalline silicon 1912 is nitrided onto this growth substrate 4.
In 17, an attempt was made to selectively grow the inside of the contact hole 11 by 300 nl on the polycrystalline silicon film 15 without growing it. The same equipment as in Example 1 was used, and the pressure was also the same as in Example 1, 30 Torr.

ます、温度800°Cでジクロロシランを300scc
n、塩化水素を150scci 15分間流し、多結晶
シリコンWj!12を100n階コンタクト孔11内に
堆積させた(第3図(b))。つぎにジクロロシランを
止め、塩化水素のみを600scci 、 10分間流
して窒化膜17上のシリコン塊13をエツチングして、
多結晶シリコン脛12を完全にコンタクト孔11のみを
埋める選択多結晶シリコン成長を実現した(第3図(C
))。
First, add 300scc of dichlorosilane at a temperature of 800°C.
n, flowing hydrogen chloride at 150scci for 15 minutes, polycrystalline silicon Wj! 12 was deposited in the 100n-th contact hole 11 (FIG. 3(b)). Next, the dichlorosilane was stopped, and only hydrogen chloride was flowed at 600 scci for 10 minutes to etch the silicon lump 13 on the nitride film 17.
We achieved selective polycrystalline silicon growth that completely fills only the contact hole 11 of the polycrystalline silicon shank 12 (see Figure 3 (C).
)).

実施例2は、実施例1の場合と異なりエツチング段階で
の塩化水素の流量を増やしな分、成長時間か短縮された
。この1サイクル25分で90nINの多結晶シリコン
J12を成長できた。選択性の説明としては絶縁膜がシ
リコン酸化膜の場合に限り、Extended Abs
tracts of the 18th Confer
ence onSolid 5tate Device
s and Materials、 1986. pp
49−52の論文が存在するが、それによるとシリコン
酸化膜上に堆積したシリコンはシリコン酸化膜と反応し
てSiOとなり、気相中に逃げるためにシリコン酸化膜
上にはシリコンが堆積しないとしている。しかし、この
実施例2の場合には絶縁膜に窒化膜を用いており、絶縁
膜がシリコン酸化膜でなくても選択多結晶シリコン成長
が実現できることがわかった。
In Example 2, unlike in Example 1, the growth time was shortened by increasing the flow rate of hydrogen chloride in the etching step. Polycrystalline silicon J12 of 90 nIN could be grown in this one cycle of 25 minutes. To explain the selectivity, only when the insulating film is a silicon oxide film, Extended Abs
tracts of the 18th Conference
ence onSolid 5tate Device
s and Materials, 1986. pp
49-52, which states that silicon deposited on a silicon oxide film reacts with the silicon oxide film to form SiO and escapes into the gas phase, so no silicon is deposited on the silicon oxide film. There is. However, in the case of Example 2, a nitride film is used as the insulating film, and it was found that selective polycrystalline silicon growth can be achieved even if the insulating film is not a silicon oxide film.

コンタクト孔11内に300nlの多結晶シリコン膜1
2を成長させるのには、のサイクルを3回繰り返すこと
で実現できたく第3図(d))。
300nl polycrystalline silicon film 1 in contact hole 11
2 can be achieved by repeating the cycle three times (Figure 3(d)).

以上の実施例において、選択多結晶シリコン成長ガスと
してジクロロシランを用いた場合について述べたが、モ
ノシラン(S I H4) 、ジシラン(Si2H6)
ガスでもよい。又成長時の温度とエツチング時の温度は
必ずしも同一である必要はなく、それ等の温度は400
’C〜900°Cであればよい 〔発明の効果〕 以上説明したように本発明を用いることによって、従来
問題になっていたシリコン塊を絶縁膜上に残すことのな
い完全な選択多結晶シリコン成長を実現できた。また、
本発明により長時間の選択多結晶シリコン成長が可能に
なった。
In the above examples, the case where dichlorosilane was used as the selective polycrystalline silicon growth gas was described, but monosilane (S I H4), disilane (Si2H6)
It could be gas. Also, the temperature during growth and the temperature during etching do not necessarily have to be the same;
[Effects of the Invention] As explained above, by using the present invention, it is possible to completely select polycrystalline silicon without leaving silicon lumps on the insulating film, which has been a problem in the past. We were able to achieve growth. Also,
The present invention has made it possible to selectively grow polycrystalline silicon over a long period of time.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明で用いた選択多結晶シリコン成長の気相
成長装置を示す縦断面図、第2図(a)は本発明の実施
例1で使用した被成長基板の一部分を示す断面図、第2
図(b)は本発明の実施例1での第1回目の成長工程を
行った状態を示す断面図、第2図(C)は実施例1の成
長工程とエツチング工程との1サイクルを終えた状態を
示す断面図、第2図((1)は実施例1の選択多結晶シ
リコン成長が完了した状態を示す断面図、第3図(a)
は本発明の実施例2で使用した被成長基板の一部分を示
す断面図、第3図(b)は本発明の実施例2での第1回
目の成長工程を行った状態を示す断面図、第3図(C)
は実施例2の成長工程とエツチング工程との1サイクル
を終えた状態を示す断面図、第3図(d)は実施例2の
選択多結晶シリコン成長が完了した状態を示す断面図、
第4図は一般の選択多結晶シリコン成長を示す断面図で
ある。 1・・・外管       2・・・内管3・・・架台
       4・・・被成長基板5・・・基板ホルダ
ー   6・・・抵抗加熱炉7・・・ガス導入管   
 8・・・ガス排出孔9・・・単結晶シリコン基板 10・・・シリコン酸化膜 12・・・多結晶シリコン膜 14・・・シリコン酸化膜 16・・・シリコン酸化膜 18・・・絶縁膜 11・・・コンタクト孔 13・・・シリコン塊 15・・・多結晶シリコン膜 17・・・窒化膜 19・・・シリコン 特許出願人   日本電気株式会社 代  理  人    弁理士 菅 野   中Oり 第 図 4値底長枳緻 第 図
FIG. 1 is a vertical cross-sectional view showing a vapor phase growth apparatus for selective polycrystalline silicon growth used in the present invention, and FIG. 2 (a) is a cross-sectional view showing a part of the growth substrate used in Example 1 of the present invention. , second
Figure (b) is a cross-sectional view showing the state after the first growth process in Example 1 of the present invention, and Figure 2 (C) is a cross-sectional view showing the state after one cycle of the growth process and etching process in Example 1. ((1) is a cross-sectional view showing the state in which the selective polycrystalline silicon growth of Example 1 is completed; FIG. 3(a)
3(b) is a sectional view showing a part of the growth substrate used in Example 2 of the present invention, and FIG. 3(b) is a sectional view showing the state after the first growth step in Example 2 of the present invention. Figure 3 (C)
3(d) is a cross-sectional view showing the state after completing one cycle of the growth process and the etching process in Example 2, and FIG.
FIG. 4 is a cross-sectional view showing general selective polycrystalline silicon growth. 1... Outer tube 2... Inner tube 3... Frame 4... Growth substrate 5... Substrate holder 6... Resistance heating furnace 7... Gas introduction tube
8... Gas exhaust hole 9... Single crystal silicon substrate 10... Silicon oxide film 12... Polycrystalline silicon film 14... Silicon oxide film 16... Silicon oxide film 18... Insulating film 11...Contact hole 13...Silicon lump 15...Polycrystalline silicon film 17...Nitride film 19...Silicon patent applicant NEC Corporation Representative Patent attorney Kanno Nakao Diagram 4-value bottom long chart

Claims (2)

【特許請求の範囲】[Claims] (1)成長工程と、エッチング工程とを有し、被成長基
板を被う絶縁膜に開口したコンタクト孔内のみに多結晶
シリコン薄膜を選択成長させる半導体装置の製造方法で
あって、 成長工程は、成長ガスとエッチングガスとを同時に流し
て多結晶シリコンを前記コンタクト孔内に選択成長させ
るものであり、 エッチング工程は、エッチングガスを流して絶縁膜上の
シリコンのみを取除くものであることを特徴とする半導
体装置の製造方法。
(1) A method for manufacturing a semiconductor device, which comprises a growth step and an etching step, and selectively grows a polycrystalline silicon thin film only in a contact hole opened in an insulating film covering a substrate to be grown, the growth step comprising: , polycrystalline silicon is selectively grown in the contact hole by simultaneously flowing a growth gas and an etching gas, and the etching process is a process in which only the silicon on the insulating film is removed by flowing the etching gas. A method for manufacturing a featured semiconductor device.
(2)前記成長工程と、エッチング工程とは、交互に組
合せて行なわれるものであり、この組合せにより前記コ
ンタクト孔内のみに膜成長させることを特徴とする請求
項第(1)項に記載の半導体装置の製造方法。
(2) The growth step and the etching step are performed in alternating combinations, and this combination allows the film to grow only within the contact hole. A method for manufacturing a semiconductor device.
JP2170962A 1990-06-28 1990-06-28 Method for manufacturing semiconductor device Expired - Lifetime JP3018408B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2170962A JP3018408B2 (en) 1990-06-28 1990-06-28 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2170962A JP3018408B2 (en) 1990-06-28 1990-06-28 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0458525A true JPH0458525A (en) 1992-02-25
JP3018408B2 JP3018408B2 (en) 2000-03-13

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Family Applications (1)

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Country Status (1)

Country Link
JP (1) JP3018408B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5494844A (en) * 1993-06-14 1996-02-27 Nec Corporation Process of fabricating Bi-CMOS integrated circuit device
JPH10321556A (en) * 1997-05-17 1998-12-04 Tokyo Electron Ltd Deposition of film
US9318328B2 (en) 2012-05-29 2016-04-19 Tokyo Electron Limited Method and apparatus for forming silicon film

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5494844A (en) * 1993-06-14 1996-02-27 Nec Corporation Process of fabricating Bi-CMOS integrated circuit device
JPH10321556A (en) * 1997-05-17 1998-12-04 Tokyo Electron Ltd Deposition of film
US9318328B2 (en) 2012-05-29 2016-04-19 Tokyo Electron Limited Method and apparatus for forming silicon film

Also Published As

Publication number Publication date
JP3018408B2 (en) 2000-03-13

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