JPS61174739A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61174739A JPS61174739A JP1591585A JP1591585A JPS61174739A JP S61174739 A JPS61174739 A JP S61174739A JP 1591585 A JP1591585 A JP 1591585A JP 1591585 A JP1591585 A JP 1591585A JP S61174739 A JPS61174739 A JP S61174739A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline
- recess
- substrate
- filling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に係り、特に、窪みを
有し該窪みを含む表面が非晶質の絶縁体でなる基板の該
窪みに多結晶物質を充填する方法に関す。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device, the present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device. The present invention relates to a method for filling polycrystalline materials into materials.
半導体装置の高集積化に伴い基板に形成される素子分離
領域やコンデンサは、溝や穴状をなし表面に絶縁膜を有
する窪みを利用して基板上の占有面積を小さくするよう
になってきた。As semiconductor devices become more highly integrated, element isolation regions and capacitors formed on substrates are now formed in the form of grooves or holes, with depressions having an insulating film on their surfaces to reduce the area they occupy on the substrate. .
この際、基板の上に他の膜を積層する都合やコンデンサ
の場合窪みの内面に電極が形成される必要性から、窪み
は通常多結晶のシリコン(Si)で充填される。At this time, the recess is usually filled with polycrystalline silicon (Si) because of the need to stack other films on the substrate or because it is necessary to form an electrode on the inner surface of the recess in the case of a capacitor.
そして、半導体装置の品質確保のため、この充填は安定
した作業で行い得ることが望ましい。In order to ensure the quality of the semiconductor device, it is desirable that this filling can be performed in a stable manner.
窪みを有し該窪みを含む表面が非晶質の絶縁体でなる基
板の該窪みに多結晶Siを充填する際の従来の方法の一
例の手順は、第2図(a)〜(C1の工程順側断面図に
示す如くである。The procedure of an example of a conventional method for filling polycrystalline Si into the hollow of a substrate having a hollow and the surface including the hollow is made of an amorphous insulator is shown in FIGS. 2(a) to (C1). As shown in the step-by-step side sectional views.
即ち、先ず〔図(a)参照〕、基板1 (1aは窪み、
1bは二酸化Si (SiO2)や窒化Si (Si3
Na )などの非晶質絶縁体からなる表面の絶縁層)
上に、作用ガスを例えばモノシラン(SiHa)にした
化学気相成長(CV D)により、窪み1aが充填され
るまで多結晶Si膜2を成長させる。多結晶Si膜2は
基板1の上面にも成長している。That is, first [see figure (a)], the substrate 1 (1a is a depression,
1b is Si dioxide (SiO2) or Si nitride (Si3
A surface insulating layer made of an amorphous insulator such as Na)
A polycrystalline Si film 2 is grown thereon by chemical vapor deposition (CVD) using monosilane (SiHa) as a working gas until the recess 1a is filled. Polycrystalline Si film 2 is also grown on the upper surface of substrate 1.
次いで〔図(′b)参照〕、多結晶Si膜膜上上通常の
方法でレジストを塗布してレジスト膜3を形成する。多
結晶Si膜2の表面に凹凸があるにもかかわらずレジス
ト膜3の表面は略平坦になる。Next [see Figure ('b)], a resist film 3 is formed by applying a resist on the polycrystalline Si film by a conventional method. Although the surface of the polycrystalline Si film 2 has irregularities, the surface of the resist film 3 becomes substantially flat.
次いで〔図(C1参照〕、レジスト膜3と多結晶Si膜
2とに対してエツチングレートの差の少ないエツチング
方法例えばスパッタエツチングにより基板1上のレジス
ト膜3と多結晶Si膜2を除去する。Next, as shown in the figure (see C1), the resist film 3 and the polycrystalline Si film 2 on the substrate 1 are removed by an etching method with a small difference in etching rate between the resist film 3 and the polycrystalline Si film 2, such as sputter etching.
ざすれば、窪み1aの中に多結晶Si体4が残り所望の
充填が完了する。When the filling is completed, the polycrystalline Si body 4 remains in the depression 1a and the desired filling is completed.
窪み1aに多結晶Siを充填する際の従来の方法の他の
例の手順は、第3図fa) (blの工程順側断面図に
示す如くである。The procedure of another example of the conventional method for filling the recess 1a with polycrystalline Si is as shown in the step-by-step side sectional view of FIG. 3 fa) (bl).
即ち、先ず〔図(al参照〕、第2図(alの場合と同
様にして多結晶Si膜2を成長させる。多結晶Si膜2
は基板1の上面にも成長している。That is, first, a polycrystalline Si film 2 is grown in the same manner as in FIG.
is also grown on the upper surface of the substrate 1.
次いで〔図fb)参照〕、基板1上の多結晶Si膜2を
機械的研摩により除去する。さすれば、窪み1aの中に
多結晶Si体4が残り所望の充填が完了する。Next (see Figure fb), the polycrystalline Si film 2 on the substrate 1 is removed by mechanical polishing. Then, the polycrystalline Si body 4 remains in the depression 1a, completing the desired filling.
しかしながら、上記第一の例においては、第2図(C1
で述べたエツチングに際して絶縁層2の表出時点の判定
が困難であるため、エツチングの再現性が良くない問題
がある。However, in the first example above, in Figure 2 (C1
During the etching mentioned above, it is difficult to determine the point at which the insulating layer 2 is exposed, so there is a problem that the reproducibility of the etching is poor.
また上記第二の例においては、研摩面を基板1の上面に
合致させるのが困難であるため、絶縁層1bの厚さが基
板1上面の場所により異なってしまう問題がある。Furthermore, in the second example, since it is difficult to match the polished surface with the top surface of the substrate 1, there is a problem that the thickness of the insulating layer 1b varies depending on the location on the top surface of the substrate 1.
そしてこれらの問題は半導体装置の品質低下に繋がるも
のである。These problems lead to a decline in the quality of semiconductor devices.
上記問題点は、窪みを有し咳窪みを含む表面が非晶質の
絶縁体でなる基板において、該表面に多結晶膜を被着し
た後該窪みの少なくとも側面領域を残して該多結晶膜を
除去し、しかる後膣多結晶膜を種にした多結晶物質の選
択的気相成長を行って、該窪みに多結晶物質を充填する
本発明による半導体装置の製造方法によって解決される
。The above-mentioned problem is that in a substrate having a depression and a surface including a cough depression made of an amorphous insulator, after a polycrystalline film is deposited on the surface, the polycrystalline film is removed by leaving at least the side area of the depression. The problem is solved by the method of manufacturing a semiconductor device according to the present invention, in which the recess is filled with the polycrystalline material by selective vapor phase growth of the polycrystalline material using the polycrystalline film as a seed.
上記多結晶膜の除去により基板の上面は絶縁体が表出し
ており、上記多結晶物質の成長は、窪みに残された多結
晶膜を種にして窪みのみを選択的に充填するので、この
成長により所望の充填が完了する。The removal of the polycrystalline film exposes the insulator on the top surface of the substrate, and the growth of the polycrystalline material selectively fills only the depressions using the polycrystalline film left in the depressions as a seed. Growth completes the desired filling.
従って、前述したエツチングや研摩が不要になり従来の
問題が解消する。Therefore, the above-mentioned etching and polishing are not necessary, and the conventional problems are solved.
かくして、窪みを有し該窪みを含む表面が非晶質の絶縁
体でなる基板の該窪みに多結晶物質を充填するのに安定
した作業で行うことが可能になり、半導体装置の品質を
向上させることが可能になる。In this way, it becomes possible to perform stable filling of the polycrystalline material into the hollows of a substrate whose surface including the hollows is made of an amorphous insulator, thereby improving the quality of semiconductor devices. It becomes possible to do so.
以下、窪みを有し該窪みを含む表面が非晶質の絶縁体で
なる基板の該窪みに多結晶Siを充填する際に、本発明
の方法によって多結晶Siを充填する素子分離領域形成
の一実施例の手順について、第1図(al〜(dlの工
程順側断面図により説明する。全図を通じ同一符号は同
一対象物を示す。Hereinafter, when filling polycrystalline Si into the hollow of a substrate having a hollow and the surface including the hollow is made of an amorphous insulator, the method of the present invention will be used to form an element isolation region filled with polycrystalline Si. The procedure of one embodiment will be explained with reference to step-by-step side cross-sectional views of FIGS.
即ち、先ず〔図(a)参照〕、素子分離領域形成予定領
域が窪み1aになっている基板1の非晶質絶縁層1bが
Si3N4の場合は直接その上に(図はこのの場合を示
す)、また絶縁層1bがSiO2の場合は通常の方法で
厚さ約1000人の図示されないSi3 N4膜を被着
した上に、作用ガスを例えばSiH4にしたCVDによ
り、厚さが100〜2000人程度の多結晶成長膜5を
成長させる。この場合、SiH4がSiとH2になって
基板1上に多結晶Siを生成させるため、多結晶Si膜
5は窪み1aの内面も含む基板1の表面に略一様の厚さ
に成長する。That is, first of all, [see Figure (a)], if the amorphous insulating layer 1b of the substrate 1 in which the region where the element isolation region is to be formed is the depression 1a is made of Si3N4, a layer is placed directly on it (the figure shows this case). ), and when the insulating layer 1b is made of SiO2, an Si3N4 film (not shown) is deposited to a thickness of about 1000 mm using a normal method, and then a Si3 N4 film (not shown) is deposited to a thickness of about 100 to 2000 mm by CVD using, for example, SiH4 as a working gas. A polycrystalline growth film 5 of about 100% is grown. In this case, since SiH4 turns into Si and H2 to produce polycrystalline Si on the substrate 1, the polycrystalline Si film 5 grows to a substantially uniform thickness on the surface of the substrate 1 including the inner surface of the recess 1a.
次いで〔図(′b)参照〕、作用ガスを例えば四塩化炭
素(CC14”)にした方向性リアクティブスパッタエ
ソチングにより多結晶Si膜5をエツチングして、絶縁
層1b (Si3 N4膜を被着した場合には該Si3
N4膜)を表出させる。この際、多結晶Si膜5の厚さ
が薄いので絶縁層1bの表出時点を狙ったエツチングス
トップが可能になりエツチングの再現性が良い。そして
この方向性エツチングにより多結晶Si膜5は、基板1
の上面および窪み1aの底面領域が除去されて窪み1a
の側面領域が残る。Next, [see Figure ('b)], the polycrystalline Si film 5 is etched by directional reactive sputter etching using carbon tetrachloride (CC14'') as the working gas to form the insulating layer 1b (covered with the Si3N4 film). If the Si3
N4 film) is exposed. At this time, since the polycrystalline Si film 5 is thin, etching can be stopped at the point where the insulating layer 1b is exposed, and the reproducibility of etching is good. By this directional etching, the polycrystalline Si film 5 is etched onto the substrate 1.
The top surface and the bottom area of the recess 1a are removed to form the recess 1a.
lateral areas remain.
次いで〔図(C)参照〕、塩素(CI)を含んだSi化
合物ガス例えばトリクロルシラン(SiHC1コ)と水
素(H2)とを作用ガスにしたCVDにより、多結晶S
i膜5を種にした多結晶Siを選択的に成長させる。さ
すれば、成長した多結晶Siは窪み1aを選択的に充填
して多結晶Si体4を形成し所望の充填が完了する。Next [see Figure (C)], polycrystalline S
Polycrystalline Si is selectively grown using the i film 5 as a seed. Then, the grown polycrystalline Si selectively fills the depression 1a to form the polycrystalline Si body 4, completing the desired filling.
この成長は、上記CVDにおいて、5iHC13とトI
2がSiとHCIになって被処理体の上(この場合、絶
縁層1bおよび多結晶Si膜5の上)に多結晶Siを生
成させる作用と、生成したSiがHCIと反応して再蒸
発する作用とが存在し、後者の作用が既存の多結晶Si
上より非晶質の絶縁体上で強いことを利用して、絶縁層
Jb上にSiが成長しないように温度や圧力を選定する
ことによって達成される。This growth is caused by 5iHC13 and tI in the above CVD.
2 becomes Si and HCI to generate polycrystalline Si on the object to be processed (in this case, on the insulating layer 1b and polycrystalline Si film 5), and the generated Si reacts with HCI and reevaporates. The latter effect exists in existing polycrystalline Si.
This is achieved by taking advantage of the fact that Si is stronger on an amorphous insulator than above and selecting the temperature and pressure so that Si does not grow on the insulating layer Jb.
上記CVDの作用ガスには、5iHC13の代わりにジ
クロルシラン(Si H2C12)若しくは四塩化Si
(SiC1a )を使用してもよく、また塩化水素(
HC1)を適宜添加してもよい。The working gas for the above CVD includes dichlorosilane (Si H2C12) or Si tetrachloride instead of 5iHC13.
(SiC1a) may be used, and hydrogen chloride (SiC1a) may also be used.
HC1) may be added as appropriate.
次いで〔図(d)参照〕、通常の熱酸化法により酸化す
れば、Si3N4で覆われていないSrの表面層即ち多
結晶Si体4の表面層のみが酸化し5i02の絶縁層6
が形成されて所望の素子分離領域が完成する。Next [see Figure (d)], when oxidation is performed by a normal thermal oxidation method, only the surface layer of Sr not covered with Si3N4, that is, the surface layer of the polycrystalline Si body 4, is oxidized, and the insulating layer 6 of 5i02 is oxidized.
is formed to complete the desired element isolation region.
上述した多結晶Siの充填方法は、前記Si3 N4膜
を被着しない場合であっても、絶縁層1bの厚さに生ず
るばらつきを従来より低減させて、前述したコンデンサ
を有する半導体装置の製造においても有効であることが
容易に理解出来る。The above-described polycrystalline Si filling method reduces variations in the thickness of the insulating layer 1b more than before even when the Si3N4 film is not deposited, and is effective in manufacturing the semiconductor device having the above-mentioned capacitor. It is easy to understand that this is also effective.
また、上述した多結晶Siの充填と同様な原理を用いれ
ば、絶縁Ff 1 bは他の非晶質絶縁体例えば非晶質
アルミナ(A1zO3)などでもよ(、多結晶Si膜5
および多結晶Si体4も、他の多結晶物質例えばそれぞ
れスパッタで成長させたタングステン(W)膜および六
弗化タングステン(WF6)とH2とを作用ガスにして
選択的に成長させたWなどにすることが可能である。Furthermore, by using the same principle as the polycrystalline Si filling described above, the insulation Ff 1 b may be made of other amorphous insulators, such as amorphous alumina (A1zO3) (polycrystalline Si film 5
The polycrystalline Si body 4 is also made of other polycrystalline materials such as a tungsten (W) film grown by sputtering and W selectively grown using tungsten hexafluoride (WF6) and H2 as working gases. It is possible to do so.
以上説明したように、本発明の方法によれば、窪みを有
し該窪みを含む表面が非晶質の絶縁体でなる基板の該窪
みに多結晶物質を充填するのに安定した作業で行うこと
が可能になり、半導体装置の品質向上を可能にさせる効
果がある。As explained above, according to the method of the present invention, a polycrystalline substance can be filled into the hollow of a substrate having a hollow and the surface including the hollow is made of an amorphous insulator using a stable operation. This has the effect of making it possible to improve the quality of semiconductor devices.
【図面の簡単な説明】
図面において、
第1図(al〜(d男本発明の方法によって多結晶Si
を充填する素子分離領域形成の一実施例の手順を示す工
程順側断面図、
第2図(al〜(C1は多結晶Siを充填する際の従来
の方法の一例の手順を示す工程順側断面図、第3図(a
l (b)は同じく他の例の手順を示す工程順側断面図
である。
また、図中において、
■は基板、 1aは窪み、1bは非晶質の
絶縁層、 2.5は多結晶Si膜、3はレジスト膜、
4は多結晶Si体、6は絶縁層、
をそれぞれ示す。
拳3に[BRIEF DESCRIPTION OF THE DRAWINGS] In the drawings, FIG.
FIG. Cross-sectional view, Figure 3 (a
1(b) is a process order side sectional view showing the procedure of another example. In addition, in the figure, ① is a substrate, 1a is a depression, 1b is an amorphous insulating layer, 2.5 is a polycrystalline Si film, 3 is a resist film,
4 is a polycrystalline Si body, and 6 is an insulating layer. to fist 3
Claims (1)
基板において、該表面に多結晶膜を被着した後該窪みの
少なくとも側面領域を残して該多結晶膜を除去し、しか
る後該多結晶膜を種にした多結晶物質の選択的気相成長
を行って、該窪みに多結晶物質を充填することを特徴と
する半導体装置の製造方法。In a substrate having a recess and a surface including the recess made of an amorphous insulator, after depositing a polycrystalline film on the surface, removing the polycrystalline film leaving at least a side region of the recess, and then 1. A method of manufacturing a semiconductor device, comprising: thereafter performing selective vapor phase growth of a polycrystalline material using the polycrystalline film as a seed to fill the recess with the polycrystalline material.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1591585A JPS61174739A (en) | 1985-01-30 | 1985-01-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1591585A JPS61174739A (en) | 1985-01-30 | 1985-01-30 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61174739A true JPS61174739A (en) | 1986-08-06 |
Family
ID=11902071
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1591585A Pending JPS61174739A (en) | 1985-01-30 | 1985-01-30 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61174739A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5004703A (en) * | 1989-07-21 | 1991-04-02 | Motorola | Multiple trench semiconductor structure method |
US5399516A (en) * | 1992-03-12 | 1995-03-21 | International Business Machines Corporation | Method of making shadow RAM cell having a shallow trench EEPROM |
KR19990060829A (en) * | 1997-12-31 | 1999-07-26 | 김영환 | Device Separator Formation Method of Semiconductor Device |
-
1985
- 1985-01-30 JP JP1591585A patent/JPS61174739A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5004703A (en) * | 1989-07-21 | 1991-04-02 | Motorola | Multiple trench semiconductor structure method |
US5399516A (en) * | 1992-03-12 | 1995-03-21 | International Business Machines Corporation | Method of making shadow RAM cell having a shallow trench EEPROM |
KR19990060829A (en) * | 1997-12-31 | 1999-07-26 | 김영환 | Device Separator Formation Method of Semiconductor Device |
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