JPS63143835A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to shorten and simplify the process to a large extent, by forming a deep groove for a capacitor cell and shallow element isolating groove in a silicon substrate, and forming an oxide film at a thickness corresponding to the depth of the element isolating grooves by using RF bias sputtering technology. CONSTITUTION:Opening parts 25a and 25b are formed in resist 24 applied on a metal layer 23. With the resist 24 as a mask, the layer 23 and an oxide film 22 are etched through the opening parts 25a and 25b. With the layer 23 and the oxide film 22 as masks, a substrate 21 is etched. Thus element isolating grooves 26a and 26b are formed in the substrate 21. After the resist 24 is removed, resist 27 is applied on the entire surface. An opening part 28 is formed. The layer 23 and the oxide film 22 are etched through the opening part 28, and then the substrate 21 is etched. A groove 29 for a capacitor cell is formed in the substrate 21. Thereafter, an oxide film 32 is formed with a thickness corresponding to the depth of the element isolating groves by using RF sputtering technology, by which flattening can be performed, at the same time as the deposition of the oxide film.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention has a Mizohori type capacitor cell which has a groove-contained element isolation region and a confectionery isolation having an isolation insulation 111t at the bottom of the groove. The present invention relates to a method for manufacturing a semiconductor device.

(Prior Art) It is known that in a MO8II dynamic memory cell of the transistor/capacitor type, the cell capacitance can be increased by digging a groove in the silicon substrate. Recently, a method has been announced in which a capacitor cell is structured to have both the function of isolating cells, and a method of reducing the memory area without reducing the memory capacity t- has been announced.

The twenty-ninth example shows, in order of steps, a method for manufacturing a conventional semiconductor device having a trench-embedded element isolation region and a groove-drilled cano-separator cell having a confectionery separation function and having an isolation barrier Ikm at the bottom of the trench. This conventional method will be explained step by step below.

First, oxidation is performed on a silicon substrate using an atmospheric pressure CVD method.
2't, next, a silicon nitride film 3 is grown using a low pressure CVD method, and an oxide film 18!4 is grown using a normal pressure CVD method. Furthermore, a resist 5t-tr is applied thereon, and an opening 6t- is formed in this resist 5 at the grooves of the element isolation region and the capacitor cell region (FIG. 2(a)).

Next, using the resist 5 as a mask, R
By IE method] The above oxide film 4. By etching the three-layer FN of silicon nitride iI3 and oxide 1112,
One opening 7 is formed in this two-layer film (FIG. 2(b)).

Next, after removing the silicon substrate 1, using the three-layer film as a mask, the silicon substrate 1 is etched through the opening 7 to form a trench 8 for the cell and an element in the silicon substrate 1. Form a groove 9 for separation (@Figure 2 (b)
) ).

Next, t-ion implantation (40 Kev) of an impurity (colon B'') for preventing inversion of the element isolation region into the bottom of the trench 9.

2×1013Long/am”) An impurity ion implantation layer 10at is formed. At this time, an impurity ion implantation layer 10 is also formed at the bottom of the groove 8 for the capacitor cell under regular conditions.
6 (Fig. 2 Φ)).

Next, after removing the three-layer film by etching, an oxide film 11 is formed on the entire surface of the substrate l including the inside of the groove 8.9 by low pressure CVD.
grow. Then apply a layer of resin over it to make the surface flat. Thereafter, an etch pack is performed using the RIE method under which the etching rates of the renost and the oxide film 11 are the same, leaving the oxide film 11t as an isolation insulating film only on the entire 1118°9 area. After that, groove 8 for capacitor cell
By excavating the oxide j1iL11 filled in the trench 8 using the RIE method, a portion of the oxide film 11 remains only at the bottom of the trench 8 as an isolation insulating film (see Fig. 2). (C)).

Next, a cell gate oxide film 12 is formed on the inner wall of the capacitor cell trench 8 and the surface of the base 1 by thermal oxidation, and then a polycrystalline silicon film is formed inside the trench 8 and on the base 1 by low pressure CVD. . After that, the polycrystalline silicon film HI4 is etched and packed using RIE method so that the surface becomes flat, and then the polycrystalline silicon film and the cell gate oxide film 1
By carrying out Nog Turning in step 2, the cell consisting of the remaining polycrystalline silicon film buried in the groove 8 is formed. At the same time as the electrode 13t is formed (the cell gate oxide film 12 is left only between the electrode 13 and the substrate 1 (see Fig. 2).
d)).

(Point m while the invention is trying to solve) However, in the above-mentioned more conventional method, an etch pack technique is used in which the resist and the oxide film 1lt are etched at the same etching rate and left only in the oxidized All It-*8,9. This required a step of excavating the oxide film 11 from #jE8 for the Mayu capacitor cell, which made the entire process long and complicated, and there were some intermittent assembly points.

The present invention was made in view of the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can significantly shorten and simplify the process.

(Means for solving the gap m point) In this invention, an etching-resistant mask layer is formed on a silicon substrate, and the silicon substrate is etched using the mask layer as a mask. Grooves and #1 for shallow element isolation are formed on the substrate, and then, using RF bias sputtering technology that allows planarization at the same time as the deposition of the oxide film, a film thickness corresponding to the depth of the groove for element isolation is formed. Form an oxide film.

(Function) In the above method, by forming an oxide film with the above thickness using RF bias sputtering technology, when the oxide film has the shape hX, t-, the confectionery The isolation trench is evenly filled with the oxide film. In addition, in the groove for the deep canosecita cell,
Simultaneously with the filling of the confectionery isolation trench, an isolation insulating film (isolation insulating film) is formed at the bottom with the same thickness as the oxide film of the device isolation trench.

(Example) An embodiment of the present invention will be described below with reference to FIG. 1.

First, a silicon oxide film (Sigh film) 22t-300A is formed on the (100) plane P-type semiconductor silicon substrate 21 by a thermal oxidation method.
grow to a certain extent. Furthermore, a metal N23 having a thickness of several hundred nanometers is grown using aluminum, titanium, tungsten, or a high melting point metal silicide film (FIG. 1(a)).

Next, a resist 24 is applied on the metal layer 23, and a wide element isolation region pattern and a narrow element isolation region pattern are formed on the resist 24 in one round portion 25a, 25b.
is formed by a normal photolithography process (Fig. 1 Φ opening).

Next, using the resist 24 as a mask, the opening 2
5a and 25be, the metal layer 23 and oxide film 22 are etched by the RIE method, and then the silicon substrate 21 is etched by changing the etching conditions of the RIE method and using the metal layer 23 and the oxide film 22 as a mask. In particular, a wide device isolation groove 26 with a depth of about 0.5μ
a, and a narrow device isolation groove 26b of the same depth as the base 2.
Figure 1 (C)).

After the ash is removed, the entire surface is again coated with LENOST 27t, and openings 28 are formed in this resist 27 in a pattern of the cell area using a photolithography process. Then, the metal layer 23 is passed through the opening part 28.
and etching by oxidation 111!221-RIB method,
Subsequently, by etching the silicon substrate 21 by changing the etching conditions of the RIE method, a depth of 1 is etched into the substrate 21.
A groove 29'fr for a capacitor cell having a diameter of approximately μ is formed (FIG. 10)).

Next, after removing the lenost 27, the groove 26a is removed.

On the inner walls of 26b and 29, p-oxide jII 30 is grown at 200A&i degree by thermal oxidation method (FIG. 1(e)). This oxide film 30 is used as a gate oxide film of the capacitor cell in the trench 29 portion for the capacitor cell.

Next, an impurity (boro 7B) t ion implantation (40 KeV,
2 x 10 1ons/ar") L, impurity ion implantation layers 31a and 31b are formed. At this time, an impurity ion implantation layer 31c is also formed under the same conditions at the bottom of the groove 29 for the capacitor cell (@1 figure ( e)).

Next, the oxide film 32t is deposited on the entire surface of the silicon substrate 21 using the RF bias snorting method that allows planarization at the same time as the oxide film is deposited (FIG. 1(e)). The film thickness is the same as that of grooves 26a and 2 for element isolation.
It is assumed that the depth is the same as that of 6b. Then, the groove 26 for element isolation
In a and 26b, when the formation of the oxide film 32 is completed, the oxide film 32 becomes flat and agglomerated. Further, in the deep trench 29 for the canopy cell, an oxide film 32 is formed as an isolation insulating film at the bottom with a thickness similar to that of the oxide film 32 in the element isolation trenches 26a and 26b.

After that, the metal layer 23 is removed, and at the same time, the unsatisfactory oxidation 8132 on it is removed by a lift-off method (first
Figure (f)).

Next, a polycrystalline silicon film 33 is deposited on the entire surface of the silicon substrate 21 including the key 29, and this polycrystalline silicon film 3
3 was etch-packed using the RIE method until the desired thickness (approximately 3000A) was obtained.

This is done for the purpose of controlling the film thickness and flattening the film. After that, the polycrystalline silicon film 33 and the oxidation layer 22 below it are removed.
By performing the patterning, an electrode 33at- of the capacitor cell buried in the groove 29 made of the remaining polycrystalline silicon film 33 is formed, and the electrode 33m is
oxide film 22f: left only between and silicon substrate 21 (first
Illustration)).

(Effects of the Invention) As explained in detail above, the method of this invention has the following advantages:
After forming a deep groove for the canopy cell and a shallow #l for element isolation in the silicon substrate, we used RF bias sputtering technology to form a film with a thickness corresponding to the depth of the element isolation groove. With the completion of the formation of the oxide film, the device isolation trenches were flattened without using etch pack technology.
It becomes possible to fill it with lj-oxide (isolation insulating film).

Further, in the case of δk for a deep capacitor cell, the oxide film can be formed as an isolation insulating film only at the bottom without the step of excavating the oxide film. Since the etch pack technique and digging process can be made unnecessary in this way, the entire process can be shortened and simplified.

Furthermore, according to the method of the present invention, even when there is a groove for separating devices with a wide ring and #Itt- for separating confectionery with a narrow width as in the embodiment, both #1s are simultaneously formed using an oxide film (an isolation insulating film). can be filled flat with a film).

[Brief explanation of the drawing]

FIG. 1 is a process sectional view showing an embodiment of the semiconductor device manufacturing method of the present invention, and @21 is a process sectional view showing a conventional semiconductor device manufacturing method. 21... P-type semiconductor silicon substrate, 22... Oxide film, 23... Metal layer, 26a, 26b... Groove for element isolation, 29... Groove for cano-nine cell, 32...
·Oxide film.

Claims (1)

[Claims] In a method for manufacturing a semiconductor device, in which a capacitor cell trench and an element isolation trench are formed in a silicon substrate, and an isolation insulating film is provided over the entire element isolation trench and at the bottom of the capacitor cell trench. (a) forming an etching-resistant mask layer on the silicon substrate; (b) etching the silicon substrate using the mask layer as a mask to form a deep capacitor cell groove;
(c) After that, the step of forming a trench for shallow device isolation, and (c) the step of forming an R, which can be flattened at the same time as the oxide film is deposited.
By forming an oxide film with a thickness corresponding to the depth of the element isolation groove using F bias sputtering technology, element isolation insulation is simultaneously formed on the entire element isolation groove and the bottom of the capacitor cell groove. 1. A method for manufacturing a semiconductor device, comprising the step of forming a film.