JPS6358851A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To dispense with a mask and to form an element isolation structure by a method wherein with three regions of a field oxide film, an element forming region and element isolation regions formed in a self matching manner, the element isolation regions are formed after the field oxide film is formed and the wide field oxide film and the narrow element isolation regions are simultaneously flattened in an etchback process. CONSTITUTION:A wide field oxide film is formed in a first groove 20 in a self matching manner by a selective oxidation using patterned first and second nitride films 13 and 15 as masks. Moreover, with second grooves 23 formed almost vertically to a semiconductor substrate 11 using the field oxide film 22 and a patterned etching mask material as masks, these second grooves are filled with an embedding material 25 land furthermore, the substrate surface is continuously flattened by etchback and so on and narrow element isolation regions 26a and an element forming region 26 are also formed in a self matching manner. Accordingly, three regions of the field oxide film, the element isolation regions and the element forming region are simultaneously flattened without using a mask for flattening.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and particularly to element isolation technology.

[Conventional technology]

In the past, the PN junction isolation method was the mainstream for device isolation in semiconductor integrated circuit devices;
Since the junction is formed isotropically through the diffusion window 7J), the areal expansion is large, and as the thickness of the epitaxial layer increases, the expansion increases accordingly. For this reason, as devices become finer and the degree of integration becomes more uniform, it becomes necessary to reduce the width and area of device isolation regions, and a thick silicon oxide film (S i 02
), the transition was made to an oxide film separation method (so-called isoplanar technology).

The oxide film isolation method not only significantly reduces the element isolation region compared to the PN junction isolation method, but also converts all regions other than the element formation region (hereinafter referred to as field regions) into a thick oxide film, which reduces wiring. - It was an effective method that reduced stray capacitance between substrates and contributed to speeding up.

In addition, in the oxide film isolation method, the element formation region is covered with an oxidizing silicon nitride film (1iIlt) on a thin silicon oxide film for buffering.
After forming grooves to adjust the volume increase due to oxidation in the region where a thick oxide film is to be formed, along with the edges, a groove is formed using an oxidation-resistant mask consisting of a two-layer film obtained by stacking SisN<).
This is a method in which thermal oxidation is performed to make the element forming region and the element isolation region substantially flat surfaces.

For this reason, oxidation also progresses in the side direction of the groove, and the width of the element isolation region is not necessarily wider than the width defined by photolithography, υ, and the limit is about 10 μm in terms of dimensions.

Furthermore, between the silicon substrate in the element formation region and the oxidation-resistant mask, a wedge-shaped extension of the oxide film from the element isolation region, a so-called nose beak, is formed, and the element formation The oxide film builds up around the area, so-called
However, the disadvantage is that a head is formed and a completely flat surface cannot be obtained.

On the other hand, in recent years, the miniaturization of elements has progressed further, and in order to achieve higher integration, it has become necessary to reduce the width and area of the outer layer element isolation region.

Recently, reactive ion etching (hereinafter referred to as RIE) has been put into practical use as an anisotropic etching technique that etches a film perpendicular to the substrate surface, and has become a new device isolation method that can replace the oxide film isolation method described above. Technology is being developed.

The various new element isolation techniques that have been proposed so far can be roughly classified into the following two categories.

One method is to dig a deep trench in a silicon substrate by RIE, and after forming an oxide film such as silicon dioxide on the inside wall of the trench,
Polycrystalline silicon or the like is deposited thickly and then etched to make it planar. Therefore, when used in a bipolar integrated circuit device, the first point is that the mask for buried diffusion can be completely omitted by forming a deep groove that penetrates the buried diffusion layer formed on the entire surface of the substrate (see below). (referred to as the Mizohori method).

The other method is to cover not only the surface of the element formation region but also the sidewalls of the trench with an oxidation-resistant mask to increase the width of the element isolation region due to lateral oxidation and reduce the noise peak and noise. This method prevents the formation of heads (hereinafter referred to as improved selective oxidation method). This improved selective oxidation method has the advantage that planarization is possible regardless of the separation width and the process is relatively simple (Journal of Electrochemistry: Solid State Science and Technology).
, :5OLID-8TATE 5CIENCE AN
D TECHNOLOGY) Volume 132 No. 7 1985
(See July P, 1705-1707).

[Problem that the invention seeks to solve]

However, in the above-mentioned Mizohori method, it is difficult to flatten the narrow grooves for separating nests and the wide field region grooves at the same time, and therefore a mask for flattening is required. However, there was a problem in that strict mask alignment accuracy was required and the process was further complicated.

On the other hand, in the above-mentioned improved selective oxidation method, since it is practically impossible to isolate through the buried diffusion 7#k, a buried diffusion mask is required. Since the alignment accuracy becomes severe, the trench separation region width cannot be narrowed using the above-mentioned trench-horizon method.

Also, is there a P+ layer for channel stop provided directly under the selective oxide film? Since it comes into contact with the buried layer, there is a problem that the parasitic capacitance t is larger than that of the Mizohori method.

Furthermore, since there is little lateral oxidation, P for channel stop
There is a risk that the + layer will spread outside the isolation oxide film due to diffusion, causing leakage and a drop in breakdown voltage.

Also, as is the case with general selective oxidation methods, defects have occurred on the side walls of the device formation region due to the need to completely form a thick silicon oxide film for device isolation due to prolonged oxidation. There is also the problem of easy occurrence.

The present invention has been made in view of the above-mentioned circumstances, and provides a semiconductor integrated circuit device in which an entire element isolation structure can be formed by a simple process that does not require a mask and by taking advantage of the trench-horizon method and the selective oxidation method. The purpose is to provide a manufacturing method.

[Means for solving problems]

The method for manufacturing a semiconductor integrated circuit device according to the present invention includes (a)
a step of sequentially forming a buffer film, an oxidation-resistant first nitride film, an etching mask material, an oxidation-resistant second nitride film, and a polycrystalline semiconductor film on one main surface of the semiconductor substrate; (b) the above steps; selectively turning the three-layer film of the polycrystalline semiconductor film, the second nitride film, and the etching mask material;
forming a wide first opening and a narrow second opening; (c) fully oxidizing the patterned polycrystalline semiconductor film to form a semi-solid oxide film having all of these parts; (d) as a mask for the semiconductor oxide film having the above-mentioned eaves part;
(e) forming a first @ by selectively removing at least the first nitride film and the buffer coating in the opening of the @1; (e) after this, at least the first and non-turning steps; (f) forming a first opening having no field oxide film;
and after exposing the surface of the semiconductor substrate at the second island opening, forming a second groove in a direction substantially perpendicular to the semiconductor substrate using the field oxide film and the patterned etching mask material as a mask. (g)) After forming a semiconductor oxide film on the inner wall of the second groove, depositing a embedding material on the entire surface of the substrate to perform the second embedding step, and applying the embedding material to the semiconductor substrate. The patterned etching mask material is continuously removed to a surface substantially equal to the surface of the second trench, and an element isolation region in which at least an inner portion and an upper surface portion of the second trench are insulated, and this element isolation region are removed. and a step of removing the first nitride film and the buffer film to expose the surface of the element formation region. It is something.

[For production]

As described above, according to the present invention, a wide field oxide film is formed in the first sea by selective oxidation using at least the T-patterned first and second nitride films as masks. can. Using the field oxide film and the etching mask material used in the patterning school as a mask, a second trench is formed almost perpendicularly to the semiconductor substrate, and this second groove is filled with a filling material, and then continued using an etch pack or the like. Since the target substrate surface is flattened, narrow device isolation regions and device formation regions can be formed in a self-aligning manner.

Moreover, since the three areas of the field oxide film, the element isolation region, and the element formation region can be planarized simultaneously without using a planarization mask, you are freed from the strict mask alignment precision that would be required when using a mask. , there is no need to provide a margin for alignment, and it is possible to miniaturize the layers.

Furthermore, since the second groove for narrow and deep separation can be completely formed, the advantages of the conventional groove digging method and the improved selective oxidation method can all be satisfied at the same time. In other words, not only can the distance between transistors be reduced, but the mask for buried diffusion can be completely omitted in the Nogu Ibora type, and contact between the P+ layer for channel stop (not necessarily required) and the furnace-type buried diffusion layer can be avoided. From the volume between the element formation region and the substrate, t! It can be made extremely small. Moreover, since a widely uniform field oxide film can be obtained even in other semiconductor integrated circuit devices such as a MOS type, the space between the wiring and the substrate can be sufficiently reduced.

Furthermore, after the field oxide film is formed, a second
Therefore, the area where defects are likely to occur on the sidewalls of the element forming area, which is a problem with the normal selective oxidation method, is removed in the trenching process, reducing the influence of defects on the element forming area. It can also be avoided.

〔Example〕

Hereinafter, based on FIGS. 1 and 2, an embodiment in which the present invention is applied to a Non-Ibora type semiconductor integrated circuit device will be described in detail.

First, a first embodiment will be described with reference to FIG.

First, as shown in FIG. 1(A), a P-type silicon substrate 11
An N+ type buried layer 11b with a thickness of about 1 to 2 μm is formed on the entire surface of a, and an N− type epitaxial layer 11c is formed on this with a thickness of 1 to 2 μm.
Form 8 times. These P- type silicon substrates 11a, N+
A semiconductor substrate 11 made of silicon oxide is constructed with a type-embedded Mllb and an N-type epitaxial layer 11c.

Subsequently, a silicon oxide film (S
The first nitride film 13 made of silicon nitride film (SisN4) was etched at about 1000 to 2000'A on the buffer film 12 made of silicon oxide (CVD silicon oxide @ (CVD-SiO21)). A second nitride film 15 of approximately 2000 to 5000 A is added to the material 14 and is made of a silicon nitride film (Si3N4).
About t-1000~200OA is deposited sequentially. Thereafter, a polycrystalline semiconductor film 16'k of about 5000 to 10000'A made of polycrystalline silicon film (Poly-3i) is deposited.

Next, as shown in FIG. 1(B), the polycrystalline silicon film 16, silicon nitride film 15, and CVD silicon oxide film 14 are selectively etched away using a normal photolithography method to mainly form field regions. A wide first opening 17 for forming an element isolation region and a narrow second opening 17a (about 0.5 to 2.0 μm wide) for forming an element isolation region are formed.

Next, as shown in FIG. 1C, the polycrystalline silicon film 16 is thermally oxidized to form silicon oxide (Si) with a thickness of about 1 to 2 μm.
02) into a semiconductor oxide film 18 consisting of. On this occasion,
When the silicon oxide film 18 is modified, the volume increases approximately twice, so that the eaves portion 18a is formed to be stretched due to the lateral bulge. Particularly in the narrow second opening 17a, the eaves 18a of adjacent silicon oxide films 18 are in contact with each other, so that a hollow portion 19 is formed. Here, the lateral overhang of the eaves portion 18a is the width of the polycrystalline silicon film 1.
It is controlled by controlling the film thickness of 6.

Next, as shown in FIG. 1D, using the silicon oxide film 18 having the eaves 18a as a mask, an anisotropic etching technique is used to form a wide first etching field region.
The opening 17 is etched. That is, the silicon nitride film 13 and silicon oxide film 12 in the first opening 17 are selectively etched away, and the N- type epitaxial layer 11c is etched to an appropriate depth of about 0.5 to 1.0 μm. A first groove 20 having a width is formed.

Next, the silicon oxide film 18 is removed, and a third nitride M21 made of a silicon nitride film (Si3N4) is deposited on the entire surface of the base.
After depositing about 00 to 100 OA, etching is performed using an anisotropic etching technique to form the side wall portion of the first groove 20 and the opening @1 as shown in FIG. 1(E). The silicon nitride film 21 is left to be formed on the portion 17 and each side wall portion of the second opening 17a. Although not shown, the silicon oxide film 18 may be removed after the third nitride film 21 is formed on the side wall of the first groove 20. Further, if necessary, a second buffer film made of a silicon oxide film (SiOz3) may be provided on the inner wall of the first groove 20.

Next, as shown in FIG. 1(F), a silicon nitride film 13°15
．． By performing thermal oxidation treatment on the substrate using 21 as a mask, a field oxide film (S
iOz) 22 is formed. This field oxide film 22 grows over the furnace-type buried layer 11b, and the surface of the substrate is generally flattened due to the increase in volume during this growth.

Thereafter, as shown in FIG. 1(G), the silicon nitride film 15 on the surface of the substrate, the silicon nitride film 13 remaining in the first opening 17, that in the second opening 17a, and the first silicon nitride film 15 are removed.
The silicon nitride film 21 on the side wall of the opening 17.17a of the first and second openings 17.17a and 2.
The buffering silicon oxide film 12 leaked through the openings 17 and 17a is removed by etching, leaving the entire surface of the N-type epitaxial layer 11c exposed.

Next, as shown in FIG. 1(H), using the CVD silicon oxide film 14 and field oxide film 22 as masks, the silicon substrate
Anisotropic etching 1-[shi-1N
- type epitaxial layer 11C and furnace type embedding Ji! +11
through BIX to reach the P″″ type silicon 11 board 11a.
A narrow second groove 23 having a depth of about 4 to 6 μm is formed. If necessary, ciboron ions (B)f are implanted into the bottom of the second groove 23 by self-alignment to form a P-type channel stop layer (not shown).

Next, as shown in FIG. 1 CI), a
After forming a semiconductor oxide film 24 made of a thermal oxide film (Sigh) with a thickness of about 0.000 to 3000 μm, a embedding material 25 made of a polycrystalline silicon film is deposited to a thickness of about 4 to 6 μm over the entire surface of the substrate. Insert the second groove.

Subsequently, the polycrystalline silicon film 25 is etched using a known technique. The depth of this etch pack is set to a level approximately equal to the surface of the substrate, and is set to an appropriate depth so that the element forming region 26 and the element isolation region 26a are flat in the final step. Furthermore, the CVD silicon oxide film 14 is removed,
Second groove 23 using silicon nitride Ii2.13 as a mask
The surface of the polycrystalline silicon film 25 inside is covered with a thermal oxide film (Si(h
When the semiconductor oxide film 25a is modified to consist of
The cross-sectional structure is as shown in J).

Finally, as shown in FIG. 1(K), the silicon nitride film 13
Then, the silicon oxide film 12 is sequentially removed, and then a desired element is formed in the element forming region 26, thereby obtaining a non-ipolar type semiconductor integrated circuit device.

In this way, when applied to a failed EA'ft bipolar semiconductor integrated circuit device, the narrow and deep second groove 23 for element isolation can be formed in a self-aligned manner, so it is possible to reduce the distance between transistors. This means that the mask for embedded diffusion can be omitted. Moreover, when forming the P+ type channel stop layer, there is no lateral inward expansion of the P+ type channel stop layer and the buried diffusion layer 11b, and contact between the two can be avoided. The parasitic capacitance between the two can be made extremely small.

Next, referring to FIG. 2, a second embodiment of the present invention will be described. Note that the steps of the first embodiment described above are the same up to the step of forming the deep second groove 23 shown in FIG. Otherwise, the same reference numerals will be used to describe the relevant parts.

Continuing from FIG. 1(H), as shown in FIG. 2(A), a semiconductor oxide film 24 made of a thermal oxide film (St(hl) is formed on the inner wall of the second trench 23, and then CVD is applied to the entire surface of the substrate. Buried material 25 made of silicon oxide film (CVD-31O2)
The second groove 23 is embedded in the first metal by depositing it completely thickly.

Subsequently, as shown in Figure 2 CB), the known technology is '1) CVD.
The silicon oxide film 25 is etched back to expose the first nitride film 13 made of a silicon nitride film (Si3N4), and the etching is stopped just in case. In the figure, 26 is an element formation region, and 26a is an element isolation region.

Thereafter, as shown in FIG. 2(C), the buffer membrane 12 made of the silicon nitride film 13 and silicon oxide film (SiOz) is removed, and then a desired element is fabricated in the element formation area 26 and then removed. It will be an Ibora type semiconductor integrated circuit device.

According to this second example 81, the oxidation process (
(see FIG. 1(J)) is now 3 thick, which not only shortens the process, but also completely suppresses the influence of nose beaks in the element forming region 26 formed in the same process.

In addition, in the second embodiment, since the element isolation region 26a is entirely composed of a silicon oxide film, a selective oxidation process (FIG. 1 (F
It is possible to completely flatten the slight surface step difference on the field oxide film 22 that occurs in the step (see ) at the same time as filling with the CVD silicon oxide film 25 and etching notches. Furthermore, when forming an element, a structure can be obtained in which a self-aligned process, which is an advantage of the oxide film separation method, can be adopted in a highly advantageous manner.

Here, in each of the above-mentioned embodiments, the case where the present invention is applied to a non-polar type semiconductor integrated circuit device is described, but the scope of application of the present invention is not limited to this, and the present invention is not limited to this. It can be widely applied to semiconductor integrated circuit devices.

〔Effect of the invention〕

As described in detail above, according to the present invention, the three regions of the field oxide film, the element formation region, and the element isolation region are formed in a self-aligned manner, and the element isolation region is formed after the field oxide film is formed. During the formation and etch-pack process, VC is applied so that the wide-field Fieldy oxide film and the narrow-width element isolation region are simultaneously planarized.

Therefore, a mask such as a flattening mask f:f is required, freeing from strict mask alignment accuracy, eliminating the need for alignment allowance, simplifying the process, and avoiding the influence of defects on the lattice formation area. This has the effect of making it possible to miniaturize the elements of the thin layer.

Furthermore, according to the present invention, it is possible to perform bonding that takes full advantage of the advantages of both the conventional trench trenching method and selective oxidation method through a simple process that does not require the above-mentioned mask, and the parasitic capacitance: ik can be significantly reduced. This has the effect that it is possible to obtain an excellent element isolation structure that is fine and has high flatness.

[Brief explanation of drawings]

FIG. 1 is a process sectional view explaining the first embodiment of the present invention;
FIG. 2 is a process cross-sectional view illustrating a second embodiment of the present invention. 11... Semiconductor substrate, 12... Buffer coating, 13.
... first nitride film, 14... etching mask material,
15... Second nitride film, 16... Polycrystalline semiconductor film,
17...first opening, 17a...second opening,
18...Semiconductor oxide film, 18a...Eave part, 20...
- First groove, 21... Third nitride film, 22... Field oxide film, 22a... Field region, 23...
- Second groove, 24... Semiconductor oxide film, 25... Burying material, 26... Confectionery forming region, 26 a... Element isolation region. Patent Applicant: Oki Electric Industry Co., Ltd. Dangerous Prisoner Figure 1 20 1llt^ 2I゛Sito311'i1I Lha11 (S Todoro JN4) 22
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Claims (1)

[Claims] (1) (a) Step of sequentially forming a buffer film, an oxidation-resistant first nitride film, an etching mask material, an oxidation-resistant second nitride film, and a polycrystalline semiconductor film on one main surface of a semiconductor substrate and (b) selectively patterning the three-layer film of the polycrystalline semiconductor film, the second nitride film, and the etching mask material to form a wide first opening and a narrow second opening. (c) oxidizing the patterned polycrystalline semiconductor film to modify it into a semiconductor oxide film having an eaves part; (d) using the semiconductor oxide film having the eaves part as a mask; ,
selectively etching away at least the first nitride film and the buffer film in the first opening to form a first groove; (e) after this, at least the first and patterned oxidizing using a second nitride film as a mask to selectively form a field oxide film in the first groove; (f) a first opening having no field oxide film;
and after exposing the surface of the semiconductor substrate in the second opening, forming a second groove in a direction substantially perpendicular to the semiconductor substrate using the field oxide film and the patterned etching mask material as a mask. (g) forming a semiconductor oxide film on the inner wall of the second trench, and then depositing a embedding material on the entire surface of the base to bury the second trench; (h) applying the embedding material to the semiconductor oxide film; an element isolation region in which at least an inner wall portion and an upper surface portion of the second groove are insulated by continuously removing the patterned etching mask material to a surface substantially equal to the surface of the substrate;
forming an element formation region surrounded by the element isolation region; and (i) thereafter, removing the first nitride film and the buffer film to expose the surface of the element formation region. A method of manufacturing a semiconductor integrated circuit device, comprising: