JPH09306984A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device having a buried-element isolation structure, which can make small a mask alignment margin and prevent generation of junction leakage when contact is made between a surface of a semiconductor substrate and a wiring layer. SOLUTION: An insulating film 102 and a film 103 are formed on a semiconductor substrate 101, a groove is made in an element isolation region, the insulating film 102 is etched and retreated to define a gap between the element region and film 103, insulating films 104 and 105 are formed thereon to bury the gap, an insulating film 106 is deposited to bury the groove, the film 103 and insulating films 102, 104, 105 on the element region are removed to expose a surface of the element region, an upper end face of the insulating film 104 of the groove side wall is covered with an insulating film 105a, an insulating film 107 is deposited on the entire surface of the stack, and a part of the stack corresponding to the element region is formed therein with a hole to expose the surface of the element region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a device having a buried element isolation structure.

[0002]

2. Description of the Related Art In order to perform element isolation in a semiconductor device, a groove is formed in an element isolation region on a surface of a semiconductor substrate and the groove is filled with an insulating material.

Conventionally, a device having such an element isolation structure has been manufactured by the following method. As shown in FIG. 4A, a groove is formed in the element isolation region on the surface of the semiconductor substrate 201 to make the element region convex. A silicon oxide film 202 is formed on the entire surface of the semiconductor substrate 201 in which the groove is formed, and a silicon oxide film 203 is deposited on the surface by LPCVD. This silicon oxide film 203 is deposited thicker than the depth of the groove. The silicon oxide film 203 is polished and planarized until the surface of the element region of the semiconductor substrate 201 is exposed.

As shown in FIG. 4B, a silicon oxide film is deposited on the entire surface to form an interlayer insulating film 204, and a resist film is used to open a hole for making contact with a portion corresponding to an element region. Make a hole.

If a mask misalignment occurs between the photomask used to form the groove and the photomask used to open the holes in the interlayer insulating film 204, FIG. 2 in the side wall of the groove as shown in
06 is dug.

When a wiring layer is formed on the surface in this state, the semiconductor substrate 2 below the diffusion layer 205 in the element region is formed.
There is a problem that a junction leak occurs between 01 and the wiring layer 204.

According to another conventional method, as shown in FIG. 5A, after forming not only the silicon oxide film 302 but also the silicon nitride film 303 on the inner wall of the groove of the semiconductor substrate 301, the silicon oxide film is formed. The groove is filled with 304. After this,
As shown in FIG. 5B, an interlayer insulating film 305 is formed and a contact hole is opened.

According to this method, even if the mask misalignment occurs, the silicon nitride film 303 remains without being removed, but the silicon oxide film 302 is removed. This allows
The hole 307 is dug along the side wall of the groove, and the junction between the diffusion layer 306 and the semiconductor substrate 301 is exposed.
Therefore, when a wiring layer is formed on this interlayer insulating film 305, a junction leak occurs with the semiconductor substrate 301.

In order to prevent such a junction leak by the conventional method, the contact area between the diffusion layer and the wiring layer must be made large in order to provide a margin for mask misalignment, and the element area It was causing an increase.

[0010]

As described above, conventionally, in order to prevent the junction leak, it is necessary to have a margin for the mask misalignment, which causes an increase in the element area.

The present invention has been made in view of the above circumstances, and in a method of manufacturing a semiconductor device having a buried element isolation structure, a margin for mask alignment is provided when a contact is made between the surface of a semiconductor substrate and a wiring layer. It is an object of the present invention to provide a manufacturing method that can reduce the size and prevent the occurrence of a junction leak.

[0012]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a first insulating film on the surface of a semiconductor substrate, and a step of forming the first insulating film on the surface of the first insulating film. Forming a film made of a material different from that of the insulating film, patterning while leaving a portion of the first insulating film and the film corresponding to the element region, and further forming a groove in the element isolation region of the semiconductor substrate. A step of forming, a step of forming a gap between the element region and the film by etching the side surface of the first insulating film to make it recede, and a second insulating film over the entire surface, A third material made of a material different from that of the second insulating film
And the insulating film are formed in order, and the gap between the element region and the film is filled with the second and third insulating films, and a fourth insulating film is deposited on the entire surface to separate the elements. Filling the region and performing etch back to leave the first, second, and third insulating films and the film above the device region; and etching the film above the device region. And removing the portion of the third insulating film above the gap between the device region and the film by etching, and removing the first and the third insulating films on the surface of the device region. The second insulating film is removed to expose the surface of the element region, and the upper end surface of the second insulating film formed on the sidewall of the groove of the element isolation region is covered with the third insulating film. And a step of depositing a fifth insulating film on the entire surface, A step of exposing the surface of the element region by opening a portion corresponding to the region, and when opening the fifth insulating film, the side surface of the groove of the element isolation region is at least the second side. And the third insulating film.

Here, if the second insulating film is a silicon oxide film and the third insulating film is a silicon nitride film, a large etching selection ratio can be obtained, and a hole is formed in the fifth insulating film. When it is performed, it is possible to more reliably prevent the side surface of the groove in the element isolation region from being exposed.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a method of manufacturing a semiconductor device according to the present embodiment as an element vertical section for each step. First, as shown in FIG. 1A, a silicon oxide film 102 is formed on the surface of a semiconductor substrate 101 by a thermal oxidation method at about 850 degrees Celsius to a thickness of about 150 to 300 angstroms. A polycrystalline silicon film 103 is formed on the surface of the silicon oxide film 102 by the CVD method to have a thickness of about 3000 angstroms so that a large etching selection ratio can be obtained. Further, the polycrystalline silicon film 103
A silicon oxide film 111 having a thickness of about 3000 angstrom is formed on the surface of the substrate by the CVD method.

As shown in FIG. 1B, the silicon oxide film 11
A resist is applied on the first layer 1, and a portion corresponding to the element region is left and the other portions are removed to form a resist film 112. Using the resist film 112 as a mask, the silicon oxide film 111 is etched as shown in FIG. 1C to remove the resist film 112.

As shown in FIG. 1D, the silicon oxide film 11 is formed.
Using 1 as a mask, the polycrystalline silicon film 103, the silicon oxide film 102, and the semiconductor substrate 101 are sequentially etched. As a result, a groove is formed in the element isolation region of the semiconductor substrate 101.

In this state, as shown in FIG. 1E, dilute hydrofluoric acid treatment is performed to recede the silicon oxide film 102 between the element region and the polycrystalline silicon film 103 to form a groove.
It is necessary to set the amount of retreat so that a sufficient gap can be formed so that the silicon oxide film and the silicon nitride film to be formed later can enter. However, silicon oxide film 1
It should be noted that if 02 is made to recede too much, the area covered with the silicon oxide film 102 and in which elements can be formed becomes small.

Next, as shown in FIG. 1F, a silicon oxide film 104 is formed on the entire surface by a thermal oxidation method. The thickness of the silicon oxide film 104 is set so that the silicon nitride film to be formed later can enter the gap between the polycrystalline silicon film 103 and the element region of the semiconductor substrate 101.

Further, as shown in FIG. 1G, the silicon nitride film 10 having a thickness of about 50 to 60 angstroms is formed by the CVD method.
Form 5 over the entire surface.

As shown in FIG. 1H, a silicon oxide film 106 is deposited on the entire surface by the LPCVD method. The thickness of the silicon oxide film 106 is set so that the groove can be filled. Anisotropic etching such as reactive ion etching or CMP (Chemical Mechanical Polishing)
g) Etch back by method to flatten the surface.

As shown in FIG. 1 (i), CDE (Chemical D
Isotropic etching such as ry etching is performed to remove the polycrystalline silicon film 103 formed to protect the element region.

Next, as shown in FIG. 1 (j), a portion of the silicon nitride film 105 above the gap between the polycrystalline silicon film 103 and the element region is removed by isotropic etching such as CDE.

As shown in FIG. 1K, the portions of the silicon oxide films 102 and 104 above the element region are removed by isotropic etching. As a result, the silicon nitride film 105a covers the upper end surface of the silicon oxide film 104 around the element region.

As shown in FIG. 1L, an interlayer insulating film 107 made of a silicon oxide film is deposited on the entire surface by a CVD method, and a resist not shown is applied. A resist film having a hole corresponding to the element region is formed, and the interlayer insulating film 107 is etched using this as a mask to open a contact hole. At this time, even if the misalignment of the mask occurs and the hole of the interlayer insulating film 107 and the element region are misaligned, as described above, the silicon oxide film 104 is formed.
The upper end surface of is covered with a silicon nitride film 105a. Therefore, when the interlayer insulating film 107 is etched with a high etching selection ratio between the silicon oxide film 104 and the silicon nitride film 105, the silicon oxide film 104 is etched.
Is not removed, and the exposed portion of the junction between the diffusion layer 108 and the semiconductor substrate 101 on the side surface of the trench can be prevented. This can prevent a leak from occurring between the wiring layer formed on the upper surface and the junction of the diffusion layer 108. Therefore, it is not necessary to take a large contact region between the wiring layer and the element region in consideration of the mask misalignment, and the element area can be reduced.

Here, without directly forming the silicon nitride film 105 on the surface of the semiconductor substrate 101, the silicon oxide film 10 is formed.
No. 5 is formed in between, which is for relieving stress.

From the time when the planarization by etching back shown in FIG. 1H is completed, the element region in FIG. 1K is exposed and the upper end surface of the silicon oxide film 104 is covered with the silicon nitride film 105a. By the time
In addition to the steps shown in FIGS. 1I to 1J, other steps are possible.

For example, similarly to the step shown in FIG. 1I, the polycrystalline silicon film 103 is removed by isotropic etching as shown in FIG. 2I.

Next, as shown in FIG. 2 (j), isotropic etching is performed to form the silicon oxide films 102, 104 and 106.
Of the above, a portion above the element region is removed. Then, the silicon nitride film 105 is etched. At this time, it is necessary to prevent the silicon nitride film 105a covering the upper end surface of the silicon oxide film 104 from being removed. After that, the interlayer insulating film 107 having the contact holes opened is formed through the steps of FIGS. 1K to 1L in the same manner.

Alternatively, as shown in FIG. 3I, isotropic etching is performed to remove the silicon nitride film 104 to the same depth as the polycrystalline silicon film 103.

As shown in FIG. 3J, isotropic etching is performed to remove the polycrystalline silicon film 103. Further, the silicon oxide films 102 and 104 located above the element region are removed by isotropic etching. After this, FIG.
The interlayer insulating film 107 is formed through the steps (k) to (l).

In any of the above-described embodiments, the silicon oxide film 104 is formed on the surface of the inner wall of the groove, and the upper end surface of the silicon oxide film 104 is covered with the silicon nitride film 105a. Since the contact hole is formed in the film 107, the side surface of the trench can be prevented from being exposed and a junction leak with the wiring layer can be prevented.

The above-described embodiment is an example and does not limit the present invention. For example, in the embodiment, the side surface of the trench in the element isolation region is covered with the silicon oxide film 104 and the silicon nitride film 105. However, the side surface of the groove may be covered with an insulating film made of another two kinds of materials as long as the etching selection ratio can be made large.

[0034]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the side surface of the trench of the element isolation region is covered with two kinds of insulating films capable of achieving a large etching selection ratio. Since a hole corresponding to the element region of the interlayer insulating film is opened, even if a mask misalignment occurs between the photomask when forming the groove and the photomask when forming the hole in the interlayer insulating film, Since it is possible to prevent the occurrence of a junction leak between the semiconductor substrate and the wiring layer formed on the interlayer insulating film by exposing the side surface of the groove, it is possible to improve the yield and to prevent the mask misalignment. In consideration of the above, it is not necessary to make a large contact region between the element region and the wiring layer, and the element area can be reduced.

[Brief description of drawings]

FIG. 1 is a vertical cross-sectional view of an element showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, step by step.

FIG. 2 is a vertical cross-sectional view of an element showing a method for manufacturing a semiconductor device according to another embodiment of the present invention, step by step.

FIG. 3 is a vertical cross-sectional view of an element showing a method for manufacturing a semiconductor device according to still another embodiment of the present invention in steps.

FIG. 4 is a vertical cross-sectional view of an element showing a conventional method for manufacturing a semiconductor device for each step.

FIG. 5 is a vertical cross-sectional view of an element showing another conventional method for manufacturing a semiconductor device, step by step.

[Explanation of symbols]

 101 semiconductor substrate 102, 104, 106, 111 silicon oxide film 103 polycrystalline silicon film 105, 105a silicon nitride film 107 interlayer insulating film 112 resist film

Claims (3)

[Claims] 1. A step of forming a first insulating film on a surface of a semiconductor substrate, and a step of forming a film made of a material different from that of the first insulating film on the surface of the first insulating film. Patterning the first insulating film and a portion of the film corresponding to the device region, and forming a groove in the device isolation region of the semiconductor substrate; and forming a groove on a side surface of the first insulating film. A step of performing etching to recede to form a gap between the element region and the film; a second insulating film on the entire surface; and a third insulating film made of a material different from the second insulating film. A step of sequentially forming a film and filling a gap between the element region and the film with the second and third insulating films; and a step of depositing a fourth insulating film on the entire surface to form the element isolation region. By embedding and etching back, the first and the first regions are formed on the device region. A step of leaving the third insulating film and the film left unetched, a step of removing the film above the element region by etching, and a step of removing the film of the third insulating film from the element region and the film. Removing a portion above a gap between the element region by etching, and removing the first and second insulating films on the surface of the element region to expose the surface of the element region to separate the element. Forming a state in which the upper end surface of the second insulating film formed on the sidewall of the groove in the region is covered with the third insulating film; and depositing a fifth insulating film on the entire surface, And a step of exposing the surface of the element region to expose the surface of the element region. When the hole is formed in the fifth insulating film, the side surface of the groove of the element isolation region is at least the second and Characterized by being covered by either one of the third insulating films The method of manufacturing a semiconductor device to be. 2. A step of forming a first insulating film on the surface of a semiconductor substrate, and a step of forming a film made of a material different from that of the first insulating film on the surface of the first insulating film. Patterning the first insulating film and a portion of the film corresponding to the device region, and forming a groove in the device isolation region of the semiconductor substrate; and forming a groove on a side surface of the first insulating film. A step of performing etching to recede to form a gap between the element region and the film; a second insulating film on the entire surface; and a third insulating film made of a material different from the second insulating film. A step of sequentially forming a film and filling a gap between the element region and the film with the second and third insulating films; and a step of depositing a fourth insulating film on the entire surface to form the element isolation region. By embedding and etching back, the first and the first regions are formed on the device region. A step of leaving the third insulating film and the film remaining, and a step of removing a portion of the third insulating film above a gap between the element region and the film by etching. A step of removing the film above the element region by etching, and removing a portion of the first, second and third insulating films above the element region by etching to remove the surface of the element region. And exposing the upper end surface of the second insulating film formed on the sidewall of the trench in the element isolation region to the state of being covered with the third insulating film, and a fifth insulating film over the entire surface. And exposing the surface of the element region by opening a portion corresponding to the element region and exposing the surface of the element region, the side surface of the groove of the element isolation region is formed when the hole is formed in the fifth insulating film. At least one of the second and third insulating films The method of manufacturing a semiconductor device characterized by being covered with. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film is a silicon oxide film and the third insulating film is a silicon nitride film.