JPH0457262B2 - - Google Patents

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention is applicable to a high-efficiency encoding device used for efficiently transmitting call information for international telephone calls. Regarding a signal processing method for inputting and outputting data according to a signal, in particular, a phase monitoring circuit monitors the phase difference between input and output request signals, and the data input and output times are determined according to the output of this monitoring circuit. The present invention relates to a signal processing method for determining position.

(Prior Art) FIG. 6 is a block diagram showing an example of a conventional asynchronous signal processing device.

In Figure 6, 11 is input data IDATAO
13 indicates an input request signal ISYNCI. 1
5 and 17 indicate the first and second DELAY, respectively, and 19 and 21 indicate the first and second selectors, respectively. In addition, 23 indicates an elastake memory (ESM), and 25 indicates a phase monitoring circuit (PHC).
shows. Further, 27 indicates output data ODATAO, and 29 indicates output request signal OSYNCI. In this device, input data 11 is written to the elastic take memory 23 in response to the input request signal 13, and data 11 is read in response to the output request signal 29. However, the input request signal 13 and the output request signal 29 are In the event of a conflict, writing to the elastake memory 23 and reading from this memory 23 may overlap, resulting in an undefined value being output. In order to prevent this, a phase monitoring circuit 25 as shown in detail in FIG. 7 has been used to control writing to the erasure memory.

In FIG. 7, 31 indicates a first differential circuit to which the output request signal 29 is input, and 33 indicates a second differential circuit to which the input request signal 13 is input. Also, 3
5 and 37 indicate first and second counters, respectively, and a predetermined single monitoring time α is connected to the input D of each of the first and second counters 35 and 37. The read instruction terminal is connected to the output terminal of the second differentiation circuit 33,
A read instruction terminal of the second counter 37 is connected to an output terminal of the first differentiation circuit 31. Also, 3
9 and 41 each represent an inverter, 43 and 45 each represent an AND circuit, and 47 represents an OR circuit. Further, 49 indicates a clock signal, which is connected to the first and second counters 35 and 37, respectively.

In such a circuit, for example, data corresponding to a single monitoring time α is read from the input D of the first counter 35 in accordance with the output signal of the second differentiating circuit 33, and the time α is counted. Meanwhile output terminal
An output signal is output to CO. Furthermore, by using the inverter 39 and the AND circuit 43 to AND the signal at the output terminal of the first counter 35 and the output of the first differentiating circuit 31, the input request signal 13 is caused to rise. The time difference from the time when the output request signal 29 rises to the time when the output request signal 29 rises, and the monitoring time α
It is possible to make a comparison with Similarly, the second counter 37 can be used to compare the time difference from the time when the output request signal 29 rises to the time when the input request signal 11 rises and the monitoring time α. Furthermore, the OR circuit 47 calculates the logical sum of the output signals of the AND circuits 43 and 45 and sets the phase flag.
PFLG is output, and writing of the input data 11 to the elastake memory 23 is controlled by this phase flag PFLG.

Further, since it has the elastic take memory 23, data can be written and read sequentially regardless of minute jitters between the input request signal 11 and the output request signal 29.

(Problem to be solved by the invention) However, in the conventional method, when the phase difference between the input request signal and the output request signal exceeds the memory limit of the elastake memory (during slip), the elastake memory is reset. In this case, a large amount of data is lost, which is equal to the capacity of the elastake memory. Therefore, for example, there are problems in that the data transmitted at the time of a slip is illegible, and even if an attempt is made to correct an error by taking the missing data into account, it cannot be corrected because a large amount of data is missing. Ta.

Furthermore, the conventional method requires a complicated circuit consisting of an elastake memory, DELAY1, DELAY2, and a selector to absorb the phase shift of the asynchronous input and output request signals.

The purpose of this invention is to solve the above-mentioned problems,
It is an object of the present invention to provide a signal processing method capable of inputting and outputting data according to asynchronous input request signals and output request signals without causing many data omissions at once.

(Means for Solving the Problem) In order to achieve this object, according to the present invention, a signal is provided that inputs and outputs data in response to an asynchronous periodic input request signal and a periodic output request signal. A signal processing method in which data captured in an output buffer is outputted to the outside in response to the above-mentioned output request signal, wherein the phase difference between the input request signal and the output request signal is determined at a first time and the first time. The second time period shorter than the first time period is used for monitoring, and the data acquisition into the output buffer is performed under the first acquisition condition immediately after the input request signal is input.
The second input request signal is executed at a time position between adjacent input request signals.
When the above-mentioned phase difference is larger than the above-mentioned first time, the above-mentioned first capture condition is performed, and when the above-mentioned phase difference is smaller than the above-mentioned second time, It is characterized by a transition to the second import condition described above.

(Actions) According to the configuration of the present invention, the following actions can be obtained.

Since the input request signal and the output request signal are asynchronous to each other and each is periodic, for a while after the phase difference between the two signals (hereinafter referred to as "phase difference") once becomes larger than the first time. The output request signal arrives with a relatively large phase difference with respect to the input request signal, and after the phase difference once becomes smaller than the second time, the output request signal arrives with a relatively small phase difference with respect to the input request signal. Arrival. In the present invention, when the phase difference is larger than the first time, data is taken into the output buffer immediately after the input request signal is input (performed under the first take-in condition), and when the phase difference is larger than the second time. If the data is small, the data is loaded into the output buffer at a time position between adjacent input request signals (performed under the second loading condition), so when data is being output from the output buffer due to the output request signal, the output buffer is It is possible to prevent new data from being imported into the .

Furthermore, when the phase difference is larger than the first time, the transition is made to the first acquisition condition, and when it is smaller than the second time, the transition is made to the second acquisition condition. If the time is more than the first time but less than the first time, the first import condition and the second
This will be performed according to the preset conditions among the import conditions. That is, when the phase difference is greater than or equal to the second time and less than or equal to the first time, the condition for taking in data to the output buffer transitions to hysteresis.
Therefore, where the phase difference should originally be smaller than the second time or larger than the first time, jitter occurs in both or one of the signals and the phase difference is greater than or equal to the second time. Even if the time period deviates to a region shorter than the first time period, data can be taken into the output buffer under appropriate conditions.

(Embodiments) Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that these figures are merely shown schematically to the extent that the present invention can be understood, and the means for realizing the present invention are not limited to the illustrated examples. Further, in these figures, the same components are designated by the same reference numerals. or,
Components that are the same as those in the prior art are designated by the same reference numerals.

FIG. 1 is a block diagram showing an embodiment of a signal processing device suitable for use in the signal processing method of the present invention.

In FIG. 1, 51 is a phase monitoring circuit for monitoring the phase difference between the input request signal and the output request signal using a first monitoring time α and a shorter second monitoring time β. (PSC), and 53 indicates a signal processing circuit (SPP) that determines the input/output time position based on the determination result. The output S ₃ of the phase monitoring circuit 51 is connected to the PFLG terminal 54 of the signal processing circuit 53.

The input terminal 55 of the input data (IDATA) 11 is
It is connected to an IR register 57, and this IR register 57 is connected to an input terminal (INDATA) 61 of a signal processing circuit (SPP) 53 via a bus driver 59. The bus driver 59 is the signal processing device 53
The contents of the IR register 57 are output to an input terminal (INDATA) 61 in response to an input data acquisition signal (IN) 63 from the IR register 57. The input terminal 65 of the input request signal (ISYNCI) 13 is the IR register 5
7, the phase monitoring circuit 51, and an interrupt signal terminal (INT) 66 of the signal processing circuit 53.

Further, the output data terminal (OUTDATA) 69 of the signal processing circuit 53 is connected to an output register buffer (ORB) 71, and this output register buffer 71 receives the instruction signal (OUT) from the output instruction signal terminal 73. Accordingly, output data is read from the signal processing circuit 53. The output register buffer 71 is connected to the OR register 75, and furthermore, this
OR register 75 is connected to output terminal 77.

In addition, the input terminal 79 of the output request signal (OSYNCI) 29 is connected to the phase monitoring circuit 51 and the OR register 75.
It is connected to.

FIG. 2 is a circuit diagram showing details of the phase monitoring circuit 51 shown in FIG. 1. The phase monitoring circuit 51 will be explained below with reference to FIG.

The input terminal 79 for the output request signal shown in FIG. 1 is connected to the first differential circuit (D1) 81, and the input terminal 65 for the input request signal is connected to the second differential circuit (D2) 83. The output terminal of the first differentiating circuit 81 is connected to the AND circuit 85, the AND circuit 89, and the read instruction signal input terminals of the second counter 95 and the fourth counter 99, respectively. The output terminal of the second differentiating circuit 83 is connected to the AND circuit 87 and the AND circuit 87.
A circuit 91, a read instruction signal input terminal of each of the first counter 93 and the third counter 97,
The delay circuit 116 is connected to the delay circuit 116, respectively. or,
First, second, third and fourth counters 93, 95,
97 and 99 have a clock signal (CLK) 101
are connected to each other.

The output terminal of the first counter 93 is the AND circuit 8
5. Connected to the AND circuit 87 and the (enable) terminal of the first counter, and the second counter 95
The output of is connected to the AND circuit 85, the AND circuit 87, and the terminals of the second counter. The output terminal of the third counter 97 is connected to the inverter 103 and the terminal of the third counter 97, and the output terminal of the fourth counter 99 is connected to the inverter 103 and the terminal of the third counter 97.
and a terminal of the fourth counter 99.
Also, the output terminal of the inverter 103 is connected to the AND circuit 8.
9, the output terminals of the inverter 105 are connected to an AND circuit 91, respectively. Furthermore, the output terminals of the AND circuit 85 and the AND circuit 87 are connected to the OR circuit 1.
07, and AND circuit 89 and
The output terminal of the AND circuit 91 is connected to the OR circuit 109.

The output terminal of the OR circuit 107 is connected to each CK of the delay flip-flop circuits 117 and 118.
The terminal and the output terminal of the OR circuit 109 are connected to the inverter 113, respectively, and the delay circuit 1
The output of 16 is the delay flip-flop circuit 11.
The output Q of the delay flip-flop circuit 117 is input to the D terminal of the delay flip-flop circuit 118. Further, the output Q of the delay flip-flop circuit 118 is connected to an inverter 111, and the output terminal of this inverter 111 is connected to the input terminal S of a flip-flop (FF) 115. Further, the output terminal of the inverter 113 is connected to the input terminal R of the FF 115. still,
The output terminal Q of this FF 115 is connected to the PFLG terminal 54 of the signal processing device 53 shown in FIG. 1, and outputs an output signal _S3 .

Further, data corresponding to a predetermined monitoring time α is connected to the input terminals D of the first and second counters 93 and 95, and data corresponding to α is connected to the input terminals D of the third and fourth counters 97 and 99. Data corresponding to a predetermined monitoring time β is connected to different values, and each monitoring time corresponding data is configured to be read in accordance with a signal input to a read instruction input terminal of each counter.

In such a phase monitoring circuit 51, the first counter 93 counts the monitoring time α and the third counter 97 counts the monitoring time β in accordance with the pre-differentiated output signal _S1 of the input request signal 13. Output "0" to each output terminal, and
Outputs "1" except when counting is in progress. Similarly, in response to the pre-differentiated output signal _S2 of the output request signal 29, the second counter 95 changes the monitoring time α to the fourth counter 99.
counts the monitoring time β, outputs “0” to each output terminal during counting, and
Outputs "1" except when counting is in progress.

Further, the AND circuit 85 monitors whether the signal S ₂ arrives at a time other than when the first counter 93 and the second counter 95 are counting. Similarly, AND circuit 8
7, the first counter 93 and the second counter 95
The arrival of the signal S ₁ other than during the counting of is monitored. Therefore, if the time difference between the rising time of the input request signal 13 and the rising time of the output request signal 29 (hereinafter also simply referred to as time difference) is larger than the monitoring time α time, the next The output of the OR circuit 107 becomes "1" twice until ISYNCI. Therefore, the outputs of delay flip-flop circuits 117 and 118 become "1" one after another. On the other hand, if the time difference is smaller than the monitoring time β, the output of the OR circuit 109 becomes "1". Therefore, in FF115, if time difference > α,
“1” is output as the output signal S ₃ to the PFLG terminal 54, and “0” is output as the output signal S ₃ to the PFLG terminal 54 if the time difference <β.

In addition, the monitoring time setting conditions are α>β, α<
If the period of S ₁ and the period of α<S ₂ are set, the delay flip-flop circuit 11
8 and the OR circuit 109 do not output signals at the same time. Therefore, after being activated by the output of the delay flip-flop circuit 118, the FF 115 monitors the output signal from the OR circuit 109, and similarly, after being activated by the output of the OR circuit 109, it monitors the output signal from the OR circuit 109. The output signal of flip-flop circuit 118 will be monitored. Therefore, since the monitoring time can have hysteresis, a stable output _S3 can be obtained even if minute jitter occurs in the signals _S1 and _S2 .

Next, the signal processing circuit 53 for determining the data input/output time position based on the phase difference determination result will be described with reference to FIGS. 1 and 3.

FIG. 3 is a flowchart for determining the output time position of data based on the signal _S3 from the phase monitoring circuit already described with reference to FIG.

First, when the power is turned on, the operation of the signal processing circuit 53 is started, and registers and the like are initialized (steps 121 and 123). Next, the presence or absence of an interrupt signal (INT) is constantly checked (step 125).
The interrupt signal in this case is the input request signal (ISYNCI)
13, and this input request signal is sent to the interrupt signal terminal 6.
6, the signal processing circuit 53 outputs the input data acquisition signal IN to the bus driver 59 and outputs the input data acquisition signal IN to the bus driver 59.
The input data (IDATA) 11 is taken from the register 57 into the signal processing device 53 (step 127). Next, the input signal is processed (arbitrary signal processing) to determine output data (step 128). Next, it is determined whether the output signal _S3 of the phase monitoring circuit 51 is "1" or "0" (step 129). here,
If S ₃ =1, the data output time position is set immediately after the input request signal 13 is input (step 131). Also, S ₃
= 0, the time position in the middle of the cycle of the input request signal 13 is set as the data output time position (step
133). Next, data is output at each time position (step 135). Steps from step 125
135 operations are performed cyclically to process input data (IDATA) 11 that is input sequentially to generate output data, and this output data is sent to input request signal (ISYNCI) 13 and output request signal (OSYNCI).
It is possible to output at a predetermined time position according to the phase difference with 29.

FIG. 4 is a block diagram showing means for implementing the procedure shown in FIG. 3.

In FIG. 4, reference numeral 141 denotes a sequence controller, which takes in an interrupt signal (INT) and an output signal _S3 from the phase monitoring circuit 51, reads out a predetermined program from the program ROM 143 according to the signal, and outputs a predetermined program from a predetermined terminal. Output. This program ROM 143 stores a program for determining the data output time position. Also, 1
Reference numeral 45 denotes a microprocessor, which performs necessary calculations based on microprogram output, processes input signals, determines output signals, and at the same time performs logical processing to determine output time to control the sequence controller. It also uses built-in registers to temporarily store data.

The signal processing method of the present invention will be explained below with reference to FIG.

It is assumed that the input request signal (ISYNCI) 13 and the input data (IDATA) to the input terminal 55 and the output request signal 29 are asynchronous. Furthermore, the data output from the signal processing circuit 53 is output request signal 2.
9 is output from the OR register 75, and
The signal processing circuit 53 receives an input request signal (ISYNCI) 1
3 is input to the interrupt signal input terminal 66, the signal processing operation is started at the same time.

Input data (IDATA) 11 is stored in the IR register 57 by the input request signal 13. at the same time,
In response to the input data acquisition signal (IN) 63 output from the signal processing circuit 53 to the bus driver 59,
Input data (IDATA) stored in the IR register 57 is taken into the signal processing circuit 53.

On the other hand, the input request signal 13 and the output request signal 29
As already explained with reference to FIG. 2, the phase difference is determined in the phase monitoring circuit 51 using two different time value monitoring times α and β, and is determined according to the magnitude relationship between the phase difference and the monitoring time. The output signal _S3 is output to the PFLG terminal 54 of the signal processing circuit 53. Furthermore, as already explained with reference to FIGS. 3 and 4, the signal processing circuit 53 determines the time position at which data is to be output for the input request signal 13 in response to the signal _S3 , and Output instruction signal terminal 73
Let it be the output signal (OUT) from. This output signal (OUT) causes the output data stored in the microprocessor 145 (see FIG. 4) of the signal processing circuit 53 to be taken into the output register buffer 71 from the data output terminal 69.

Therefore, the OR register 75 does not output an undefined value, and furthermore, the input request signal (ISYCI) 13 and the output request signal (OSYCI) 29
Even if a minute jitter occurs in the data, the processed data can be output sequentially.

5A to 5E are time charts showing signal waveforms of main parts in the circuit shown in FIGS. 1 and 2 in order to facilitate understanding of the present invention.

5A shows the differential output signal S ₁ (hereinafter abbreviated as input request signal S ₁ ) of the input request signal (ISYNCI) 11, and FIG. 5B shows the differential output signal of the output request signal (OSYNCI) 29. S ₂ (hereinafter abbreviated as output request signal S ₂ ). However, the fifth
Figures A and B show examples where the cycle of _S1 >the cycle of _S2 .

Further, FIG. 5C shows the first counter 93, the second counter 95, the third counter 97, and the fourth counter 9.
The valid timing monitoring time EPST of 9 is shown, and the part indicated by arrow a in the figure is the monitoring time for monitoring a phase difference of time α or more.

Note that the monitoring times corresponding to α, β, and a are set each time an input and output request signal appears, but in FIG. The time position is omitted from the illustration.

FIG. 5D shows the output signal _S3 of the phase monitoring circuit 51, and FIG. The signal to be taken into the register buffer 71 (see FIG. 1) is shown.

Moreover, the dotted line with an arrow shown in FIG. 5 indicates that the phase difference between the input request signal S ₁ and the output request signal S ₂ is larger than the monitoring time α, and the data acquisition condition to the output buffer is the second acquisition condition. FIG. 3 is a diagram showing the causal relationship when transitioning from the first import condition to the first import condition. That is, for example, the output request signal at time _tA
Whether or not S ₂ exhibits a phase difference greater than time α with respect to input request signal S ₁ is determined if output request signal S ₂ at time t _A has a phase difference greater than α with respect to each input request signal at time t ₁ and t ₂ . Since it is necessary to check whether there is a phase difference, this is done between t ₁ and _{t 2} in FIG. 5C. and,
In this case, the phase difference is actually larger than α, so when the output request signal arrives at time t ₂ , S ₃ becomes “1” (time t ₂ in FIG. 5D), and until now the adjacent input request signal While the data was being taken into the output buffer in the middle of (time t ₁₂ in FIG. 5E), the data import conditions change so that the data is taken in immediately after the input request signal is input (time t ₂ in FIG. 5E). Also,
In FIG. 5, the dashed line with an arrow indicates that the phase difference between the input request signal S ₁ and the output request signal S ₂ is the monitoring time β.
FIG. 7 is a diagram showing a causal relationship when the data acquisition condition to the output buffer changes from the first acquisition condition to the second acquisition condition as the data becomes smaller.
That is, from t ₂ to _{t 4} , the phase differences are all greater than β, but since the phase difference between the output request signal at time t _D and the input request signal S ₁ at time t ₄ has become smaller than β, When the output request signal arrives at time _tD , S ₃
becomes "0" (time t _D in FIG. 5D), and while data was being taken into the output buffer immediately after the input request signal (time t ₂ to E in FIG. 5),
_t4 ) in the middle of the adjacent input request signal.
Data import conditions change (time in Figure 5)
_t45 ).

In addition, data (ABC),...
..., (PQR) is processed. however,
Each data ((ABC), etc.) is stored at time t _o (n is 0, 1,
2,...) is taken into the signal processing circuit 53 (see Fig. 1) in response to the input request signal _S1 , and from time t _o to
During t _o+1, it is processed by the microprocessor 145 (see Figure 4), and is fetched into the output buffer register 71 (see Figure 1) according to the nearest OUT signal, and then the output is processed by the nearest output request. According to signal S ₂
It is shown as being output to the outside via an OR buffer 75 (see FIG. 1). In other words, for example, data (ABC) input at time t ₀ is input at time t ₀
It is processed by the microprocessor between t1 and _t1 , is taken into the output register buffer at time _t12 between time _t1 and _t2 (Fig. 5E), and is output to the outside at time _tA (Fig. 5E). Figure 5B). In addition, the remaining data (DEF), etc. are also captured into the output register buffer according to the capture conditions determined according to the phase difference between the input and output request signals (see Figure 5E), and further It is output to the outside in response to the output request signal _S2 (see FIG. 5B). However, if the data acquisition condition to the output register transitions from one acquisition condition to the other acquisition condition, and as in this example, if the period of S ₁ > the period of S ₂ , data duplication may occur. . In other words, at time _t45 in FIG. 5E, the data (MNO) taken in at time _t4 in FIG. 5A cannot be taken into the output register buffer because it cannot be processed in time; The data (JKL) before the cycle is taken in redundantly, and this is outputted to the outside at time _tE in FIG. 5B. On the other hand, if the cycle of _S1 <the cycle of _S2 , data dropout may occur for the opposite reason. However, even if this occurs, only one data is missing.

Note that the signal processing device used in the signal processing method of the present invention is not limited to the signal processing device of the above-described embodiment. The phase monitoring circuit and signal processing circuit described in the embodiments may be replaced by other circuits as long as the circuit configuration can achieve the object of the present invention.

(Effects of the Invention) As is clear from the above description, according to the signal processing method of the present invention, the phase difference between the input request signal and the output request signal is monitored at the first and second times and output. Since data can be taken into the buffer at an appropriate position, it is possible to prevent new data from being taken into the output buffer while data is being output from the output buffer by the output request signal. Therefore, data with an undefined value is not output from the signal processing device.

Note that in the signal processing method of the present invention, data may be missing or duplicated when the data acquisition condition to the output buffer changes from one to the other, but even if data is missing or duplicated, only one data There is only the omission or duplication of data, and there is no need to omit a large amount of data as in the case of the conventional method. Therefore,
Good data processing can also be performed when changing the conditions for data acquisition into the output buffer.

In addition, since hysteresis is provided in the transition of data acquisition conditions to the output buffer, data can be input and output stably and continuously even in the face of minute phase fluctuations in input and output request signals. I can do it.

Further, according to the present invention, it is possible to determine the phase difference between asynchronous input and output request signals, and to simultaneously perform data input/output processing. Therefore,
It is possible to use a device with a simpler configuration than a conventional device having an elastic memory or the like.

For this reason, data input and output according to multiple asynchronous input request signals and output request signals,
It is possible to provide a signal processing method that can be performed without causing many data omissions at once.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a signal processing device suitable for use in this invention, FIG. 2 is a circuit diagram showing a phase monitoring circuit suitable for use in this invention, and FIGS. 3 and 4 are FIG. 1 is a diagram for explaining the signal processing device shown in FIG. 1, FIGS. 5A to 5E are diagrams for explaining the present invention, and FIGS. 6 and 7 are diagrams for explaining the prior art. 11...Input data, 13...Input request signal,
29... Output request signal, 51... Phase monitoring circuit,
53...Signal processing circuit, 57...IR register,
59... Bus driver, 71... Output register buffer, 75... OR register, 81... First differentiation circuit, 83... Second differentiation circuit, 85, 87, 8
9, 91...AND circuit, 93...first counter,
95...Second counter, 97...Third counter,
99... Fourth counter, 101... Clock signal, 103, 105... Inverter, 107, 1
09...OR circuit, 111, 113...NAND circuit, 115...flip-flop circuit, 116...
... Delay circuit, 117, 118 ... Delay flip-flop, 141 ... Sequence controller, 143 ... Program ROM, 145 ... Microprocessor.

Claims (1)

[Scope of Claims] 1. A signal processing method for inputting and outputting data in response to a periodic input request signal and a periodic output request signal, both of which are asynchronous to each other, wherein the data taken into an output buffer is In a signal processing method for outputting to the outside in response to a request signal, the phase difference between an input request signal and an output request signal is monitored during a first time and a second time shorter than the first time, and data is output to an output buffer. The capture is performed under the first capture condition immediately after inputting the input request signal, and
The second input request signal is executed at a time position between adjacent input request signals.
If the phase difference is greater than the first time, the first capture condition is selected, and if the phase difference is smaller than the second time, the second capture condition is selected. A signal processing method characterized by transitioning to a condition.