KR950014084B1 - Data write device of memory - Google Patents

Abstract

The device improves the system productivity and simplifies the environment device according to the processing bit number of CPU. The device includes the external memory means which saves the data and program, the 1st signal(-DWL) which varies the signal state by system diagnosis action, the 2nd signal(-SW_RST), the 3rd signal(MODE) which varies the signal state by reset switch action, the reset signal(-RESET) which resets the system, the interrupt signal generation means which outputs the interrupt signal(INTn), and the CPU which reads the corresponding data by selection of external memory means.

Description

Data reading device in memory

1 is a block diagram of a data reading apparatus of a memory according to an embodiment of the present invention.

2 is an operation flowchart of a data reading method of a memory according to an embodiment of the present invention.

3 is a detailed flowchart of a data reading method according to an embodiment of the present invention.

4 is a detailed circuit diagram of a reset and interrupt signal generating unit according to an embodiment of the present invention.

5 is an operation timing diagram of a reset and interrupt signal generator according to an exemplary embodiment of the present invention.

The present invention relates to a data reading device for reading data stored in an external memory device and a method thereof. In particular, the present invention relates to a memory for allowing a data reading operation to proceed in accordance with the number of execution bits to an external memory device. A data reading device.

In general, the control device of a system is converted from an analog control method to a digital control method due to the development of a processor and an improvement of control theory, and the application range is also widened.

Therefore, when controlling the operation of the system by the digital method as described above, the data processing of the system is quick and easy and the data communication according to the operation state of the system through the simple communication is very convenient.

In addition to the control signals corresponding to the operation of the system, by adding other operations such as self-diagnostic operation, a multi-functional system device can be developed, so that the reliability and quality of the product can be pursued.

In addition, since the function can be easily changed or added, and the gain value can be easily changed, a linkage operation with other systems is possible.

In the digital control apparatus that is gradually expanded for the above reasons, conventionally, a microprocessor or a microcomputer reads data stored in a memory such as ROM (Read Only Memory) or RAM (Random Access Meory) and controls correspondingly. The processing bits of the memory must match the number of processing bits of the microcomputer or processor used when performing the operation.

Therefore, when using a 32-bit microprocessor, a memory device for storing data and a program for performing a set operation must also execute an input / output operation of data in 32 bits, which is the same bit as the microprocessor.

Therefore, when using a ROM that does not have the same number of input and output bits as the microprocessor, it is necessary to input and output control signals and data for controlling the operation using the same number of bits as the output bits of the microprocessor using a plurality of ROMs.

Therefore, a problem arises in that the memory device used to adjust the number of processing bits only needs to be increased regardless of the capacity of data stored in the memory.

Therefore, regardless of the data capacity, it causes a lot of manufacturing cost increase and requires a lot of transmission lines, which causes design difficulties.

Therefore, an object of the present invention is to solve the above-mentioned problems, and it is possible to reduce the manufacturing cost by transmitting the data according to the processing bit number of the memory device used regardless of the processing bit number of the control means used. To provide a data reading device and a method of the memory to be able to pursue the convenience of design and design.

An aspect of the present invention for achieving the above object is an external memory means for storing data and programs required for operation of the system in units of transmission bits; A first signal in which the state of the signal varies according to the diagnostic operation of the system, a second signal in which the state of the signal varies according to the operation state of the reset switch, and a third in which the state of the signal varies according to the state of the power supply used. A signal, a reset signal for resetting the system in response to a clock signal having a predetermined period, and a clock signal applied after the reset signal becomes inactive to read data stored in the external memory means. Reset and interrupt signal generating means for counting and outputting an interrupt signal which becomes active after a predetermined time and maintains an active state for a predetermined time; The central processing unit resets the state of the system according to the reset signal, selects the external memory means according to the state of the interrupt signal, and reads out the data.

Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention;

1 is a block diagram of a data reading apparatus of a memory according to an embodiment of the present invention, FIG. 2 is an operation flowchart of a data reading method of a memory according to an embodiment of the present invention, and FIG. 3 is a data reading according to an embodiment of the present invention. 4 is a detailed circuit diagram of a reset and interrupt signal generator according to an embodiment of the present invention, and FIG. 5 is an operation timing diagram of a reset and interrupt signal generator according to an embodiment of the present invention.

Referring to the configuration of the present invention with reference to FIG. 1, a central processing unit (CPU) 1 for reading data required by a program stored in the internal memory 11 and the central processing unit ( An external ROM (ROM) 2 connected to 1) for storing data and programs for controlling the operation of the central processing unit 1 and outputting necessary data according to the reading operation of the central processing unit 1; A reset and interrupt signal generator (3) connected to the central processing unit (1) and generating a reset signal and an interrupt signal of the central processing unit (1), the central processing unit (1) and an external ROM (2); It is connected to the peripheral device portion 4 is composed of an input signal conversion device for the operation of the central processing unit (1), an external communication device and an operation control device.

The reset and interrupt signal generator 3 is an input unit 31 to which a control signal (-DWL, -SW _- RST, MODE) and a clock signal CK are input, and is connected to the input unit 31 and is connected to the input unit 31. Counter unit 32 for counting the signal applied from the, and the output unit 32 is connected to the counter unit 32 and outputs the counted signal from the counter unit (32).

The input unit 31 includes an AND gate AND311 having a first input terminal connected to a diagnostic signal (-DWL) and a second input terminal connected to a reset request signal (-SW _- RST), and a power state monitoring signal. Inverter having an AND gate (AND312) connected to a first input terminal (MODE) and a second input terminal connected to a clock signal CK, and an input terminal connected to an output terminal of the AND gate (AND311). It consists of (INV311).

The counter 32 has first and second input terminals R01 and R02 connected to the output signal of the inverter INV311 of the input unit 31, and outputs of the AND gate AND312 of the input unit 31. A first counter 321 having a first clock terminal CLKA connected to a terminal and a second clock terminal CLKB connected to a first output terminal QA, and the output unit of the input unit 31; The first and second input terminals R01 and R02 are connected to the signal applied from 33, and the first clock terminal CLKA is connected to the output terminal of the AND gate AND312 of the input unit 31. The second counter 322 has a second clock terminal CLKB connected to the output terminal QA.

The output unit 33 includes an AND gate AND331 connected to an input terminal of a fourth output terminal QD of the first counter 321 of the counter unit 32, and an output of the counter unit 32. An AND gate AND332 having an input terminal connected to the fourth output terminal QD of the second counter 322, and a clock terminal CLK connected to the output terminal of the AND gate AND331 are connected to the input terminal 31. The output terminal of the AND gate AND332 and the D flip-flop DF331 having the clear terminal CLR connected to the output terminal of the AND gate AND311 and the input terminal D connected to the power supply Vcc. D flip-flop DF332 connected to (CLK), the clear terminal (CLR) is connected to the output terminal of the AND gate (AND311) of the input unit 31, the input terminal (D) is connected to the power supply (Vcc) ), An inverter INV331 having an input terminal connected to the output terminal Q of the D flip flop DF331, and an input terminal to the output terminal Q of the D flip flop DF331. The inverter INV332 connected to the first and second input terminals R01 and R02 of the second counter 321 of the counter unit 32 and the output terminal of the inverter INV331. It consists of an OR gate OR331 having one input terminal connected and a second input terminal connected to the output terminal Q of the D flip flop DF332.

The operation of the present invention made as described above is as follows.

According to a program embedded in the internal RAM of the 32-bit central processing unit 1, the central processing unit 1 operates the data inputted from an external device or the central processing unit 1; Read data to control.

Therefore, the operation of reading data necessary for the operation according to the algorithm stored in the internal memory device of the central processing unit 1 will be described.

First, when the operation is started (20), to initialize the state of the system to perform the correct operation (20). When the initialization operation is completed, the central processing unit 2 determines the value of the control signal MC / -MP applied from the outside (30), and sets the usage mode of the central processing unit (1).

The central processing unit 1 used in the embodiment of the present invention operates as a microcomputer when the value of the control signal MC / -MP is "H" at a high level, and the control signal MC / -MP. If the value of "L" is a low level, the microprocessor can operate.

Therefore, by adjusting the value of the control signal (MC /-MP) it is possible to adjust the use of the central processing unit according to the user's purpose of use.

Therefore, when the value of the control terminal MC / -MP is " H ", the CPU 1 operates as a microcomputer, and when the value of the control terminal MCBL / -MP is " L " The processing device 1 is in a state capable of being operated by a microprocessor.

Therefore, when the value of the control terminal MC / -MP is " H ", the CPU 1 can operate according to data and programs stored in the external ROM 2, and control terminal MC / -MP. If the value of -MP) is " L ", it can be operated by the microprocessor (80).

Therefore, when the central processing unit 1 is operated by a microcomputer, the central processing unit 1 is selected from among the interrupt signals (-INT0 to -INT2) output from the reset and interrupt signal generating unit 3. It is determined whether the value of INT1) is "0" (40).

The central processing unit 1 reads the data stored in the external ROM 2 according to the state of the interrupt signals (-INT0 to -INT2) output from the reset and interrupt signal generator 3, or externally. It is determined whether to read data input from an external device through a communication device connected to the device.

Therefore, the central processing unit 1 when the interrupt signal (-INT0, -INT1) is low level "L" among the interrupt signals (-INT0 to -INT2) output from the reset and interrupt signal generating section (3). Reads the data stored in the external ROM (2).

An operation state of the reset and interrupt signal generator 3 will be described with reference to FIG.

First, the diagnostic signal (-DWL) whose signal value is variable according to the self-diagnosis operation result in a method not shown is "H", which is a high level when the operation state of the system is normal, but the system is normally operated by the self-diagnosis operation. If it is determined that a malfunction is performed without operating, the diagnostic signal -DWL is changed to "L" which is a low level.

The reset request signal -SW_RST becomes low level "L" when the reset switch mounted in the system is operated, and normally high level "H".

The power state monitoring signal MODE becomes a high level "H" when the state of the power source used as the power state monitoring signal is a normal state, and a low level "L" when the state of the power source is abnormal.

Therefore, the diagnostic signal (-DWL) and the power state monitoring signal MODE, which are normal when the system is in a normal state, become high level "H" as shown in a and b of FIG. 5, and the reset signal is inactive when the reset signal is active as shown in c of FIG. Operation when the reset request signal (-SW 신호 RST) is switched from the low level " L " state to the high level " H " state and the clock signal CK is applied as d of FIG. Is as follows.

First, as shown in FIG. 5C, when the reset request signal SW_RST is in the low level "L" state, the low level "L" is set to the reset terminal (-RESET) which is the output terminal of the AND gate AND311 of the input unit 31. Output

Therefore, due to the above reset signal (-RESET) to initialize the system state for the normal operation of the system.

At this time, the counter 32 is supplied with the high level "H" to the reset input terminals R01 and R02 of the first counter 321, and the low level "L" signal is output to the output terminals QA and QD. In response to the operation of the first counter 321, the state of the output terminals QA and QD of the second counter becomes a low level "L" state.

Therefore, the signal of the interrupt INTn maintains the high level "H" state.

However, when the state of the reset request signal SW_RST is changed to the high level "H" state, it is applied to the input terminal of the inverter INV311 of the input unit 31 to reset the input of the first counter CT321 of the counter unit 32. When the low level "L" signal is applied to the terminals R01 and R02, the first counter CT321 counts the input clock signal CK.

Therefore, the output signal of the AND gate AND331 of the output unit 33 connected to the fourth output terminal QD of the first counter CT321 by the operation of the first counter CT321 is shown in FIG. Signal is output.

Accordingly, the first D flip-flop DF331 is operated by the output signal of the AND gate AND331, and the signal as shown in FIG. 5 is output to the output terminal Q and is applied to the input terminals of the inverters INV331 and INV332. .

Therefore, when the output signal of the inverter INV332 is the same as g of FIG. 5 and the low level " L " is applied to the reset input terminals R01 and R02 of the second counter CT322 of the counter unit 32, The second counter CT322 starts operation.

Accordingly, a signal such as h of FIG. 5 is output to the output terminal of the AND gate AND332 according to the signal output from the fourth output terminal QD by the operation of the second counter CT332, so that the second D flip flop DF332 It is applied to the clock terminal CK to output a signal as shown in FIG.

Therefore, the inverted signal of the 1D flip flop DF331 and the output signal of the 2D flip flop DF332 are applied to the input terminal of the OR gate OR331 so that the signal applied to the interrupt terminal INRn is as shown in FIG. 5. After the reset request signal (-SW＿RST) becomes inactive, the reset signal (-RESET) becomes inactive and is delayed for a predetermined time (t1) to maintain a low level that is active for a predetermined time (t2). do.

At this time, the reset request signal (-SW＿RST) is switched to the high level "H" state, and then the predetermined time (t1) is delayed, and then the interrupt signal (INTn) is switched to the active "L" state. same.

In order for the system's operation to proceed normally, the system's initialization must be normally performed before the operation.

Therefore, when the reset signal (-RESET) is active, all input signals are ignored and only the reset operation of the system is executed.

Therefore, when the interrupt signal INTn is activated to read the corresponding data immediately after the reset operation of the system is completed, the reset signal (-RESET) and the interrupt signal (INTn) match each other, and the data read result of the interrupt signal is displayed. Something wrong happens.

Therefore, in order to determine the state of the correct interrupt signal INTn, the reset operation of the system is completely completed by the reset signal (-RESET), and the predetermined time (t1) does not match the reset signal (-RESET) and the interrupt signal (INTn). Delay to make the interrupt signal INTn active.

That is, after several cycles of the operation for determining the interrupt status, the interrupt signal INTn is activated to prevent problems due to matching with the reset signal (-RESET).

The reason for maintaining the active state of the interrupt signal INTn for a predetermined time t2 is to accurately determine the active state of the interrupt signal INTn.

This is because when the interrupt signal INTn is activated for a very short time, the CPU 1 cannot determine the correct active state due to the noise generated by the operation of the system.

Therefore, the active state is maintained for a predetermined time t2 to sufficiently recognize the active state of the interrupt signal INTn, thereby solving the problem of not recognizing the interrupt signal INTn due to the influence of noise.

The interrupt signals used to determine whether to read data stored in the external ROM 2 or data applied from an external input device are all three signals (-INT0 to -INT2). I use it.

Therefore, select the interrupt terminal (-INT0 ~ -INT2) among the interrupt signals (INT0 ~ INT2) according to the device to read the data and select the interrupt terminal (-INT0 ~ -INT2) to output the above-mentioned signal. Only output

Therefore, in order to read the data stored in the external ROM 2, the CPU 1 selects the interrupt terminal (-INT0 to INT1) and selects one of the selected interrupt terminals (-INT0 to -INT1). A low level "L" signal can be applied to the.

Therefore, when any one of the interrupt signals (-INT0 to -INT1) maintains the low level "L" value by the operation of the reset and interrupt signal generator 3 as described above, the central processing unit 1 Executes a ROM data read operation for inputting data stored in the external ROM 2 (60).

However, when the interrupt signals -INT0 to -INT1 are not low level "L", the CPU 1 determines whether the value of the interrupt signal -INT2 is "L" low level (50).

Therefore, when the interrupt signal (-INT2) is " L " at low level, the central processing unit 1 is operated in accordance with data applied from an externally mounted communication device (70).

However, when the interrupt signal (-INT2) is also not at the low level "L", the CPU 1 continues to judge the state of the interrupt signals (-INT0 to -INT2).

A method of receiving data stored in the external ROM 2 when any one of the interrupt signals -INT0 and -INT1 is "L" at a low level will be described.

When reading the data of the external ROM 2 by the interrupt signals (-INT0, -INT1) as described above, the CPU 1 first determines the address number where the data is stored in the external ROM 2. In order to determine the boot number set in order to determine the data storage start address of the external ROM 2 (62).

In the embodiment of the present invention, when the boot number is "0", it is determined that the corresponding data is stored from the "1000" address of the external ROM, and when the boot number is "1", the "400000" address of the external ROM. If the data is stored from, and if the boot number is "2", it is determined that the data is stored from the "FF000" address of the external ROM.

Therefore, the central processing unit 1 determines the value of the set boot and sequentially reads from the start address where the data is stored in the external ROM 2 to read the stored data.

When the boot number is determined as described above, the CPU 1 determines the data transmission bit by reading the data stored in the first area from the start address (63).

The present invention is to enable 32-bit data processing by using one 8-bit ROM, and the data transmission bit in the embodiment of the present invention is set to 8 bits.

The data stored in the second region is read to determine the data processing speed of the external ROM 2 (64).

The reason for determining the data processing speed of the external ROM 2 as described above is a problem of incorrectly determining the transmission information by incorrectly determining the transmission data due to the difference in the data processing speed between the central processing unit 1 and the external ROM 2. To solve the problem.

Therefore, the data processing speed of the external ROM 2 is determined so that all data transmitted from the external ROM 2 can be read and processed according to the data processing speed of the central processing unit 1.

Then, the data stored in the third area is read to determine the size of the data stored in the external ROM 2 to determine the size of the block in which the actual data necessary for the operation of the CPU 1 is stored (65). ).

Therefore, when the central processing unit 1 reads the data stored in the external ROM 2, all the stored data can be read.

The CPU 1 determines whether the size of the block in which the actual data is stored is "0" (66) and checks whether the actual data necessary for the operation is stored in the external ROM 2.

Therefore, when the size of the block in which the actual data is stored is not "0", the central processing unit 1 reads the data stored in the fourth area and internal RAM 11 built in the central processing unit 1. By determining the start address of the address (67), it is possible to store the data read from the determined start address.

In the embodiment of the present invention, the start address of the internal RAM 11 is "809800H", but the start address of the program is set to "809810H" in consideration of the part of the internal RAM 11 used when reading data.

After reading the data necessary for the read operation stored in the external ROM 2 as described above, the central processing unit 2 reads the data or program required for the actual operation.

Therefore, the central processing unit 1 again determines whether the size of the actual data stored in the external ROM 2 is not "0" (68), and stores the actual data necessary for operation in the external ROM 2. Determine if it is.

Therefore, if the actual data size is '0', the central processing unit judges that the data necessary for the actual operation of the central processing unit 1 is not stored in the external ROM 2 or that all stored data have been read. Go to the first start address of the internal RAM 11 of the device 1 (612), process the signal so that the data stored in the internal RAM 11 can be processed into 32 bits, and then execute the corresponding operation (100). .

However, when the size of data is not "0", the central processing unit 1 sequentially moves address addresses to read data stored in the external ROM 2 (69). In operation 610, the size of the initially set data is sequentially decreased by "1".

The above data read operation is continued until the size of the actual data is reduced to " 0 " to read all the data stored in the external ROM 2.

Therefore, when the data size is " 0 " by reading the data stored in the external ROM 2 as described above, the central processing unit 1 reads the data stored in the third area of the external ROM 2 and actually The size of the data is determined (611).

Therefore, if the actual data size is not "0", it is determined that other data is continuously stored in addition to the data read through the above process, and the stored data is read through the above-described operation process.

However, when the size of data is "0", the CPU 1 determines that there is no data stored in the external ROM 2 and the first start address of the internal RAM 11 of the CPU 1 no longer exists. In operation 612, the program is executed after processing the data stored in the internal RAM 11 according to the number of processing bits of the central processing unit 1 according to the data read operation as described above.

Therefore, the central processing unit 1 can read and process data stored in the external ROM as described above according to the processing bit or processing speed of the external ROM.

As described in the above embodiment, when the data read from the external ROM 2 is stored in the internal RAM 11, the data read from the address having a predetermined address larger than the start address of the internal RAM 11 set is set. You can prevent errors that occur when you execute an action.

Therefore, the effects of the present invention operating as described above do not need to transfer the data stored in the external memory according to the number of processing bits of the central processing unit. There is no need to install the device, which can save a lot of cost.

In addition, since the number of bits of the data bus for transmitting data can be set according to the number of bits of the external memory used, the peripheral device becomes very simple and the system design becomes very easy, thereby increasing the reliability of the system.

Claims (4)

External memory means for storing data and programs required for operation of the system in units of transmission bits; The first signal (-DWL) whose state is changed according to the diagnostic operation of the system, the second signal (-SW_RST) whose state is changed according to the operation state of the reset switch, and the state of the power supply used. A third signal MODE in which the state of the signal is variable, a reset signal (-RESET) for resetting the system in response to the clock signal CK having a predetermined period, and data stored in the external memory means. An interrupt for counting the clock signal CK applied after the reset signal (-RESET) becomes inactive for reading and becoming active after a predetermined time (t1), and maintaining an active state for a predetermined time (t2). Reset and interrupt signal generating means for outputting a signal INTn; And a central processing unit for resetting the state of the system according to the reset signal (-RESET), selecting the external memory means according to the state of the interrupt signal (INTn), and reading out the corresponding data. Reader. 2. The apparatus of claim 1, wherein the reset and interrupt signal generating means comprises: AND multiplication means (AND311) for outputting a reset signal (-RESET) by ANDing the input first and second signals (-DWL, -SW_RST); Inverting means (INV311) for inverting a signal of the AND product AND311; The output signal of the inverting means INV311 is input to the reset input terminals R01 and R02, and the signal obtained by logically multiplying the third signal MODE and the clock signal CK is input to the first clock terminal CLKA. First counter means CT321; A first D flip flop DF331 to which an output signal QD of the first counter means CT321 is input to a clock terminal CLK and a power supply Vcc is connected to the input terminal D; Inverting means (INV331, INV332) for inverting the output signal Q of the first D flip flop DF331; A second counter CT322 having reset input terminals R01 and R02 connected to an output terminal of the inverting means INV332 and a first clock terminal CLKA connected to a clock terminal CK; A second D flip flop DF332 having a clock terminal CK connected to the output terminal QD of the second counter CT322 and a power supply Vcc connected to the input terminal D; And a logic OR means OR331 for outputting an interrupt signal INTn, which is connected to an output terminal of the inverting means INV331 and an output terminal Q of the second D flip-flop DF332 and outputs an applied signal. A data reading device of a memory. 3. The interrupt signal of claim 2, wherein the interrupt signal becomes active in synchronization with the output of the first flip flop DF331, and becomes inactive in synchronization with the output of the second flip flop DF332. Data reading device in memory. The data reading apparatus of claim 1, wherein the data processing unit of the central processing unit is an integer multiple of the transmission bit unit of the external memory means.