JPS62216454A - Signal processing method - Google Patents

Abstract

PURPOSE:To input and output data corresponding to plural asynchronous data processing request signals without causing many data omission at a time by determining input and output time position corresponding to phase difference of data processing request signals. CONSTITUTION:It is supposed that an input request signal 13 and input data 11 to an input terminal 55 and an output request signal 29 are asynchronous. The phase difference between the input request signal 13 and output request signal 29 is discriminated by a phase supervisory circuit 51 using two different time value supervisory times alpha and beta an output signal S3 corresponding to magnitude relation between the phase difference and supervisory time is outputted to the PFLG terminal 54 of a signal processing circuit 53. Further, the signal processing circuit 53 determines time position at which data are outputted to the input request signal responding to the signal S, and this time position is made an output signal (OUTO) from an output designation signal terminal 73. By such an output signal (OUTO), output data stored in a microprocessor of the signal processing circuit 53 are taken in an output register buffer from a data output terminal 69.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention is applicable to a high-efficiency encoding device used to efficiently transmit call information for international telephone calls. Regarding a signal processing method for inputting and outputting data according to a signal, in particular, a phase monitoring circuit monitors the phase difference between input and output request signals, and the time position of data input and output is determined according to the output of this monitoring circuit. The present invention relates to a signal processing method for determining a signal processing method.

(Prior Art) FIG. 6 is a block diagram showing an example of a conventional asynchronous signal processing device.

In FIG. 6, 11 indicates human data IDATAO, and 13 indicates input request signal 15YNCI. 15 and 1
7 indicates the first and second DELAY, respectively; 19 and 21 indicate the second and second selectors, respectively. Also, 2
3 indicates an elastake memory (ESM), and 25 indicates a phase monitoring circuit (PHC). Also, 27 is output data 0D
29 indicates an output request signal 05YNCI.

In this device, input data 1 is input in response to an input request signal 13.
1 is written to the elastake memory 23, and data 11 is read in response to the output request signal 29. However, if the input request signal 13 and the output request signal 29 conflict, the write to the elastake memory 23 and the data 11 are read out according to the output request signal 29. , and the reading from the memory 23 may overlap, resulting in an undefined value being output. In order to prevent this, a phase monitoring circuit 25 as shown in detail in FIG. 7 has been used to control writing to the erasure memory.

In FIG. 7, 31 indicates a first differential circuit to which the output request signal 29 is input, and 33 indicates a second differential circuit to which the human power request signal 13 is input. Further, 35 and 37 indicate the first and second counters, respectively, and the second and second counters 3
A predetermined single monitoring time α is connected to each of the inputs of the counters 5 and 37, and the reading instruction terminal of the first counter 35 is connected to the output terminal of the second differentiating circuit 33.
The read instruction terminal τ of the second counter 37 is connected to the output terminal of the first differentiation circuit 31. Further, 39 and 41 each indicate an inverter, and 43 and 45 each indicate an A
An ND circuit is shown, and 47 is an OR circuit. Further, 49 indicates a clock signal, which is connected to the first and second counters 35 and 37, respectively.

In such a circuit, for example, data corresponding to a single monitoring time α is read from the input of the first counter 35 in accordance with the output signal of the second differentiating circuit 33, and the time α is counted. During this time, an output signal is output to the output terminal surface. Furthermore, by using the inverter 39 and the AND circuit 43 to logically AND the signal at the output terminal C of the first counter 35 and the output of the first differentiating circuit 31, the human power request signal 13 is raised. The time difference between the time and the time when the output request signal 29 rises can be compared with the monitoring time α. Similarly, the second counter 37 can be used to compare the time difference from the time when the output request signal 29 rises to the time when the input request signal 11 rises and the monitoring time α. Further, the OR circuit 47 calculates the logical sum of the output signals of the AND circuits 43 and 45, and the phase flag 4 is
9, and this phase flag 49 controls the writing of input data 11 to the elastake memory 23.

Further, since it has the elasticity memory 23, data can be written and read sequentially regardless of minute jitters between the input request signal 11 and the output request signal 29.

(Problem to be solved by the invention) However, in the conventional method, when the phase difference between the input request signal and the output request signal exceeds the memory limit of the elastake memory (slip), the elastake memory is reset. In this case, a large amount of data is lost, which is equal to the capacity of the elastake memory. Therefore, for example, the data transmitted at the time of a slip may be unreadable, and even if an attempt is made to correct an error by taking the missing data into account, there is a problem in that a large amount of data is missing and cannot be corrected. .

Furthermore, in the conventional method, elastic take memory, DEL
There is a problem in that a complicated circuit consisting of AY 1, DELAY 2 and a selector is required to absorb the phase shift of the asynchronous input and output request signals.

An object of the present invention is to solve the above-mentioned problems and to provide a signal processing method capable of inputting and outputting data in response to a plurality of asynchronous data processing request signals without causing many data omissions at once. Our goal is to provide the following.

(Means for Solving the Problems) In order to achieve this object, the present invention provides a signal processing method for inputting and outputting data in response to a plurality of asynchronous data processing request signals. The present invention is characterized in that the phase difference of the request signal is determined at two or more different times, the above-described time positions of data input and output are determined based on the result of this determination, and the data is output at these time positions.

(Operation) According to the signal processing method of the present invention, the data input/output time position is determined according to the phase difference of the data processing request signal.

Therefore, for example, in the case where multiple data processing request signals are an input request signal and an output request signal, the output time position of data when these request signals conflict is, for example, the time position in the middle of the period of the manual request signal. It can be done. Therefore, even if the input and output request signals conflict, data with an undefined value will not be output from the signal processing device.

(Embodiments) Hereinafter, embodiments of the present invention will be described with reference to the drawings. It should be noted that the Kowara diagram is only a schematic representation to the extent that the present invention can be understood, and means for realizing the present invention are not limited to the illustrated example. Further, in these figures, the same components are designated by the same reference numerals. In addition, the same components as in the prior art are denoted by the same reference numerals.

FIG. 1 is a block diagram showing an embodiment of a signal processing device suitable for use in the signal processing method of the present invention.

In FIG. 1, 51 is a phase monitoring circuit (PSC) for determining the phase difference of data request signals at two or more different times.
53 indicates a signal processing circuit (spp) that determines the input/output time position based on the determination result. Phase monitoring circuit 51
The output S3 is connected to the PFLG terminal 54 of the signal processing circuit 53.

Input data (IDATA) 11 input terminal 55 is I
It is connected to the R register 57, and this IR register 57
is connected to the signal processing circuit (SPP) 5 via the bus driver 59.
It is connected to the input terminal (INDATA) 61 of No. 3.

The bus driver 59 outputs the contents of the IR register 57 to an input terminal (INDATA) 61 in response to an input data acquisition signal (INiT) a3 from the signal processing device 53. Human power request signal (l5YNCI) +3 input terminal 65 is I
It is connected to the R register 57, the phase monitoring circuit 51, and the interrupt signal terminal (INT) 66 of the signal processing circuit 53.

In addition, the output data terminal (0υTDAT) of the signal processing circuit 53
A) 69 is connected to an output register buffer (ORB) 71, and this output register buffer 71 reads output data from the signal processing circuit 53 in response to an instruction signal (OUTδ) from an output instruction signal terminal 73. The output register buffer 71 is connected to the OR register 75, and furthermore,
This OR register 75 is connected to an output terminal 77.

Also, input terminal 7 of output request signal (05YNCI) 29
9 is connected to the phase monitoring circuit 51 and the OR register 75.

FIG. 2 is a circuit diagram showing details of the phase monitoring circuit 51 shown in FIG. 1. Hereinafter, with reference to FIG. 2, the phase monitoring circuit 5
Let me explain about 1.

The input terminal 79 for the output request signal shown in FIG. 1 is connected to the first differentiating circuit (DI), and the input terminal 65 for the human power request signal is connected to the second differentiating circuit (D2) 83. The output terminal of the first differentiating circuit 81 is connected to the AND circuit 85 and
They are connected to the circuit 89 and the read instruction signal input terminals of the second counter 95 and the fourth counter 99, respectively. The output terminal of the second differentiating circuit 83 is an AND circuit 87,
an AND circuit 91, a read instruction signal input terminal (r,) of each of the first counter 93 and the third counter 97;
These are connected to the delay circuit 116, respectively. Also, first,
Second, third and fourth counters 93.95.97 and 99
A clock signal (to CL) +01 is connected to each.

The CO output terminal of the first counter 93 is connected to the AND circuit 85, A
It is connected to the ND circuit 87 and the 100 (enable) terminal of the first counter, and the - output of the second counter 95 is connected to the AND circuit 85, the AND circuit 87, and the positive terminal of the second counter. The CO output terminal of the third counter 97 is connected to the inverter 103 and the E terminal of the third counter 97, and the CO output terminal of the fourth counter 99 is connected to the inverter 103.
5 and the E terminal of the fourth counter 99. or,
The output terminal of inverter 103 is connected to AND circuit 89, and the output terminal of inverter 105 is connected to AND circuit 91. Furthermore, AND circuit 85 and AND circuit 8
The output terminal of 7 is connected to the OR circuit 107, and the output terminal of A
The output terminals of the ND circuit 89 and the AND circuit 91 are connected to the OR circuit 109.

The output terminal of the OR circuit 107 is the CK positive terminal of each of the delay flip-flop circuits 117 and 118, and the O
The output terminals of the R circuits 109 are connected to the inverters 113, the outputs of the delay circuits 116 are connected to the R@ terminals of the delay flip-flop circuits 117 and 118, and the delay flip-flop circuits 11
The output Q of 7 is the D of the delay flip-flop circuit 118.
has been entered. Further, the output Q of the delay flip-flop circuit +18 is connected to the inverter Ill, and the output terminal of this inverter 111 is connected to the flip-flop (F
F) Connected to input terminal S of 115. Further, the output terminal of the inverter 113 is connected to the input terminal R of the FF 115. Note that the output terminal Q of this FFll5 is connected to the PFLG terminal 54 of the signal processing device 53 shown in FIG. 1, and outputs an output signal S3.

In addition, data corresponding to a predetermined monitoring time α is connected to the input terminals of the first and second counters 93.95, and data corresponding to α is connected to the input terminals of the third and fourth counters 97.99. Data corresponding to a predetermined monitoring time β is connected to different values, and each monitoring time corresponding data is configured to be read in accordance with a signal input to a read instruction input terminal of each counter.

In such a phase monitoring circuit 51, the first counter 93 counts the monitoring time α and the third counter 97 counts the monitoring time β in response to the pre-differentiated output signal S1 of the input request signal 13. ■ Connect “ to the output terminal of
"0" is output, and "1" is output except when counting is in progress. Similarly, in response to the pre-differentiated output signal S2 of the output request signal 29, the second counter 95 changes the monitoring time α to the fourth counter 9.
9 counts the monitoring time β, and outputs "0" to each gate output terminal during counting, and outputs "1" at times other than counting.

Further, the AND circuit 85 monitors whether the signal S2 arrives at a time other than when the first counter 93 and the second counter 95 are counting. Similarly, the AND circuit 87 outputs the signal S when the first counter 93 and the second counter 95 are not counting.
Watch for the arrival of I.

Therefore, if the time difference between the rising time of the input request signal 13 and the rising time of the output request signal request 29 (hereinafter also simply referred to as a time difference) is larger than the monitoring time α time, l5YN(:I The output of the OR circuit 107 becomes "1" twice until l5YNC1 of the rising composition. Therefore, the delay flip-flop circuits 117 and 118
The output becomes "1" sequentially. On the other hand, the time difference is the monitoring time β
If it is smaller, the output of the OR circuit 109 becomes "1". Therefore, FF 115 is PF if time difference>α
“1” is output as the output signal S3 to the LG terminal 54, and “0” is output as the output signal S3 to the PFLc=i child 54 in the case of time difference β.

Furthermore, if the monitoring time setting conditions are α>β, the period of α<Sl, and the period of α<Sl, then the delay flip-flop circuit 118 and the OR circuit 1
Output signals from 09 and 09 are not output at the same time. Therefore, FF115 is a delay flip-flop circuit +
After operating according to the output of OR circuit 109, the output signal from OR circuit +09 is monitored.
After operating based on the output of the delay flip-flop circuit 118, the output signal of the delay flip-flop circuit 118 is monitored. Therefore, since the monitoring time can have hysteresis, a stable output S3 can be obtained even if minute jitter occurs in the signals S and Sl.

Next, the signal processing circuit 53 for determining the data input/output time position based on the phase difference determination result will be described with reference to FIGS. 1 and 3.

FIG. 3 is a flowchart for determining the output time position of data based on the signal S3 from the phase monitoring circuit already explained with reference to FIG.

First, when the power is turned on, the operation of the signal processing circuit 53 is started, and initial settings of registers, etc. are performed (step 1).
21, 123). Next, the presence or absence of an interrupt signal (INT) is constantly checked (step 125). The interrupt signal in this case is an input request signal (ISYN(:I) 13, and when this manual request signal is input to the interrupt signal terminal 66, the signal processing circuit 53 transfers the input data acquisition signal INO to the bus driver. 59 and input data (IDA) from the IR register 57.
Step 12 of importing TA) 11 into the signal processing device 53
7). Then process the input signal (arbitrary signal processing)
is performed to determine output data (step 128). Next, it is determined whether the output signal S3 of the phase monitoring circuit 51 is "1" or "0" (step 129). Here, if 53=1, the data output time position is set immediately after input of the input request signal 13 (step +31). If 53=0, the time position in the middle of the period of the input request signal 13 is set as the data output time position (step 133). Next, data is output at each open position (step 135). The operations from step 125 to step 135 are performed cyclically to generate output data by embedding the manually input data (IDATA) II into IA, and this output data is used as input request signal (l5YNCI) 13 and output request signal ( OS
It is possible to output at a predetermined time position according to the phase difference with YNCI) 29.

FIG. 4 is a block diagram showing means for implementing the procedure shown in FIG. 3.

In FIG. 4, +41 indicates a sequence controller, which takes in the interrupt signal (INT) and the output signal S3 from the phase monitoring circuit 51, reads out a predetermined program from the program ROM 143 according to the signal, and outputs it from a predetermined terminal. let This program ROM 143 stores programs for determining the data output time position. A microprocessor 145 performs necessary calculations based on the microprogram output, processes input signals, determines output signals, and at the same time performs logical processing to determine output time to control the sequence controller. It also uses built-in registers to temporarily store data.

The signal processing method of the present invention will be explained below with reference to FIG.

In addition, the input request signal (l5YNCI) 13, the manual data (IDATA) to the input terminal 55, and the output request signal 2
9 is asynchronous. Further, the data output from the signal processing circuit 53 is output from the OR register 75 in response to the output request signal 29, and the signal processing circuit 53 receives the input request signal (l5YNCI) 13 from the interrupt signal input terminal 66.
The signal processing operation starts at the same time as the signal is input.

Input data (IDATA) 11 is stored in the IR register 57 in response to the input request signal 13. At the same time, in response to the input data acquisition signal (rNo) a3 output from the signal processing circuit 53 to the bus driver 59, the input data (IDATA) stored in the IR register 57 is transferred to the signal processing circuit 59.
Incorporate into 3.

On the other hand, the phase difference between the input request signal 13 and the output request signal 29 is determined in the phase monitoring circuit 51 using two different time value monitoring times α and β, as already explained with reference to FIG. The output signal S3 corresponding to the magnitude relationship between the phase difference and the monitoring time is sent to the PFLG terminal 54 of the signal processing circuit 53.
Output to. Roughly speaking, as already explained with reference to FIGS. 3 and 4, the signal processing circuit 53 determines the time position at which data for the input request signal 13 is output in response to the signal S3, and Output signal from output instruction signal terminal 73 (OUTo) Tot6゜Cono output signal (OUT
vJ) Output data stored in the microprocessor 145 (see FIG. 4) of the signal processing circuit 53 is taken into the output register buffer 71 from the data output terminal 69.

Therefore, an undefined value is not loaded into the OR register 75, and furthermore, even if slight jitter occurs in the human input request signal (l5YCI) 13 and the output request signal (O5YCI) 29, the processed data can be sequentially output. I can do it.

5(A) to 5(E) are time charts showing signal waveforms of main parts in the circuit shown in FIGS. 1 and 2 for better understanding of the present invention.

FIG. 5(A) shows the manual request signal (ISYNCI month 1 differential output signal S1), and FIG. 5(B) shows the output request signal (O
SYNCI) 29 differential output signal S2 is shown.

Further, FIG. 5(C) shows the load movement timing monitoring time EPST of the first counter 93, second counter 95, third counter 97, and fourth counter 99, and the part indicated by the arrow (a) in the figure is This is the monitoring time for monitoring the phase difference over time α.

Note that the monitoring times corresponding to α, β, and (a) are set each time an input and output request signal appears, but as shown in FIG. 5(C)
The arrows indicating each monitoring time shown in are just an example, and the arrows shown at each time position are omitted.

5(D) shows the output signal S3 of the phase monitoring circuit 5I, and FIG. 3(E) shows the output instruction signal o+rro from the signal processing device 53.

Incidentally, the signal processing device used in the signal processing method of the present invention is as follows:
The present invention is not limited to the signal processing device of the embodiment described above. The phase monitoring circuit and signal processing circuit described in the embodiments may be replaced by other circuits as long as the circuit configuration can achieve the object of the present invention.

Further, in the above-described embodiment, the monitoring time was explained as two times α and β, but it is also possible to set the monitoring time to three or more to closely monitor the phase difference between the input and output request signals.

(Effects of the Invention) As is clear from the above description, according to the signal processing method of the present invention, the data input/output time position is determined according to the phase difference of the data processing request signal.

Therefore, for example, when a plurality of data processing request signals are an input request signal and an output request signal, the data output time position when these request signals conflict can be set to, for example, a time position in the middle of the period of the input request signal. For example, even if human input and output request signals conflict, the asynchronous signal processing device will not output data with an undefined value.

Furthermore, in the signal processing method of this invention, data may be omitted or duplicated when the monitoring time is changed, but even if data omitted or duplication occurs, only one data is omitted or duplicated. However, unlike in the past, large amounts of data will not be lost. Therefore, good data processing can be performed even when switching the monitoring time.

In addition, since the monitoring time has hysteresis, it is stable even against minute phase fluctuations of input and output request signals.
In addition, data can be input and output continuously.

Further, according to the present invention, it is possible to determine the phase difference between asynchronous input and output request signals, and to simultaneously perform data input/output processing. Therefore, it is possible to use a device with a simpler configuration than a conventional device having an elastic memory or the like.

Therefore, it is possible to provide a signal processing method that can input and output data in response to a plurality of asynchronous data processing request signals without causing many data omissions at once.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a signal processing device suitable for use in this invention, FIG. 2 is a circuit diagram showing a phase monitoring circuit suitable for use in this invention, and FIGS. 3 and 4 are Diagrams for explaining the signal processing device shown in FIG. 1, FIGS. 5A to 5E are diagrams for explaining the present invention, and FIGS. 6 and 7 are diagrams for explaining the prior art. be. 11--Input data, 13--Input request signal 2
9--Output request signal, 51--Phase monitoring circuit 53
...Signal processing circuit, 57-IR register 59...
・Bus driver, 71--Output register buffer 7
5.-OR register, 81...first differentiation circuit 83-
・・Second differentiation circuit 85.87, 89.91・−A N D circuit 93−・・
First counter, 95--Second counter 97--Third counter, 99--Fourth counter 101--Clock signal, 103,105--Inverter 107.
109-OR circuit, 111.113-N A N D circuit 115...Flip-flop circuit 116-...Delay circuit 117.118-...Delay flip-flop +41
---Sequence controller 143--Program ROM 145--Microprocessor. Patent applicant Oki Electric Industries Co., Ltd. 3 counters
/II, H3: Inbar 793: Second Chohata Road
9q: Fourth counter 115: Full nozzle 0zbu straight β&g5. g7.8q,'? /: ANDEJ
'! & 101: 7a-tri (15'l
116: Slow i circuit Diagram 2 Cheetah

Claims (1)

[Claims] (1) In a signal processing method for inputting and outputting data in response to a plurality of asynchronous data processing request signals, the phase difference of the data processing request signals is determined at two or more different times, and based on the determination result, A signal processing method, comprising: determining the time positions of input and output of the data, and outputting the data at the time positions.