JP2713222B2 - Memory monitoring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device for monitoring the normality of an elastic memory for changing clocks.

[0002]

2. Description of the Related Art Generally, since the clock of an input digital signal has various variations, in order to perform control by a stable clock signal, the clock of the input signal is changed to the clock in the apparatus. There is. In this case, for example, an elastic memory using a FIFO is used. FIG. 2 shows a conventional example. In the elastic memory 1, the write data 10 is supplied to a write data terminal together with a pre-replacement clock 50, and the pre-replacement clock 50 is supplied to the write terminal. , Write data 10 is written to elastic memory 1. Also, the parity rule instruction signal 3
For example, an instruction to alternately switch between even parity and odd parity is provided to the parity operation circuit 2 for each cycle of the frame after the transfer, and the parity operation is performed on the write data. Written to 1.

Of the written information, read data 20
Is read by the clock 60 after the transfer, and the parity calculation result written is also read by the transfer clock, and the parity detection circuit 3 performs parity detection based on the read data 20 and the parity calculation result, and the parity detection result 40 Is output. In this manner, the clock transfer and the accompanying parity check are performed. The reason why the parity law instruction signal is appropriately switched is to prevent erroneous determination when the elastic memory 1 is abnormal. At this time, the parity rule instruction signal 3 supplied to the parity detection circuit 3 shown in FIG.
0 is the frame pulse 7 after the transfer shown in FIG.
0, the flip-flop 8 as shown in FIG.
, And the stored signal is used as a parity law instruction signal 75 at the time of reading. This prevents the parity rule from being different between the time of writing and the time of reading.

[0004]

However, in such a conventional device, if the clock before the transfer is cut off, the data in the memory is not shifted by the clock, and the data cannot be reached to the read position. I can't. Therefore, the parity check cannot be performed, and the normality of the memory cannot be determined. Further, if the clock before the transfer is interrupted immediately after the parity rule switching, the shift by the clock is not performed as described above. Even if the operation result remains written and does not change, even if it is read and a parity check is performed, unlike the parity rule after switching, a parity error occurs, and this occurs because the clock before switching is cut off. In spite of the state, the apparent state of the elastic memory is abnormal, so that the normality of the elastic memory cannot be monitored.
The present invention has been made in view of such a situation, and enables the normality of an elastic memory to be monitored even if a clock before transfer is lost.

[0005]

SUMMARY OF THE INVENTION In order to solve such a problem, the present invention detects a disconnection of a clock before a transfer.
Generates a clock loss detection signal when
Disconnection detection circuit, clock before transfer and transfer
Both clocks are supplied and the clock loss detection signal is supplied.
If the clock is not supplied, write the clock before changing
When a clock loss detection signal is generated
To the write terminal of the above memory
A selection circuit for supplying and writing data,
Performs parity operation on data written to memory
And a parity operation for supplying the operation result to the memory.
Indicate circuit, frame pulse and parity after transfer
Is supplied, and the frame pal
Flip-flop that outputs a parity rule indication signal synchronized with the
The data read from the memory and the data
And the parity rule instruction signal is supplied.
Parity check according to the
And a parity detection circuit for outputting the result .

[0006]

If the clock before the transfer is supplied normally, the data and the parity result are written accordingly,
If the clock before the transfer is lost, data writing and parity result writing are performed by the clock after the transfer, and writing and reading to and from the memory are continuously performed, so that no memory abnormality occurs.

[0007]

FIG. 1 is a block diagram showing an embodiment of the present invention, and the same parts as those in FIG. 2 are denoted by the same reference numerals and their description is omitted. The pre-replacement clock 50 is supplied to both one input terminal of the selection circuit 4 and the pre-replacement clock disconnection detection circuit 5. The clock 60 after the transfer is supplied to the read terminal of the elastic memory 1 and to the other input terminal of the selection circuit 4. The pre-replacement clock disconnection detection circuit 5 sends out an output signal of “1” level when the pre-replacement clock 50 is disconnected, and the selection circuit 4 outputs “1” from the pre-replacement clock disconnection detection circuit 5. When the signal of the "" level is supplied, the clock 60 after the transfer is selected and transmitted to the write terminal of the elastic memory 1, otherwise, the clock 50 before the transfer is selected and transmitted to the write terminal. It has become.

[0008] When the pre-transfer clock 50 is normally supplied, the apparatus having the above-described configuration can select the selection circuit 4.
Selects it and supplies it to the write terminal of the elastic memory 1 as a write signal 55.
Write data 10 is written to the elastic memory 1. The write data 10 is supplied to the parity operation circuit 2 together with the parity rule instruction signal, where a parity check is performed, and the operation result is written to the elastic memory 1.

The written data is read from the elastic memory 1 by the clock 60 after the transfer,
The data is output as the read data 20, and the read data 20 is supplied to the parity detection circuit 3. The parity detection circuit 3 performs a parity check according to the supplied parity rule instruction signal 75, and obtains a parity detection result 40
Is output.

When the pre-replacement clock is cut off, a "1" level signal is supplied from the pre-replacement clock disconnection detection circuit 5 to the selection circuit 4, so that the selection circuit 4 outputs the post-replacement clock. Select Elastic memory 1
Is output as a write signal 55 to the write terminal. As a result, the write data 10 is sequentially written to the elastic memory 1 by the post-replacement clock 60, whereby the data written to the elastic memory 1 is shifted immediately before the pre-replacement clock is cut off. The transferred data is read out by the clock 60 after the transfer.

The data written in the elastic memory 1 is read out within the same frame period, and the parity law instruction signal changes, for example, every frame signal period. . Although in this for write data and the read data there is a time delay, the time delay is absorbed by the flip-flop 8. In addition, normal clock transfer cannot be performed because the clock before the transfer is cut off, but it is monitored by another monitoring device (not shown) that the clock before the transfer is cut off, the subsequent resynchronization operations recombinant previous clock becomes sectional placed is not guaranteed, it can be known by monitoring the results of the different monitoring devices. For this reason, even if the clock transfer operation is not guaranteed,
In the device of FIG. 1, even if the clock before the transfer is lost,
If so is not performed determination of memory error, the previous clock loss instead put memory abnormality does not occur.

[0012]

As described above, according to the present invention, even if the clock before the transfer is cut off, the continuous operation is performed with the clock after the transfer, so that the clock before the transfer is cut off. Has the effect that no memory abnormality occurs.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of one embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a conventional device.

FIG. 3 is a waveform chart illustrating the operation of the circuit of FIG. 2;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Elastic memory, 2, 3 ... Parity operation circuit, 4 ... Selection circuit, 5 ... Clock disconnection detection circuit before transfer, 8 ... Flip-flop.

Claims (1)

(57) [Claims] An externally supplied data is written into a memory together with a parity check result when a clock before transfer is supplied to a write terminal, and data written when a clock after transfer is supplied to a read terminal. reading, in the memory monitoring device for monitoring the health of the data, before the clock interruption detecting circuit instead put generates a clock interruption detection signal when detecting a disconnection of the pre-changeover clock loaded, handoff previous clock and handoff When both clocks are supplied and the clock disconnection detection signal is not supplied, the clock before switching is supplied to the write terminal of the memory, and when the clock disconnection detection signal is generated, the clock after switching is supplied to the memory. a selection circuit for writing data is supplied to the write terminal and written to the memory Parity calculation on the over data
And supplies the calculation result to the memory.
Operation circuit and a signal indicating the frame pulse and parity after the transfer
Is synchronized with the frame pulse after the transfer.
Flip-flop which outputs a parity rule indicating signal
And the data read from the memory and the parity rule
And an indication signal according to the parity rule indication signal.
Performs parity check and outputs parity detection result
And a parity detection circuit .