JPH0456261A - Lead frame and semiconductor device provided therewith - Google Patents
Lead frame and semiconductor device provided therewithInfo
- Publication number
- JPH0456261A JPH0456261A JP16721190A JP16721190A JPH0456261A JP H0456261 A JPH0456261 A JP H0456261A JP 16721190 A JP16721190 A JP 16721190A JP 16721190 A JP16721190 A JP 16721190A JP H0456261 A JPH0456261 A JP H0456261A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- semiconductor element
- conductive layer
- insulating layer
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 239000011347 resin Substances 0.000 claims abstract description 12
- 229920005989 resin Polymers 0.000 claims abstract description 12
- 238000007789 sealing Methods 0.000 claims abstract description 11
- 239000004020 conductor Substances 0.000 claims 1
- 238000000034 method Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体素子を搭載する半導体用リードフレー
ムおよび半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor lead frame on which a semiconductor element is mounted and a semiconductor device.
従来の技術
第３図（ａ）は従来のリードフレームを用いた半導体装
置の平面図、第３図（ｂ）は第３図（ａ）のＡ−Ａ ’
における断面図である。第３図において、１は半導体素
子、２はリード部、３は封脂用樹脂、４は半導体素子搭
載部、５は端子、６はワイヤである。リードフレームは
リード部２と半導体素子搭載部４で構成される。半導体
装置は半導体素子１をリードフレームの半導体素子搭載
部４に搭載し、半導体素子１の端子５とリード部２をワ
イヤ６で接続し、封止用樹脂３で被覆して構成される。Conventional technology FIG. 3(a) is a plan view of a semiconductor device using a conventional lead frame, and FIG. 3(b) is a diagram taken along line AA' in FIG. 3(a).
FIG. In FIG. 3, 1 is a semiconductor element, 2 is a lead part, 3 is a sealing resin, 4 is a semiconductor element mounting part, 5 is a terminal, and 6 is a wire. The lead frame is composed of a lead part 2 and a semiconductor element mounting part 4. The semiconductor device is constructed by mounting a semiconductor element 1 on a semiconductor element mounting part 4 of a lead frame, connecting terminals 5 of the semiconductor element 1 and lead parts 2 with wires 6, and covering the semiconductor element 1 with a sealing resin 3.
発明が解決しようとする課題
従来のリードフレームは、外部への入出力に必要な端子
５の数だけリード部２が必要であった。Problems to be Solved by the Invention The conventional lead frame required as many lead portions 2 as the number of terminals 5 necessary for external input/output.
そのため、リード部２が多数の場合には必要以上に封止
用樹脂３が太き（なるという問題があった。また、リー
ド部２がアンテナとなってリード部２よりノイズが飛び
込み、誤動作を起こすという問題もあった。本発明は、
このような課題を解決することを目的とする。Therefore, when there are a large number of lead parts 2, there is a problem that the sealing resin 3 becomes thicker than necessary.In addition, the lead part 2 acts as an antenna, and noise enters from the lead part 2, causing malfunction. There was also the problem of causing
The purpose is to solve such problems.
課題を解決するための手段
上記課題を解決するために、本発明はリード部の一部に
絶縁層を設け、かつその上に導電層を形成したものであ
る。Means for Solving the Problems In order to solve the above problems, the present invention provides an insulating layer on a part of the lead portion and forms a conductive layer thereon.
作用
リード部の一部に絶縁層を設け、かつその上に導電層を
形成することにより、１本のリード部で導電層と絶縁層
で被覆されていないリード露出部の２カ所にワイヤ接続
が可能となり、実質のリード部の数が増加することにな
るから、外部への入出力が多い半導体素子を用いる場合
にもリード部の本数を削減することができる。かつ、封
止用樹脂外形の小型化が可能となる。また、リード部を
接地すれば絶縁層上の導電層をシールドした効果が現れ
、耐ノイズ性が向上する。By providing an insulating layer on a part of the working lead part and forming a conductive layer on it, wire connections can be made in two places with one lead part: the conductive layer and the exposed part of the lead not covered with the insulating layer. This makes it possible to increase the actual number of lead portions, so the number of lead portions can be reduced even when using a semiconductor element with many inputs and outputs to the outside. Moreover, the outer shape of the sealing resin can be made smaller. Moreover, if the lead portion is grounded, the effect of shielding the conductive layer on the insulating layer will appear, and the noise resistance will be improved.
実施例
第１図（ａ）は本発明の一実施例におけるリードフレー
ムを用いた半導体装置の平面図、第１図（ｂ）は第１図
（ａ）のＡ−Ａ ’断面図である。本実施例は９つの入
出力端子を持つ半導体素子を６本のリード部を持つリー
ドフレームに搭載した例である。第１図において、１は
半導体素子、２はリード部、３は封止用樹脂、４は半導
体素子搭載部、５は端子、６はワイヤ、７はリード部２
上の一部に形成された絶縁層、８は絶縁層上に形成され
た導電層である。リードフレームは半導体素子搭載部４
と、一部を絶縁層７．導電層８で被覆されたリード部２
から構成される。半導体装置は半導体素子１を半導体素
子搭載部４に搭載し、端子５をワイヤ６で導電層８およ
びリード露出部９のリード部２の２カ所、またはリード
部２のみに接続し、封止用樹脂３で被覆した構成である
。６本のリード部２のうち３本のリード部２の一部に絶
縁層７を設け、その上に導電層８を形成したことにより
、リード部２で１本当り２本のワイヤ６を張ることが可
能となる。Embodiment FIG. 1(a) is a plan view of a semiconductor device using a lead frame according to an embodiment of the present invention, and FIG. 1(b) is a sectional view taken along line AA' in FIG. 1(a). This embodiment is an example in which a semiconductor element having nine input/output terminals is mounted on a lead frame having six lead portions. In FIG. 1, 1 is a semiconductor element, 2 is a lead part, 3 is a sealing resin, 4 is a semiconductor element mounting part, 5 is a terminal, 6 is a wire, and 7 is a lead part 2
An insulating layer 8 formed on a part of the upper portion is a conductive layer formed on the insulating layer. The lead frame is the semiconductor element mounting part 4
and a part of the insulating layer 7. Lead portion 2 covered with conductive layer 8
It consists of In the semiconductor device, the semiconductor element 1 is mounted on the semiconductor element mounting part 4, and the terminals 5 are connected with wires 6 to the conductive layer 8 and the lead part 2 of the lead exposed part 9, or only to the lead part 2. This structure is coated with resin 3. By providing an insulating layer 7 on a part of three of the six lead parts 2 and forming a conductive layer 8 thereon, two wires 6 can be stretched in each lead part 2. becomes possible.
第２図は、本発明の他の実施例におけるリードフレーム
を用いた半導体装置の平面図である。本実施例は１つの
リード部２に複数の導電層８を形成したリードフレーム
を用いた場合の半導体装置である。幅の広いリード部２
に固定（位置決め）用の穴をあけである。このリード部
２を接地することで、導電層８の信号対雑音比（Ｓ／Ｎ
）が６ｄＢ改善された。FIG. 2 is a plan view of a semiconductor device using a lead frame in another embodiment of the present invention. This embodiment is a semiconductor device using a lead frame in which a plurality of conductive layers 8 are formed on one lead portion 2. Wide lead part 2
This is a hole for fixing (positioning). By grounding this lead part 2, the signal-to-noise ratio (S/N) of the conductive layer 8 is
) was improved by 6dB.
本発明の実施例のようにリード部の一部に絶縁層を設け
、かつその上に導電層を形成することにより封止用樹脂
外形を容易に小型化することができる。By providing an insulating layer on a part of the lead portion and forming a conductive layer thereon as in the embodiment of the present invention, the outer shape of the sealing resin can be easily reduced in size.
発明の効果
以上のように、本発明によるリードフレームを用いるこ
とで容易に封止用樹脂外形を小型化することができる。Effects of the Invention As described above, by using the lead frame according to the present invention, the outer shape of the sealing resin can be easily reduced in size.
また、リード部を接地することにより絶縁層上の導電層
にシールド効果が現れ、耐ノイズ性が大幅に向上する。Further, by grounding the lead portion, a shielding effect appears in the conductive layer on the insulating layer, and noise resistance is greatly improved.
第１図（ａ）は本発明の一実施例であるリードフレーム
を用いた半導体装置の平面図、同図（ｂ）は同図（ａ）
のＡ−Ａ’線に沿った断面図、第２図は本発明の他の実
施例であるリードフレームを用いた半導体装置の平面図
、第３図（ａ）は従来のリードフレームを用いた半導体
装置の平面図、同図（ｂ）は同図（ａ）のＡ−Ａ’線に
沿った断面図である。
１・・・・・・半導体素子、２・・・・・・リード部、
３・・・・・・封止用樹脂、４・・・・・・半導体素子
搭載部、５・・・・・・端子、６・・・・・・ワイヤ、
７・・・・・・絶縁層、８・・・・・・導電層。
代理人の氏名 弁理士 粟野重孝 ほか１名第
図
弔
図
第
図FIG. 1(a) is a plan view of a semiconductor device using a lead frame which is an embodiment of the present invention, and FIG.
FIG. 2 is a plan view of a semiconductor device using a lead frame according to another embodiment of the present invention, and FIG. 3(a) is a cross-sectional view taken along line AA' of FIG. A plan view of the semiconductor device, FIG. 2(b) is a sectional view taken along line AA' in FIG. 1(a). 1... Semiconductor element, 2... Lead part,
3... Sealing resin, 4... Semiconductor element mounting part, 5... Terminal, 6... Wire,
7... Insulating layer, 8... Conductive layer. Name of agent: Patent attorney Shigetaka Awano and one other person
Claims (2)
ターンが１つの導体平板に複数個反復して形成されたリ
ード部と、少なくとも１つの前記リード部上の一部に設
けた絶縁層と、前記絶縁層上に形成した導電層とを備え
たことを特徴とするリードフレーム。(1) at least one semiconductor element mounting section, a lead section in which a plurality of lead patterns are repeatedly formed on one conductor flat plate, an insulating layer provided on a part of at least one of the lead sections, and the A lead frame comprising a conductive layer formed on an insulating layer.
部に半導体素子を搭載し、前記半導体素子の異なる端子
をそれぞれ導電層と絶縁層のないリード露出部にワイヤ
接続し、封止用樹脂で被覆したことを特徴とする半導体
装置。(2) A semiconductor element is mounted on the semiconductor element mounting part of the lead frame according to claim 1, and different terminals of the semiconductor element are connected with wires to the lead exposed parts without a conductive layer and an insulating layer, and a sealing resin is used. A semiconductor device characterized by being coated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16721190A JPH0456261A (en) | 1990-06-25 | 1990-06-25 | Lead frame and semiconductor device provided therewith |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16721190A JPH0456261A (en) | 1990-06-25 | 1990-06-25 | Lead frame and semiconductor device provided therewith |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0456261A true JPH0456261A (en) | 1992-02-24 |
Family
ID=15845486
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16721190A Pending JPH0456261A (en) | 1990-06-25 | 1990-06-25 | Lead frame and semiconductor device provided therewith |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0456261A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010153579A (en) * | 2008-12-25 | 2010-07-08 | Denso Corp | Lead frame |
-
1990
- 1990-06-25 JP JP16721190A patent/JPH0456261A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010153579A (en) * | 2008-12-25 | 2010-07-08 | Denso Corp | Lead frame |
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