JPH0451980B2 - - Google Patents
Info
- Publication number
- JPH0451980B2 JPH0451980B2 JP58118516A JP11851683A JPH0451980B2 JP H0451980 B2 JPH0451980 B2 JP H0451980B2 JP 58118516 A JP58118516 A JP 58118516A JP 11851683 A JP11851683 A JP 11851683A JP H0451980 B2 JPH0451980 B2 JP H0451980B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- external lead
- semiconductor device
- semiconductor
- protrude
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 47
- 239000000919 ceramic Substances 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000000465 moulding Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
- H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
- H01L2224/06155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49177—Combinations of different arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明に相対する２辺の近傍にボンデイングパ
ツドが設けられた半導体チツプを有する半導体装
置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device having a semiconductor chip provided with bonding pads near two opposing sides.
デユアルインラインパツケージの半導体装置
は、第１図に示すように、リードフレームからタ
イバー６により保持されたベツド５上に半導体チ
ツプ７をマウントし、外部リード端子２に連続し
ているインナーリード３と半導体チツプ７のボン
デイングパツド１０をワイヤ１１により接続し、
樹脂モールドまたはセラミツク外囲器により封止
したものである。デユアルインパツケージの半導
体装置の寸法は標準化されており、外部リード端
子２のピツチＰは2.54mmまたは1.778mmであり、
直角に曲げた外部リード端子間の寸法Ｌは7.62
mm、10.16mm、15.24mm等である。近年は半導体装
置の機能拡大のため半導体チツプが大きくなり、
逆に半導体装置の外型寸法は高密度実装のため小
型化の要求が強まつている。
As shown in FIG. 1, a dual in-line package semiconductor device has a semiconductor chip 7 mounted on a bed 5 held by tie bars 6 from a lead frame, and an inner lead 3 connected to an external lead terminal 2 and a semiconductor chip 7 mounted on a bed 5 held by tie bars 6 from a lead frame. Connect the bonding pads 10 of the chip 7 with the wires 11,
It is sealed with a resin mold or ceramic envelope. The dimensions of the dual-in-package semiconductor device are standardized, and the pitch P of the external lead terminal 2 is 2.54 mm or 1.778 mm.
The dimension L between the external lead terminals bent at right angles is 7.62
mm, 10.16mm, 15.24mm, etc. In recent years, semiconductor chips have become larger due to the expansion of the functions of semiconductor devices.
On the other hand, there is an increasing demand for miniaturization of the external dimensions of semiconductor devices due to high-density packaging.
このため長方形の半導体チツプ７の短辺長さへ
の制限が厳しくなつている。このため多機能の半
導体チツプ７では、長辺付近にボンデイングパツ
ド１０を設けることが困難になつている。したが
つて例えば半導体メモリでは、半導体チツプ７の
中央部一杯をメモリセル部８とし、短辺付近の領
域９にボンデイングパツド１０を配置するように
している。このように配置することが半導体装置
の外形寸法に対して半導体チツプの実質的な領域
（半導体メモリの場合のメモリセル部）を大きく
とれるからである。 For this reason, restrictions on the short side length of the rectangular semiconductor chip 7 are becoming stricter. For this reason, it has become difficult to provide bonding pads 10 near the long sides of the multifunctional semiconductor chip 7. Therefore, for example, in a semiconductor memory, the entire center of the semiconductor chip 7 is used as the memory cell section 8, and the bonding pad 10 is arranged in the region 9 near the short side. This is because such an arrangement allows the substantial area of the semiconductor chip (memory cell portion in the case of a semiconductor memory) to be larger than the external dimensions of the semiconductor device.
ところがこのような構成の半導体チツプ７を第
１図のようにマウントすると、外部リード端子２
のうち、各外部リード端子列の中央の外部リード
端子２１，２２と、ボンデイングパツド１０１，
１０２との距離が長くなり、これらを電気的に接
続するワイヤ１１が半導体チツプ７のエツジや隣
りのインナーリード３に接触する危険が増す。ま
たワイヤ１１が長いと樹脂モールド時にワイヤ流
れ等の問題が生じやすい。 However, when the semiconductor chip 7 with such a configuration is mounted as shown in FIG.
Among them, the central external lead terminals 21 and 22 of each external lead terminal row, the bonding pad 101,
102 becomes longer, and the risk that the wire 11 that electrically connects them comes into contact with the edge of the semiconductor chip 7 or the adjacent inner lead 3 increases. Further, if the wire 11 is long, problems such as wire drifting are likely to occur during resin molding.
これに対してインナーリード３の先端部の形状
を接続すべきボンデイングパツド１０の方へ伸ば
すことが考えられるが、半導体チツプ７の長辺と
半導体装置の外形との間にはすでにそのようなス
ペースの余裕がない場合が多く、このような方法
を採用することは困難である。 On the other hand, it is conceivable to extend the shape of the tip of the inner lead 3 toward the bonding pad 10 to which it should be connected, but there is already such a gap between the long side of the semiconductor chip 7 and the outer shape of the semiconductor device. It is difficult to adopt such a method because there is often a lack of space.
〔発明の目的」
本発明は上記事情を考慮してなされたもので、
外部リード端子数を2nとしてｎが奇数の場合の
半導体装置に対し、ワイヤの短絡やワイヤ流れの
おきにくい高信頼性の半導体装置を実現すること
を目的とする。[Object of the invention] The present invention was made in consideration of the above circumstances, and
The purpose of this invention is to realize a highly reliable semiconductor device in which the number of external lead terminals is 2n, where n is an odd number, and which is less likely to cause wire short-circuits or wire drift.
上記目的を達成するために本発明による半導体
装置は、半導体チツプの中心を真中の外部リード
端子よりも半ピツチだけシフトして設け、半導体
チツプの２辺のうちシフト方向の１辺の近傍にあ
るボンデイングパツドをひとつ相対する辺の近傍
に移している。
In order to achieve the above object, the semiconductor device according to the present invention is provided such that the center of the semiconductor chip is shifted by half a pitch from the central external lead terminal, and the center is located near one of the two sides of the semiconductor chip in the shift direction. One bonding pad is moved to the vicinity of the opposite side.
本発明の一実施例による半導体装置を第２図に
示す。この半導体装置は18ピンのデユアルインラ
インパツケージであり、タイバー６により保持さ
れたベツド５上に半導体チツプ７をマウントし、
外部リード端子２に連続しているインナーリード
３と半導体チツプ７のボンデイングパツド１０を
ワイヤ１１により接続し、樹脂モールドにより封
止している。
A semiconductor device according to an embodiment of the present invention is shown in FIG. This semiconductor device is an 18-pin dual in-line package in which a semiconductor chip 7 is mounted on a bed 5 held by tie bars 6.
Inner leads 3 continuous to external lead terminals 2 and bonding pads 10 of semiconductor chip 7 are connected by wires 11 and sealed with resin molding.
本実施例では、外部リード端子２の真中の外部
リード端子２１と外部リード端子２２とを結ぶ中
心線から、外部リード端子間ピツチＰの半分だけ
ずれた位置に、半導体チツプ７の中心の位置にシ
フトする。これにより外部リード端子２２とボン
デイングパツド１０２とが近くなる。ところが外
部リード端子２１とボンデイングパツド１０１と
は、逆に遠くなるため、ボンデイングパツド１０
１をシフト方向の領域９１から相対する辺の領域
９２へ移す。このようにすることにより外部リー
ド端子２１とボンデイングパツド１０１とを結ぶ
ワイヤを短くできる。 In this embodiment, the center line of the semiconductor chip 7 is shifted from the center line connecting the external lead terminals 21 and 22 in the middle of the external lead terminals 2 by half the pitch P between the external lead terminals. shift. This brings the external lead terminal 22 and bonding pad 102 closer together. However, since the external lead terminal 21 and the bonding pad 101 are far apart, the bonding pad 10
1 is moved from the area 91 in the shift direction to the area 92 on the opposite side. By doing so, the wire connecting the external lead terminal 21 and the bonding pad 101 can be shortened.
シフトする量を約半ピツチＰ／２としたのは、
半ピツチＰ／２より小さいと、外部リード端子２
１，２２とボンデイングパツドが十分近くなら
ず、半ピツチＰ／２より大きいと、他の外部リー
ド端子を電気的に接続するワイヤが長くなるから
である。例えば外部リード端子２３，２４を接続
するワイヤである。 The reason why the amount of shifting was set to about half a pitch P/2 is because
If the half pitch is smaller than P/2, the external lead terminal 2
This is because if the bonding pads 1 and 22 are not sufficiently close to each other and the pitch is larger than half pitch P/2, the wires that electrically connect other external lead terminals will become long. For example, it is a wire that connects the external lead terminals 23 and 24.
先の実施例では18ピンの半導体装置の場合を示
したが、デユアルインラインパツケージの一方の
列の外部リード端子が奇数であれば良い。特に14
ピン、18ピン、22ピンの半導体装置に有効であ
る。また樹脂封止型に限らず、セラミツクパツケ
ージの半導体装置、特にサーデイツプタイプ
（Cerdip type）の半導体装置にも有効である。 In the previous embodiment, the case of an 18-pin semiconductor device was shown, but it is sufficient if the number of external lead terminals in one row of the dual in-line package is an odd number. especially 14
Effective for pin, 18-pin, and 22-pin semiconductor devices. Moreover, it is effective not only for resin-sealed semiconductor devices but also for semiconductor devices in ceramic packages, especially Cerdip type semiconductor devices.
なお、先の実施例は外部リード端子が直角に曲
げられたいわゆるデユアルインラインパツケージ
の半導体装置であつたが、外部リード端子が直角
に曲げられていないいわゆる「フラツトデユアル
インパツケージ」の半導体装置についても適用す
ることができる。 Although the previous embodiment was a so-called dual-in-line package semiconductor device in which the external lead terminals were bent at right angles, this example is about a so-called "flat dual-in-line package" semiconductor device in which the external lead terminals are not bent at right angles. can also be applied.
以上の通り本発明によれば、ボンデイングのた
めのワイヤを短くすることができ、ワイヤと半導
体チツプや他の外部リード端子との接触やワイヤ
流れによる不良を防止でき、高信頼性の半導体装
置を実現できる。外部リード端子とボンデイング
パツドの距離とが長いため、従来はセラミツクパ
ツケージのレイヤータイプ（Layer Type）等で
パツケージングする必要のあつたものを、安価な
封脂モールドタイプにすることができ、高機能の
半導体装置を安価に提供することができる。
As described above, according to the present invention, the wire for bonding can be shortened, and defects caused by contact between the wire and the semiconductor chip or other external lead terminals or wire drift can be prevented, and highly reliable semiconductor devices can be manufactured. realizable. Because the distance between the external lead terminal and the bonding pad is long, it is now possible to use an inexpensive resin-sealed mold type instead of a ceramic package that required layer type packaging. A functional semiconductor device can be provided at low cost.
第１図は従来の半導体装置の平面図、第２図は
本発明の一実施例による半導体装置の平面図であ
る。
２，２１，２２，２３，２４……外部リード端
子、３……インナーリード、５……ベツド、６…
…タイバー、７……半導体チツプ、８……メモリ
セル部、１０，１０１，１０２……ボンデイング
パツド。
FIG. 1 is a plan view of a conventional semiconductor device, and FIG. 2 is a plan view of a semiconductor device according to an embodiment of the present invention. 2, 21, 22, 23, 24...External lead terminal, 3...Inner lead, 5...Bed, 6...
... Tie bar, 7... Semiconductor chip, 8... Memory cell section, 10, 101, 102... Bonding pad.
Claims (1)
する２側面からそれぞれ一定ピツチでｎ個づつ突
出し、他の相対する２側面からは突出していない
外部リードと、前記外部リードの突出していない
パツケージ外側面に対向する２辺の近傍にそれぞ
れボンデイングパツトが設けられた半導体チツプ
とを有する半導体装置において、ｎ個の前記外部
リードの中央位置に対して、前記半導体チツプの
中央位置を前記一定ピツチのほぼ半分だけシフト
し、前記ボンデイングパツトが設けられる前記半
導体チツプの２辺のうち、シフト方向の１辺の前
記ボンデイングパツトの数をｎ−１個とし、他の
１辺の前記ボンデイングパツトの数をｎ＋１個と
したことを特徴とする半導体装置。1 With n being an odd number, n external leads protrude at a constant pitch from two opposing sides of the outer circumferential side of the package, and do not protrude from the other two opposing sides, and external leads do not protrude from the outer surface of the package from which the external leads do not protrude. In a semiconductor device having a semiconductor chip having a bonding pad provided near each of two opposing sides, the center position of the semiconductor chip is set by approximately half of the constant pitch with respect to the center position of the n external leads. Of the two sides of the semiconductor chip on which the bonding pads are provided, the number of bonding pads on one side in the shift direction is n-1, and the number of bonding pads on the other side is n+1. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58118516A JPS6010651A (en) | 1983-06-30 | 1983-06-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58118516A JPS6010651A (en) | 1983-06-30 | 1983-06-30 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6010651A JPS6010651A (en) | 1985-01-19 |
| JPH0451980B2 true JPH0451980B2 (en) | 1992-08-20 |
Family
ID=14738557
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58118516A Granted JPS6010651A (en) | 1983-06-30 | 1983-06-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6010651A (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0732223B2 (en) * | 1985-01-11 | 1995-04-10 | 三菱電機株式会社 | Semiconductor device |
| EP0242962A1 (en) * | 1986-04-25 | 1987-10-28 | Inmos Corporation | Offset pad semiconductor lead frame |
| JPH0719872B2 (en) * | 1987-03-30 | 1995-03-06 | 三菱電機株式会社 | Semiconductor device |
| JP2560805B2 (en) * | 1988-10-06 | 1996-12-04 | 三菱電機株式会社 | Semiconductor device |
| JP2885167B2 (en) * | 1996-03-11 | 1999-04-19 | 三菱電機株式会社 | Semiconductor device |
| DE102005062344B4 (en) | 2005-12-23 | 2010-08-19 | Infineon Technologies Ag | Semiconductor component for high-frequency applications and method for producing such a semiconductor component |
| WO2023176267A1 (en) * | 2022-03-17 | 2023-09-21 | ローム株式会社 | Semiconductor device |
-
1983
- 1983-06-30 JP JP58118516A patent/JPS6010651A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6010651A (en) | 1985-01-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8502395B2 (en) | Semiconductor device and a method of manufacturing the same | |
| US8053278B2 (en) | Multi-chip package type semiconductor device | |
| US5545921A (en) | Personalized area leadframe coining or half etching for reduced mechanical stress at device edge | |
| KR920008250B1 (en) | A semiconductor which is a resin envelope type | |
| JPH0451980B2 (en) | ||
| JP3124381B2 (en) | Semiconductor device and mounting structure | |
| JPS61258458A (en) | Resin-sealed ic | |
| JPH0546098B2 (en) | ||
| US6737733B2 (en) | Sealed semiconductor device and lead frame used for the same | |
| US5925927A (en) | Reinforced thin lead frames and leads | |
| KR0148078B1 (en) | Lead on chip having forward lead | |
| JPH02133942A (en) | Ceramic-chip carrier type semiconductor device | |
| US6949820B2 (en) | Substrate-based chip package | |
| JP3082507U (en) | Double side chip package | |
| US20220157681A1 (en) | Integrated circuit package with v-shaped notch creepage structure | |
| JP2563507Y2 (en) | Semiconductor device | |
| JPH01206652A (en) | Semiconductor device | |
| JPS60113958A (en) | Semiconductor device | |
| JPS6079733A (en) | Semiconductor device | |
| KR200164518Y1 (en) | Semiconductor package | |
| JPH04134853A (en) | Lead frame for semiconductor device | |
| JPH0888310A (en) | Resin-sealed semiconductor device | |
| JPH01270256A (en) | Semiconductor device | |
| JPS59198744A (en) | Resin sealed type semiconductor device | |
| JPH0669411A (en) | Semiconductor device |