JPH0451488Y2 - - Google Patents
Info
- Publication number
- JPH0451488Y2 JPH0451488Y2 JP1987056960U JP5696087U JPH0451488Y2 JP H0451488 Y2 JPH0451488 Y2 JP H0451488Y2 JP 1987056960 U JP1987056960 U JP 1987056960U JP 5696087 U JP5696087 U JP 5696087U JP H0451488 Y2 JPH0451488 Y2 JP H0451488Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- wiring conductor
- external
- lead
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987056960U JPH0451488Y2 (instruction) | 1987-04-15 | 1987-04-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987056960U JPH0451488Y2 (instruction) | 1987-04-15 | 1987-04-15 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63164245U JPS63164245U (instruction) | 1988-10-26 |
| JPH0451488Y2 true JPH0451488Y2 (instruction) | 1992-12-03 |
Family
ID=30886237
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987056960U Expired JPH0451488Y2 (instruction) | 1987-04-15 | 1987-04-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0451488Y2 (instruction) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60160154A (ja) * | 1984-01-30 | 1985-08-21 | Nec Kansai Ltd | Hic |
-
1987
- 1987-04-15 JP JP1987056960U patent/JPH0451488Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63164245U (instruction) | 1988-10-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4941033A (en) | Semiconductor integrated circuit device | |
| JP2819285B2 (ja) | 積層型ボトムリード半導体パッケージ | |
| US6028358A (en) | Package for a semiconductor device and a semiconductor device | |
| US4618739A (en) | Plastic chip carrier package | |
| JPH10242210A (ja) | 集積回路装置の実装構造およびその製造方法 | |
| JPH064595Y2 (ja) | ハイブリッドic | |
| WO2003005445A1 (fr) | Dispositif a semiconducteur et module a semiconducteur | |
| JP3553849B2 (ja) | 半導体装置及びその製造方法 | |
| US5099395A (en) | Circuit board for mounting electronic components | |
| US5422515A (en) | Semiconductor module including wiring structures each having different current capacity | |
| JP3656861B2 (ja) | 半導体集積回路装置及び半導体集積回路装置の製造方法 | |
| JP3258428B2 (ja) | 複合半導体装置の製造方法 | |
| JP3549316B2 (ja) | 配線基板 | |
| JPH06283639A (ja) | 混成集積回路 | |
| JPH0451488Y2 (instruction) | ||
| JPH0645504A (ja) | 半導体装置 | |
| JP3942495B2 (ja) | 半導体装置 | |
| JPS6250063B2 (instruction) | ||
| JP3297959B2 (ja) | 半導体装置 | |
| JPH0622997Y2 (ja) | 絶縁物封止型半導体装置 | |
| JPH0442942Y2 (instruction) | ||
| JP3048707B2 (ja) | 混成集積回路 | |
| JPH0358537B2 (instruction) | ||
| JPS58178544A (ja) | リ−ドフレ−ム | |
| JPH0741167Y2 (ja) | 絶縁物封止型回路装置 |