JPH0448746A - Semiconductor device - Google Patents

Abstract

PURPOSE:To approach an area of an OR term of a programmable logic array to 1/2 as near as possible and to perform contraction of the array by approaching the general shape of the OR term to a triangle, and splitting an AND term and the block of the OR term relative to the output inclusive by the number of outputs of the AND term of about 1/2. CONSTITUTION:A programmable logic array input 22 is input to an AND term 32, an output 23 from the term 32 is input to an OR term 34, and an output 24 is produced from the term 34. One programmable logic array input 22 is input to an AND term 33, and the output from the term 33 is input to an OR term 35. The term 34 is connected to the term 35 via a connecting line 25. When the length of one side of a coating cell 8 is m, the length of the other side is n, the lengths of one sides of a precharge transistor 9 of the AND term and precharge transistor 10 of the OR term are m, and the lengths of the other sides are q, the area S of the array is S=S1+S2, where S1=(6X2n+q)16m, S2=13n(8m+1), the S1 is the area of the AND term, and the S2 is the area of the OR term.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device using a programmable logic array.

Prior art programmable logic arrays basically consist of an AND term that decodes the inputs and an 02 term that takes out the programmable logic array output.

Hereinafter, a conventional example will be explained with reference to FIGS. 8 to 11.

FIG. 8 shows an example of a programmable logic array having 6 bits of input, 16.02 product terms, and 11 outputs. FIG. 10 is a block diagram of a general programmable logic array.

In Fig. 8, inputs 1 to 6 generate negative polarity signals through one stage of inverter 7, and positive polarity signals through two stage valves.
It is connected to each coating cell 8 of section D. Also,
16 with precharge transistor 9 from AND term
The plurality of outputs are connected to each coating cell 8 of the 02 term and have a precharge transistor 10 of the 02 term.
This results in one programmable logic array output 11-21.

FIGS. 9(a), 9(b), and 9(c) are circuit diagrams showing the connection state of coating cell 8 and precharge transistors 9 and 10, respectively.

The above is shown in a block diagram in FIG. 10, where the programmable logic array input 22 enters the AND term 30, and the A
The output 23 from the ND term is input to the OR term 31, and its O
Output 24 is taken out from R term 31. OR term 31
A plurality of coating cells 8 are arranged in the inside of the rectangle, and the approximate shape becomes a rectangle as a result.

The area S of the programmable logic array shown in FIG. 8 is given by the length of one side of the coating cell 8 being m1 and the length of the other side being n, and the precharge transistor 9 of the AND term and the precharge transistor 10 of the 02 term. When the length of one side is m1 and the length of the other side is q, it is given by the following formula.

S+= (6X2n+q)16m −(1)S2=
11 n (16m1q) ---(2) s=sl
+s2 ・・・・・・・・・・・・・・・・・・
・・・・・・・・・ (3) S indicates the area of the AND term, and S
2 indicates the area of the 02 term.

Further, an example of the operation of the programmable logic array shown in FIG. 8 will be explained using the timing chart shown in FIG. 11. AND term precharge control signals 28 and 02
The precharge control signal 29 of the term becomes active (low level) at the same time and charges up the output lines of the AND term and the 02 term, and during this charging up, the input signals 1 to 6 of the programmable logic array are determined. . Next, the AND term precharge control signal 28 becomes non-active, and all but one AND term to be selected are discharged. After a sufficient time TND for this discharge, the precharge control signal 28 of the 02 term becomes non-active, and the output of the one AND term that has been selected and becomes high level becomes the 02 term.
The gates of all coating cells that cross this high level signal line are turned on, and the output of the 02 term connected to that coating cell is discharged.

Problems to be Solved by the Invention Reducing the area of the AND term, that is, reducing the number of outputs of the AND term, is possible by, for example, the Queen-McCrawsky method. ) Since the number of lines is fixed, it is difficult to reduce the area of item 02. However, if you look inside the block of item 02 in FIG. 8, which is shown as a conventional example,
The coating cells 8 are by no means all over the block of section 02. In other words, unnecessary areas without coating cells 8 are scattered in the block of item 02, and there is a problem in that unnecessary costs are generated by the areas.

In addition, from the perspective of increasing the speed of programmable logic arrays, since %TND is not constant due to variations in semiconductor device characteristics, since the system clock is used, 1/2 of this system clock FSYS is the minimum unit. , it is necessary to establish the following formula.

As a result, the instruction interpreter (programmable logic array), which is required to operate at the highest speed, cannot demonstrate its high speed, and the programmable logic array requires 3 clocks to operate. (Execution 1, Execution 2, Execution 3 in FIG. 11) has the problem of slowing down the entire microcomputer.

The present invention is intended to solve this problem, and aims to reduce the area of a programmable logic array, reduce costs, and improve operating speed.

Means for Solving the Problems The semiconductor device of the present invention is a programmable logic array in which the number of coating cells in the OR term connected to the AND term output of the programmable logic array is reduced as much as possible, including the reduction of the number of AND terms. each AND
Depending on the number of coating cells in the 02 terms connected to the term, the AND terms are arranged in order of increasing or decreasing order, and the output line from the AND term is deleted at the end where the gate of the coating cell in each OR term is present. In addition, the order of the outputs of the 02 terms is changed from high to low according to the number of coating cells, so that the outline of the 02 terms approaches a triangle, and the number of outputs of the AND terms is approximately 1/2. Divide into two including the 02 term block related to the term and its output, and divide one of the divided AND terms and the 02 term block,
Mirror inversion is performed with respect to the input direction of the AND term, and A
AND created by mirror inversion with respect to the output direction of the ND term
Align the end of the 02 term of the 02 term block and the 02 term end of the other AND term and 02 term block that is not mirrored so that the output of the AND term of each block will not be short-circuited. This is a reconstruction by connecting the outputs of the 02 terms of each of the two blocks divided at the time of division into two outside the two blocks.

According to the present invention, under the best conditions, the area of the 02 term of the programmable logic array can be reduced to as close as possible to 1/2, and the size of the programmable logic array can be reduced.

In addition, the number of locks required for programmable logic array operation can be reduced to two (Execution 1 and Execution 2 in Figure 4).
The programmable logic array can be operated at high speed almost to the limit of the performance of the transistors depending on the process parameters forming the programmable logic array.

Embodiment An embodiment of the present invention will be described with reference to the drawings.

FIG. 6 shows the conversion process for configuring the semiconductor device of the present invention. In the programmable logic array, inputs 1 to 6 of the AND term are supplied with negative polarity signals through one stage of inverter 7, and positive polarity signals through two stages. A signal is generated and connected to each coating cell 8 of the AND term. In addition, the AN
The 16 plurality of outputs with precharge transistors 9 from the D term become 11 programmable logic array outputs 11 to 21 connected to each coating cell 8 of the 02 term and have the precharge transistor 10 of the 02 term. FIG. 7 shows the result of rearranging the 16 outputs from the AND term in FIG. 8 shown as an example, and removing the wiring from the output line of each AND term to the point where the coating cell exists in the OR term. The rule for rearranging was the order of the number of coating cells in the OR term connected to the output of the 16 AND terms. As a result, as shown in FIG. 6, the block of term 02 becomes approximately triangular, and a blank portion occurs. In order to make the triangular portion of the margin as large as possible, it may be necessary to rearrange the output of the 02 term as well. This configuration is shown in FIG.

In this Figure 7, the AND term is divided into two at approximately the half position (line 10 in the figure), and the lower AND term and the 0
Using term 2 as a block, mirror invert it in the vertical and horizontal directions, move the mirror inverted block so that the non-mirrored term 02 and the diagonal part of the mirror inverted term 02 almost match, The two separated 02 terms are reconnected externally (this connection corresponds to the connection line 25 in FIG. 2).

The circuit diagram of the semiconductor device of the present invention produced by the above operations is shown in the first diagram.
2, and its block diagram is shown in FIG.

In Figure 2, programmable logic array human power 2
2 enters the AND term 32 and the output 23 from the AND term 32
is input to the OR term 34, and the output 24 from the OR term 34 is
is taken out. Also, one programmable logic array input 22 enters an AND term 33, and the output 23 from the AND term 33 is input to an OR term 35. OR term 34 and O
The R terms 35 are connected to each other by a connecting line 25.

The area S of the programmable logic array shown in FIG. When the length of one side is m1 and the length of the other side is q, it is given by the following formula.

SI= (6x2n+q)16m ・・・・・・ (
4) S2=13n (8m1q) ・・・・・・・・・
・・・・・・ 6) S=S, +S2・・・・・・・・・・・・
・・・・・・・・・・・・・・・・・・・・・ (6) Sl
indicates the area of the AND term, and S2 indicates the area of the 02 term.

FIG. 3 shows another embodiment. The basic configuration is the same as in FIG. 1, but one output (reference line) is added to the AND term, and the precharge control in term 02 is different.

In the embodiment of FIG. 3, one of the two AND terms is
In order to always discharge in the discharge mode regardless of the input data of the AND term, a coating cell is applied to both the negative polarity signal through one stage of inverter 7 and the positive polarity signal through two stages as the input of the AND term. 8 is arranged, a coating cell is placed between this output and all output lines of the 02 term corresponding to this output, and an inverter 27 is connected to the terminal of the OR term of the AND term output. Connect the input to this inverter 2
The output of 7 is connected to the gate of a precharge transistor 10 which is connected to the total OR term output. The block diagram of FIG. 3 is the same as that of FIG.

As an example of the operation of the embodiment shown in FIG. 3, a timing chart is shown in FIG. 4, and the operation of the programmable logic array will be explained. When the precharge control signal 28 of the AND term becomes active (low level), all the precharge transistors 9 of the AND term are turned on, and the outputs of all the AND terms become high level. Therefore, one output 26 of the AND term also becomes high level, the output of the inverter 27 becomes low level, and all the precharge transistors 9 of the 02 terms connected thereto are turned on. Next, when the AND term precharge control signal 28 becomes non-active (high level),
All but one AND term that should be selected are ANDed.
The term is discharged. At this time, the reference
Compared to other AND term outputs, the line output 26 has two more coating cells and has a larger load capacity.
It is always discharged later than the output of the other AND terms. This delayed reference line output 260 low level is input to the inverter 27, and all the precharge transistors 10 of the 02 terms connected to the output of the inverter 27 are turned off, and the output of one of the selected AND terms is turned off. Only the outputs of the arranged 02 terms are discharged and operate as a programmable logic array. Therefore, in order to control the precharge transistor 10 in term 02 with the AND term output output guaranteeing a large discharge delay by the reference line output 26, the semiconductor process parameters can be adjusted by simply controlling the AND term precharge control signal 28. The programmable logic array can be operated in an optimal state according to the application.

Further, FIG. 5 shows a third embodiment. Figure 5 shows an AN in which the two AND terms in Figure 3 have no connection with the 02 term.
Section D has been added. This prevents only the area of the wiring 25 connecting the two 02 terms from protruding from the programmable logic array block, and also allows the simple decoding section that does not require the 02 terms to be compactly housed in the same programmable logic array block. I can do it.

Effects of the Invention According to the present invention, the programmable logic array 02
In the best case, the term can be reduced to 1/2, which helps reduce product costs. Particularly in microcomputers that require complicated control, the programmable logic array for interpreting instructions becomes large, and the present invention becomes very effective. In the actual case, the number of inputs is 13 and the number of AND terms is about 200.
A programmable logic array with approximately 50 OR terms can save approximately 30% of the area compared to conventional technology.

In addition, by providing the reference line output 26, the precharge control in item 02 can be completely automatic depending on process parameters, and does not require a system clock such as a microcomputer as shown in the conventional example. This makes it possible to operate accurately and at high speed. In other words, in the past, a total of 3 clocks were required: 1 clock for precharging the AND term and the 02 term, 1 clock for discharging the AND term, and 1 clock for discharging the 02 term, but according to the present invention, the AND term and 0
A total of 2 clocks, 1 clock for precharging in the 2nd term and 1 clock for discharging in the 02nd term, is required, and the time can be reduced by 2/3 (compared to the conventional example shown in Figure 11 and the example of the present invention shown in Figure 4). (See timing chart).

As described above, the present invention is extremely effective since it can achieve the effect of reducing the size and increasing the speed of the programmable logic array.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a block diagram thereof. FIG. 3 is a circuit diagram of another embodiment of the semiconductor device according to the present invention, and FIG. 4 is a timing chart for explaining its operation. FIG. 5 is a circuit diagram of still another embodiment of the semiconductor device according to the present invention. FIG. 6 is a circuit diagram showing the conversion process for configuring the semiconductor device of the present invention, and FIG. 7 is a diagram for explaining the process. Figure 8 is a circuit diagram of a conventional example, Figure 9 (a
), (b), and (C) are wiring diagrams of cells in the conventional example, FIG. 10 is a block diagram thereof, and FIG. 11 is a timing chart for explaining its operation. 7...Inverter, 8...Coating cell, 9゜10...Precharge transistor, 1
1 to 21...Output, 22...Input, 2
3...Output, 24...Input, 25...
・Connection line, 26...Reference line, 2
7...Inverter, 28.29...Precharge control signal. Name of agent Patent attorney Shigetaka Kurino One idiot Figure 1 Figures 1-6 Enter Figure 2 Figure Figure Figure Figure Figure Figure Figure Funeral diagram

Claims (2)

[Claims] (1) In a programmable logic array in which the number of coating cells in the OR term connected to the AND term output is reduced including the reduction of the number of AND terms, the number of coating cells in the OR term connected to each AND term is reduced. Accordingly, the order of the AND terms is arranged in order of increasing or decreasing order, and the output line from the AND term is deleted at the end where the gate of the coating cell in each OR term exists, and the order of the output of the OR term is also coated. Depending on the number of cells, the approximate shape of the OR term is approximated to a triangle by rearranging it in ascending or descending order according to the number of cells, and with the number of outputs of the AND term being approximately 1/2, the AND term and the OR term related to its output are Divide into two including the block,
One divided block of AND term and OR term is AN
In addition to mirror inversion with respect to the input direction of the D term, AND
The end of the OR term of the block of AND terms and OR terms created by mirroring the output direction of the term, and the end of the OR term of the block of AND terms and OR terms that are not mirrored, respectively. A semiconductor device characterized in that it is reconfigured by connecting the outputs of the OR terms of the two blocks divided at the time of said two blocks outside the two blocks so that the outputs of the AND terms of the blocks do not short-circuit. . (2) In the AND term, provide one AND term output that is always discharged in the discharge mode regardless of the input data of the AND term, and place a coating cell on all output lines of the OR term corresponding to this output, Claim characterized in that the input of an inverter is connected to the terminal end of the OR term of the AND term output, and the output of the inverter is connected to the gate of a precharge transistor connected to all the OR term outputs. 1. The semiconductor device according to 1.