JPH01135118A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce noise and radiation by dividing an output transistor(TR) into plural number, and triggering each output TR by a respective signal having a time series delay. CONSTITUTION:An input signal 1 is delayed by an inverter 2 and an N-channel output TR 14 is triggered by the retarded signal. Then the next Nch output TR 5 is triggered by a signal retarded further by inverters 2, 3 and Nch output TRs 6,7 are triggered by signals 8,9 retarded similarly to smooth the leading edge (for Pch) and trailing edge (for Nch) of a final output signal 18. Thus, noise and radiation are reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an input signal system for a semiconductor integrated circuit.

[Conventional technology]

Figure 3 is a circuit diagram showing the configuration of a conventional CMO3 output transistor. In the figure, (1) is the input signal, (25)
, (26) is the inverter, (27) , (2
8) is the signal from each inverter to the output transistor, (29) is the Pch output transistor, (30
) is the Nch output transistor, and the symbol a is the output signal from both of the Nch output transistors.

Figure 4 is a waveform diagram of each signal in Figure 3. In the figure, 09) is the input signal (11, (31) is the signal (27) and (28) from the two inverters to the output transistors.
.

(24) represents the output signal waveform from both channel output transistors.

Next, FIG. 3 will be explained in detail. First, when outputting "L", the input signal (1) is "simply input", the two inverters (25) and (26) invert the input signal, and the signals (27) and (28) are used to invert the input signal. The inverted signal "H" is sent to the output transistors (29) and (30).The "H" signal turns the Nch output transistor "ON", the Pch output transistor "OFF", and the output signal 0 becomes 'L'. °゛ appears.

Next, when outputting “H”, input signal (1) is “H”.
is input, and the two inverters (25) and (26) are
The signal is inverted and the inverted signal "L" is transmitted to the respective output transistors (29) and (30) through (27) and (2B). The "1." signal turns the Nch output transistor "OFF", the Pch output transistor turns "L" (ON), and "■" is output to the output signal α9).

[Problem that the invention attempts to solve]

In the conventional MO3 output port, the output transistor is large, the output waveform is sharp, and a lot of noise and radiation is generated. In addition, there was a problem that the transistor size could not be reduced unnecessarily due to DC requirements.

This invention was made to solve the above problems, and the output transistor has the same size as the conventional one in terms of DC, and the rise and fall of the waveform are smoothed to reduce noise and radiation. The purpose is to

[Means for solving problems]

The output transistor configuration according to the present invention is such that the output transistor is divided into a plurality of parts, and each output transistor is driven by a plurality of signals delayed in time series.

[Effect]

In the output transistor circuit of the present invention, a plurality of output transistors are triggered with a time delay when a signal changes, thereby smoothing the rise and fall of an output signal and reducing noise and radiation.

〔Example〕

An embodiment of the present invention in a CMO3 will be described below with reference to the drawings. In FIG. 1, (1) is an input signal to the output transistor circuit, (2) to (5) are four pairs of inverters for generating signals with four stages of time-series delay, and (6) to ( 9) is a gate for generating a delayed trigger signal for each stage, αυ~ is a delayed trigger signal for each stage, 041-07) is a 4-stage Nch output transistor, 0
8) is the output signal from this output transistor circuit. Figure 2 is a waveform diagram showing the waveform and timing of each signal in this output transistor circuit.
is the input signal to the output transistor circuit, (28) is the signal delayed by the inverter (2) and the gate (6),
(21) is the inverter (2) and (3) and the gate (7)
The signal delayed by (22) is inverter (21,
(31 and (4) and the signal (23) delayed by gate (8) is inverter (21, (31, +41 and (5)
and the signal delayed by gate (9), (24) is 4
This is a signal waveform output by two Nch output transistors.

Next, the configuration of the present invention will be explained in detail.

First, an incoming input signal (1) is delayed by an inverter (2), and the delayed signal triggers the Nch output transistor Oa. Next, inverter +
21. +3) triggers the next Nch output transistor (5), and in the same way, further delayed signals (8) and (9) trigger the Nch output transistors (6) and (7). By being triggered, the final output signal 08) rises (Pc
h) and falling edge (at Nch) are smooth.

In addition, although the above embodiment has been explained using the CMO3 circuit as an example, it can be implemented in the same manner with other NMO3 and PMO3 circuits, and the same effects can be obtained.

In addition, in the above embodiment, gates (6) to
(9) is used, but this is not limited to a gate; any circuit that can obtain a delay, such as a CR open circuit, may be used.

〔Effect of the invention〕

As described above, according to the present invention, the output transistor is divided into a plurality of parts, and each output transistor is configured to be triggered by each signal having a time-series delay. Since the falling edge (Nch) becomes smooth, noise and radiation can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an 0MO3 output transistor according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing signal waveforms of each part of the circuit in FIG. 1, and FIG. 3 is a diagram showing a conventional 0MO3 output transistor.
FIG. 4 is a circuit configuration diagram showing a three-output transistor. FIG. 4 is a waveform diagram showing signal waveforms at various parts of the circuit in FIG. In the figure, (1) is the input signal to the output transistor circuit, (2) to (5) are four pairs of inverters for generating signals with four stages of time-series delay, and (6) to (9) are the input signals to the output transistor circuit.
) are gates for generating delayed trigger signals for each stage, 00) to 03) are delayed trigger signals for each stage, Oa to Q
71 is a four-stage Nch output transistor, αB) is the output signal from the output transistor circuit, 09) is the input waveform to the output transistor circuit, (2) is the signal delayed by the inverter (2) and the gate (61) (21) is the waveform of the signal delayed by the inverter (21, (31) and gate (7), (22) is the waveform of the signal delayed by the inverter (21, (31) and gate (7),
1, (waveform of signal delayed by 41 and gate (8), (23) is inverter (2), +31,
(The waveforms of the signals delayed by 41 and (5) and the gate (9) are shown. In the figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A semiconductor integrated circuit characterized in that an output transistor is divided into a plurality of output transistors, and an input signal that rises in time series and falls simultaneously when falling is applied to each output transistor at an output terminal for outputting a signal.