JPH0445864B2 - - Google Patents

Info

Publication number
JPH0445864B2
JPH0445864B2 JP57165089A JP16508982A JPH0445864B2 JP H0445864 B2 JPH0445864 B2 JP H0445864B2 JP 57165089 A JP57165089 A JP 57165089A JP 16508982 A JP16508982 A JP 16508982A JP H0445864 B2 JPH0445864 B2 JP H0445864B2
Authority
JP
Japan
Prior art keywords
address
data
output
latch circuit
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57165089A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5955538A (ja
Inventor
Akio Iba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP57165089A priority Critical patent/JPS5955538A/ja
Publication of JPS5955538A publication Critical patent/JPS5955538A/ja
Publication of JPH0445864B2 publication Critical patent/JPH0445864B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Electrophonic Musical Instruments (AREA)
  • Executing Machine-Instructions (AREA)
JP57165089A 1982-09-24 1982-09-24 ネクストアドレス方式のプロセッサ Granted JPS5955538A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57165089A JPS5955538A (ja) 1982-09-24 1982-09-24 ネクストアドレス方式のプロセッサ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57165089A JPS5955538A (ja) 1982-09-24 1982-09-24 ネクストアドレス方式のプロセッサ

Publications (2)

Publication Number Publication Date
JPS5955538A JPS5955538A (ja) 1984-03-30
JPH0445864B2 true JPH0445864B2 (enrdf_load_stackoverflow) 1992-07-28

Family

ID=15805668

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57165089A Granted JPS5955538A (ja) 1982-09-24 1982-09-24 ネクストアドレス方式のプロセッサ

Country Status (1)

Country Link
JP (1) JPS5955538A (enrdf_load_stackoverflow)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5938616B2 (ja) * 1977-06-02 1984-09-18 横河電機株式会社 マイクロ・プログラム制御装置

Also Published As

Publication number Publication date
JPS5955538A (ja) 1984-03-30

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