JPH0444692U - - Google Patents
Info
- Publication number
- JPH0444692U JPH0444692U JP8639090U JP8639090U JPH0444692U JP H0444692 U JPH0444692 U JP H0444692U JP 8639090 U JP8639090 U JP 8639090U JP 8639090 U JP8639090 U JP 8639090U JP H0444692 U JPH0444692 U JP H0444692U
- Authority
- JP
- Japan
- Prior art keywords
- analog switch
- signal
- controlled oscillator
- reference clock
- voltage controlled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010355 oscillation Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Transforming Electric Information Into Light Information (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Liquid Crystal Display Device Control (AREA)
- Synchronizing For Television (AREA)
Description
第１図及び第２図は本考案の一実施例を示し、
第１図はＰＬＬ回路を示す構成説明図、第２図は
第１図の各部の信号の関係を示すタイムチヤート
、第３図は従来のＰＬＬ回路を示す構成説明図、
第４図は第３図の各部の信号の関係を示すタイム
チヤートである。
１１……アナログスイツチ、１４……ローパス
フイルタ、１５……電圧制御発振器、１７……分
周器、１８，１９……アンドゲート、２１……イ
ンバータ、２２……オアゲート。
1 and 2 show an embodiment of the present invention,
FIG. 1 is a configuration explanatory diagram showing a PLL circuit, FIG. 2 is a time chart showing the relationship of signals in each part of FIG. 1, and FIG. 3 is a configuration explanatory diagram showing a conventional PLL circuit.
FIG. 4 is a time chart showing the relationship of signals in each part of FIG. 3. 11... Analog switch, 14... Low pass filter, 15... Voltage controlled oscillator, 17... Frequency divider, 18, 19... AND gate, 21... Inverter, 22... OR gate.
Claims (1)
同期信号に従つて開閉される位相比較用アナログ
スイツチと、 このアナログスイツチからの出力信号が積分さ
れるローパスフイルタと、 このローパスフイルタの出力電圧レベルに従つ
て発振周波数が制御され、基準クロツクを発生す
る電圧制御発振器と、 前記ビデオ信号の垂直帰線消去期間内は前記電
圧制御発振器からの基準クロツクを前記アナログ
スイツチへの入力比較信号とし、前記ビデオ信号
の垂直帰線消去期間外は前記電圧制御発振器から
の基準クロツクを分周したクロツクパルスを前記
アナログスイツチへの入力比較信号とする選択回
路と を具備することを特徴とするＰＬＬ回路。[Claims for Utility Model Registration] A phase comparison analog switch to which a comparison signal is input and which is opened and closed in accordance with a synchronization signal obtained from a video signal; a low-pass filter in which an output signal from this analog switch is integrated; A voltage controlled oscillator whose oscillation frequency is controlled according to the output voltage level of the low-pass filter and generates a reference clock, and a reference clock from the voltage controlled oscillator to the analog switch during the vertical blanking period of the video signal. and a selection circuit that inputs a clock pulse obtained by dividing the reference clock from the voltage controlled oscillator as an input comparison signal to the analog switch outside the vertical blanking period of the video signal. PLL circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990086390U JP2536973Y2 (en) | 1990-08-20 | 1990-08-20 | PLL circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990086390U JP2536973Y2 (en) | 1990-08-20 | 1990-08-20 | PLL circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0444692U true JPH0444692U (en) | 1992-04-15 |
| JP2536973Y2 JP2536973Y2 (en) | 1997-05-28 |
Family
ID=31818034
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990086390U Expired - Lifetime JP2536973Y2 (en) | 1990-08-20 | 1990-08-20 | PLL circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2536973Y2 (en) |
-
1990
- 1990-08-20 JP JP1990086390U patent/JP2536973Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2536973Y2 (en) | 1997-05-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0444692U (en) | ||
| JPH0466876U (en) | ||
| TW332950B (en) | PLL circuit and noise reduction | |
| JPS6333280U (en) | ||
| JPH0412763U (en) | ||
| JPH0253676U (en) | ||
| JP2600714Y2 (en) | Circuit for generating carrier signal and test signal of RF modulator | |
| JPS6327477Y2 (en) | ||
| JPH0446492U (en) | ||
| JPH0478828U (en) | ||
| JPH0434028U (en) | ||
| JPS5843043U (en) | frequency synthesizer | |
| JPS6438022U (en) | ||
| JPH03117946U (en) | ||
| JPH0467824U (en) | ||
| JPH0434027U (en) | ||
| JPH01103975U (en) | ||
| JPS61248676A (en) | Relaxation oscillator | |
| JPS6429174A (en) | Clock generation circuit | |
| JPH0375683U (en) | ||
| JPS6150346U (en) | ||
| JPH0386635U (en) | ||
| JPS6185934U (en) | ||
| JPS6438028U (en) | ||
| JPS62155528U (en) |