JPH0444485A - Time axis error correction device - Google Patents

Abstract

PURPOSE:To prevent generation of a velocity error caused by a switching point by replacing a horizontal scanning line including the switching point into a data of another horizontal scanning line through the use of a delay circuit and a switch. CONSTITUTION:The effect of a switching point in a time axis error correction device using an APC circuit appears only on one horizontal scanning line. Moreover, a position where the switching point appears is discriminated from a drum pulse. Thus, a switch 20 through which a signal delayed by one horizontal scanning period has been fed to a memory 3 so far is selected to give a signal not delayed to the memory 3 by using a mask control signal generated from an edge of the drum pulse. Thus, the write of the horizontal scanning line including the switching point is not caused in the memory 3. Thus, no switching point is included in a data subject to time axis correction processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a time axis error correction device for correcting a time axis error included in a video signal read from a recording medium such as a VTR.

[Prior Art] When there is a time axis error in the horizontal section of a video signal, the video signal is written into a memory using a clock that has an axis error at the same time, and is read out without a time axis error or with an O clock. It is possible to compensate for time axis errors.

FIG. 5 shows an example of a time-base error correction device that compensates for time-base errors in a video signal. In the figure, an input video signal is input to an A/D converter #N1 and A/D converted by a write clock synchronized with the input video signal generated by a write clock generation N2. After the A/D converted video signal is written to the memory 3 by the write clock,
The data is read out using a reference continuous clock that can be generated by the read clock generator 4, and converted into an analog signal by the D/A conversion H5. Normally, the read clock uses a fixed clock based on crystal oscillation and is stable with crystal oscillation accuracy, so the time axis correction ability generally depends on the accuracy of the read-in clock.

A write clock synchronized with the input signal, that is, a recessed clock whose phase varies depending on the time axis error, can be generated by an AFC circuit as shown in FIG. 6, for example.

That is, the horizontal synchronization signal is separated from the video signal by the synchronization separation circuit 6 and input to the AFC circuit 7. The AFC circuit 7 includes a phase comparator N8, a loop filter 9, a VCO 10,
It is composed of a PLL circuit consisting of a frequency divider 11,
VCOlo outputs a clock having the same time base error as the horizontal synchronization signal.

This clock writes the input video signal to memory,
By reading out a clock with no time axis error, it is possible to obtain a video signal without time axis error. However, since the loop band of the AFC circuit is determined by the time constant and frequency characteristics of the loop filter 9, the response speed cannot be increased in order to obtain stable performance, and it is not possible to follow high-speed temporal fluctuations.

Therefore, while the AFC circuit synchronizes the phase of the clock with the input signal by varying the oscillation frequency and phase according to the length of one horizontal scanning period, the APC circuit synchronizes the phase of the clock with the input signal. In recent years, lock generation circuits have been used that can synchronize with the phase within the phase.

The APC circuit is configured as shown in FIG. 7, for example.

The synchronization separation circuit 6 separates a horizontal synchronization signal from the input video signal and supplies it to the phase detection 112.

Depart! A clock signal with a fixed frequency outputted by the clock signal 1113 is input to the delay unit 14, and is delayed by a mutually different predetermined time to generate clock signals with a plurality of phases. These clock signals of multiple phases are input to the phase detection 812 and the phase selection N15.

The phase detection 1112 is connected to the synchronization separation circuit 6 and the delay &! Compare the phases of the signals input from 14 and compare the results! 1! (phase error) is output to the phase selector 15. Phase selection 1W1
5 selects and outputs the clock signal with the smallest phase error in accordance with the output of the phase detector 12.

As a result, as shown in FIG. 8, a clock signal synchronized with the horizontal synchronizing signal that is reset every time an edge of the horizontal synchronizing signal arrives can be generated.

Therefore, as shown in FIG. 9, by writing the signals of each line of the video signal into the memory in response to this clock signal, the time axis error can be corrected. In other words, if you write to the memory space while resetting at the edge of the synchronization signal, and read out at the reference clock while resetting every horizontal section, the signal after D/A conversion can be reproduced correctly (Figure 10). A and B).

Let us now consider the characteristics of time axis error correction in the AFC method and APC method. Figure 11 is an example of a circuit used for measurement of a time axis error correction device, and the variable delay line 16 has no time axis error. Bidet No. 48 is being supplied, and a sine wave of a single frequency that can be roughly output from the sine wave oscillator 17 is being supplied as a control signal. Therefore, the input video signal with no time axis variation is sinusoidally expanded or contracted in the time axis direction by the variable delay line 16, and this is supplied to the time axis error correction device 18. Then, by finding the fluctuation component (sine wave component) ratio between the input and output of the time axis error correction device i18, the correction ability of the time axis error correction device can be measured.

FIG. 12 shows the AFC circuit measured using this method and A
It is a graph showing the time axis error correction ability of the PC circuit. In the figure, the horizontal axis represents the fluctuating component frequency, and the vertical axis represents the fluctuating component correction ability (suppression ratio) by the time axis error correction device. That is, if the vertical axis is less than OdB, it means that there is a time axis error correction ability, and if it is larger than OdB, it means that the time axis error correction ability is insufficient. The solid line indicates the time axis error correction ability using the APC circuit, and the dotted line indicates the time axis error correction ability using the AFC circuit.

As a result 1, in the low frequency component below around Hz, AP
It is understood that the time axis error correction device using the C circuit has a better time axis error improvement effect by about 7 to 8 dB than the case using the AFC circuit, and has a correction ability up to around 3 KIz.

On the other hand, a time axis error correction device using an AFC circuit is approximately I
It is understood that for frequency components higher than KH2, the time axis error cannot be fully corrected, and the characteristics are inferior to those using the APC circuit.

In general, the fluctuation component tends to become less visually noticeable as the frequency becomes higher, and the fluctuation component itself tends to decrease as the frequency becomes higher.

[Problems to be Solved by the Invention] However, even with a time axis error correction device such as an APC circuit, velocity errors that occur at switching points in consumer VTR formats and that expand and contract greatly during one horizontal scanning section cannot be avoided. cannot be followed. In addition, the switching point constantly changes with a convergence of several μS due to table tension, low frequency jitter, etc., and the time axis error of the horizontal scanning line signals before and after the horizontal scanning section including the switching point is sufficiently corrected. Errors in horizontal scanning lines, including switching points, were particularly visually noticeable.

For this reason, by setting the switching point on a horizontal scanning line other than the effective scanning line on the monitor screen, the disturbance in the image caused by the switching point was made invisible, but on large monitor screens, the range of effective scanning lines expands. , disturbances caused by switching points have become visible.

This situation is shown in FIGS. 13 to 15.

That is, as shown in FIG. 13, noise appears in the reproduced video signal in synchronization with the edge (switching point) of the drum pulse. As shown in FIG. 14, the error component due to the switching point located at the bottom of the screen is not removed even by the time axis error correction device using the APC circuit, and is output as shown in FIG. 15.

Means for Solving Problem E] The time axis error correction device of the present invention converts the input video signal into A/
A/D converted video (g
a delay circuit that delays the signal by at least one horizontal scanning period in units of one horizontal scanning period, and a horizontal scanning period in which the switching point is included in response to the first horizontal synchronization signal after generation of the drum pulse instructing head switching. A mask control signal generator that generates a mask control signal (No. 3) and a signal that does not include a switching point are selected from the signals delayed and non-delayed by a delay circuit according to the mask control signal and supplied to the memory. The invention is characterized in that it includes a switch.

[Operation] The time axis error correction device configured as described above is provided with a switch that selects either a delayed signal or a non-delayed signal, so that a horizontal scanning line including a switching point is generated. In this case, for example, a horizontal scanning line before IH that does not include this can be output. Moreover, since the horizontal scanning line where the switching point occurs is obtained from the drum pulse, no special switching point detection means is required.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

Note that the same reference numerals are given to the parts corresponding to those in the conventional case, and the explanation thereof will be omitted as appropriate.

FIG. 1 is a block diagram showing the configuration of an embodiment of the time axis error correction device of the present invention.

The input video signal is A/D converted in A/D conversion N1 using a write clock phase synchronized with the synchronization signal generated by the APC circuit 21. The A/D converted video signal is supplied to one terminal a of the switch 20, and is also supplied to the other terminal a of the switch 20 via an IH delay circuit 19.

In addition to being supplied to the APC circuit 21, the output of the synchronization separation circuit 6 is also supplied as a trigger (g) to a mask control signal generator M23.The mask control signal generator N23 receives drum pulses from a controller (not shown). Then, a mask control signal is generated which is at H level for one horizontal scanning period from the time when the first horizontal synchronizing signal is generated after the drum pulse is generated.The mask control signal becomes the switching side m signal of the switch 20.

When the mask control signal is at H level, the switch 20
selects the terminal ba to supply the undelayed video signal to the memory 3, and when the mask control signal is at L level, selects the terminal a side so that the IH-delayed video signal is supplied to the memory 3.

The horizontal synchronization signal separated by the synchronization separation circuit 6 is applied to the memory 3 as a horizontal reset pulse.

Next, the operation of the time axis error correction device having the above configuration will be explained.

First, in a time axis error correction device using an APC circuit, since each horizontal scanning line is reset by a horizontal synchronizing signal on the memory, the switching point affects only one horizontal scanning line. Furthermore, since the switching point of the head is synchronized with the drum pulse of the VTR, the position where the switching point appears can be determined from the drum pulse.

Therefore, the switch 20, which had been supplying a signal delayed by one horizontal scanning period to the memory 3, is switched to the undelayed signal by the mask control signal which becomes H level at the time when the synchronization signal is generated immediately after the edge of the drum pulse is generated. is switched to supply the memory 3. In this way, the horizontal scanning line including the switching point will not be written into the memory 3, and the data after time axis correction processing will no longer include the switching point.

FIG. 2 is a timing chart showing signal waveforms at each part of the configuration shown in FIG. As shown in FIG. 2A, it is assumed that a switching point is included in n lines of the input video signal. The A/D converted data is shown in Figure B.
The data roughly delayed by IH is shown in C of the same figure. Normally, the switch 20 is configured to select the IH-delayed output C.

and the switching point and drum pulse (Fig. 2D)
), the switch 20 is controlled by the mask control signal (FIG. 2 F) for one horizontal scanning period from the horizontal synchronization signal (FIG. 2 E) immediately after the drum pulse generated on the nth line of the input signal. By switching and selecting the undelayed video signal B, the switching point does not appear in the output of the switch 20 (FIG. 2 G), which could not be removed even by a conventional time axis error correction device using an APC circuit. It is possible to prevent velocity errors from occurring.

Note that in the above embodiment, the signal is replaced with the signal one line after the horizontal scanning line that includes the switching point, but the A/
By inserting a one-line delay circuit before the D conversion 11, it is also possible to replace the signal with one line earlier in analog fashion.

Also, use two IH delay circuits to create a 2H delay circuit,
The average of the input signal g and the signal delayed by 2H is calculated as the first
It can be connected to the terminal side of the switch 20 in the figure. In this way, the horizontal scanning line including the switching point can be replaced by the average of the horizontal scanning lines before and after it.

FIG. 3 is a timing chart showing the waveforms of each part at that time.

The waveform in the figure shows a video signal delayed by 2H, and during the period when the mask control signal E is at H level, the average F of the current input signal B and the video delayed by 2H (number 8) is output. By doing so, not only is there no switching point, but also a decrease in vertical M image quality can be prevented.

Furthermore, if the drum pulse is delayed by one horizontal scanning interval, the delayed output is used as a new drum pulse for head switching, and a mask control signal is created using the drum pulse before the delay, the switching point can be eliminated. This situation is shown in FIG.

That is, the drum pulse G is generated on the (n-1)th line, and by delaying it by IH, the switching point comes on the nth line. If the switch 20 is controlled so that the signal supplied to the A/D converter when the nth line is input is the signal before IH, the data F sent to the A/D converter N1 does not include switching points.

[Effects of the Invention] As described above, according to the time axis error correction device of the present invention, a horizontal scanning line including a switching point is replaced with data of another horizontal scanning line by using a delay circuit and a switch. It is possible to prevent velocity errors caused by switching points from occurring.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the time axis error correction device of the present invention, FIGS. 2 to 4 are timing charts illustrating the operation of the time axis error correction device of the present invention, and FIG. 5 is a block diagram showing the configuration of an example of a general time axis error correction device, FIG. 6 is a block diagram showing the configuration of an example of an AFC circuit, FIG. 7 is a block diagram showing the configuration of an example of an APC circuit, and FIG. The figure is a timing chart explaining the operation of the example in Figure 7, Figure 9 is an explanatory diagram of the memory explaining the operation of time axis error correction, and Figures 10 A to 10 are concepts representing the time axis error on the monitor screen. Figure 111M is a block diagram showing the configuration of an example of the ability measuring device of the time axis error correction device.
Figure 2 shows a time base error correction device using an AFC circuit and APC.
A graph comparing the time axis correction ability with a time axis error correction device using a circuit, Fig. 13 is a timing chart for explaining the timing of switching points and drum pulses, Figs. 14 and 15 are FIG. 3 is a conceptual diagram showing how switching points appear on a monitor screen. 1...A/D conversion 113...1 memo 4...Read clock generation circuit, 5...t)/A conversion IL 1
9... IH delay circuit, 21... APC circuit, 23...
...Mask control signal generation inspection. Patent applicant: Victor Japan Co., Ltd.

Claims (1)

[Claims] A time axis error correction device for a VTR that performs time axis error correction by A/D converting an input video signal and writing it into a memory using a write clock phase-synchronized with the input video signal, and reading from the memory using a read clock. hand,
a delay circuit that delays the A/D-converted video signal by at least one horizontal scanning period in units of one horizontal scanning period; and a switching point in response to the first horizontal synchronizing signal after generation of a drum pulse instructing head switching. a mask control signal generator that generates a mask control signal by determining a horizontal scanning section including a mask control signal; and a signal that does not include a switching point among the signals delayed and non-delayed by the delay circuit according to the mask control signal; A time axis error correction device comprising: a switch for selecting a signal and supplying the selected signal to the memory.