JPH0444219A - Semiconductor substrate - Google Patents

Semiconductor substrate

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Publication number
JPH0444219A
JPH0444219A JP14864090A JP14864090A JPH0444219A JP H0444219 A JPH0444219 A JP H0444219A JP 14864090 A JP14864090 A JP 14864090A JP 14864090 A JP14864090 A JP 14864090A JP H0444219 A JPH0444219 A JP H0444219A
Authority
JP
Japan
Prior art keywords
film
substrate
gaas
compressive stress
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14864090A
Other languages
Japanese (ja)
Other versions
JP2862018B2 (en
Inventor
Masami Tachikawa
太刀川 正美
Yoshinori Nakano
中野 好典
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP14864090A priority Critical patent/JP2862018B2/en
Publication of JPH0444219A publication Critical patent/JPH0444219A/en
Application granted granted Critical
Publication of JP2862018B2 publication Critical patent/JP2862018B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To obtain a desired film on which a compressive stress is applied or from which a tensile stress is reduced on a substrate so as to obtain a high- quality film having a low dislocation density by constituting the substrate by utilizing a difference in coefficient of thermal expansion between materials. CONSTITUTION:A silicon nitride (SiNx) film having a film thickness of about 1,000 A is partially formed on the surface of an Si substrate 1. After forming the film, a silicon oxide (SiO2) film 3 having a film thickness of about 5mum is formed on the substrate including the silicon nitride film 1. After removing part of the SiO2 film 3 by partial etching of the SiNx film is exposed ((c), Fig. 1), only the SiNx film is removed by selective etching. Then a GaAs film 4 is selectively formed by vapor growth on the exposed part of the Si substrate 1. Numeral 5 in the figure denotes hollow (cavity) section. Since a relation alpha3>alpha1>alpha2 exists among the coefficients of thermal expansion of Si, SiO2, and GaAs, such a relation that the length of the upper layer is longer than that of the lower layer can be obtained when the length are appropriately selected. Under such condition, the upper layer receives a compressive stress and, therefore, a GaAs layer suffering a compressive stress can be obtained.

Description

【発明の詳細な説明】 E産業上の利用分野〕 本発明は、QaAs、InPあるいは81などの半導体
基板および同半導体基板上に形成した単体、化合物ある
いは混晶からなる基板の構造に関する。
DETAILED DESCRIPTION OF THE INVENTION E-INDUSTRIAL APPLICATION FIELD The present invention relates to a semiconductor substrate made of QaAs, InP or 81, and a structure of a substrate made of a single substance, a compound, or a mixed crystal formed on the semiconductor substrate.

〔従来の技術] 物質の特性は、その物質に掛かっている応力に大きく依
存する。例えば、Si基板上のGaAs膜等は、Slと
GaAs0熱膨張係数差により、GaAs膜に引張り応
力が入っており、バンドギャップが応力のないバルクG
aAs等より小さくなっていることがフォトルミネッセ
ンスの測定等から知られている。
[Prior Art] The properties of a substance largely depend on the stress applied to the substance. For example, in a GaAs film on a Si substrate, tensile stress is applied to the GaAs film due to the difference in thermal expansion coefficient between Sl and GaAs0, and the band gap is different from that of the stress-free bulk G.
It is known from photoluminescence measurements that it is smaller than aAs or the like.

また近年、歪超格子などが使われている。例えばInP
系歪起歪超格子いては、圧縮応力下において、InGa
AsP等の半導体の価電子帯構造を変化させ、有効質量
を小さくしたりして、高効率のレーザダイオード(LD
)が作製されている。
In recent years, strained superlattices have also been used. For example, InP
In the system strain-induced superlattice, under compressive stress, InGa
By changing the valence band structure of semiconductors such as AsP and reducing the effective mass, we can create highly efficient laser diodes (LDs).
) has been created.

〔発明が解決しようとする課題] 他方、上記のGaAs/Si基板の例においては、熱応
力の緩和のために、基板の一部のみに成長させる選択成
長が行われている。
[Problems to be Solved by the Invention] On the other hand, in the above-mentioned example of the GaAs/Si substrate, selective growth is performed to grow only on a part of the substrate in order to alleviate thermal stress.

この方法により、熱応力を減少させることは可能であっ
たが、単にSi基板の一部に成長させるのみでは、熱応
力を完全にゼロにすることは不可能であった。
Although it was possible to reduce thermal stress using this method, it was impossible to completely eliminate thermal stress by simply growing it on a portion of the Si substrate.

本発明の目的は、熱膨張係数の違いを利用して、目的と
する任意の圧縮あるいは引張り応力を有する膜(物質)
を提供することにある。
The purpose of the present invention is to create a film (substance) having a desired compressive or tensile stress by utilizing the difference in thermal expansion coefficients.
Our goal is to provide the following.

〔課題を解決するための手段〕[Means to solve the problem]

上記の課題を解決するために、本発明の半導体基板は、
基板となる第1の物質(基板というのは、第1の物質か
らなる基板のほか、所定の基板上に形成された第1の物
質からなる層の場合も含む)と、上記第1の物質上に形
成された上記第1の物質とは異なる第2の物質からなる
薄膜と、上記薄膜の一部が上記第1の物質の表面まで除
去された部分に選択成長させた第3の物質で構成される
半導体基板において、上記第2の物質と上記第1の物質
の間で上記第3の物質の近傍が中空または第4の物質で
構成されていることを特徴とする。
In order to solve the above problems, the semiconductor substrate of the present invention includes:
A first substance that serves as a substrate (a substrate includes not only a substrate made of a first substance but also a layer made of a first substance formed on a predetermined substrate), and the first substance A thin film made of a second substance different from the first substance formed on the top, and a third substance selectively grown on the part of the thin film where a part of the thin film is removed to the surface of the first substance. In the semiconductor substrate constructed according to the present invention, the vicinity of the third material between the second material and the first material is hollow or is made of a fourth material.

(作用〕 本発明の半導体基板では、上記第2の物質と上記第1の
物質の間で上記第3の物質の近傍を中空または第4の物
質で構成し、かつ上記第1、第2、第3の物質の熱膨張
係数差およびその形状を制御することにより、所望の応
力を有する第3の物質を得ることができ、転位密度を低
減することができる。
(Function) In the semiconductor substrate of the present invention, the vicinity of the third material is formed between the second material and the first material, and the first, second, and By controlling the difference in thermal expansion coefficient of the third material and its shape, it is possible to obtain a third material having a desired stress and to reduce the dislocation density.

〔実施例] 実施例 1 第1図(a)〜(e)は、本発明による実施例1として
、81基板上に圧縮応力を有するGaAs膜を形成する
例を示す工程断面図である。
[Example] Example 1 FIGS. 1(a) to 1(e) are process cross-sectional views showing an example of forming a GaAs film having compressive stress on an 81 substrate as Example 1 according to the present invention.

まず、Si基板1上の一部に膜厚約1000人の窒化シ
リコン(S i N、)膜2を形成する(第1図(a)
)。
First, a silicon nitride (S i N) film 2 with a thickness of about 1000 nm is formed on a part of the Si substrate 1 (see FIG. 1(a)).
).

その後、膜厚的5μmの酸化シリコン(S i O,)
膜3を形成する(第1図(b))。
After that, silicon oxide (S i O,) with a film thickness of 5 μm was deposited.
A film 3 is formed (FIG. 1(b)).

その後、SiO,Jlj3の一部を部分的にエツチング
により除去し、SiN、膜2を露出させ(第1図(c)
)、次いで、S IN xl!2のみを選択的にエツチ
ングにより除去する(第1図(d))。
Thereafter, a part of SiO and Jlj3 was partially removed by etching to expose SiN and film 2 (see Fig. 1(c)).
), then S IN xl! 2 is selectively removed by etching (FIG. 1(d)).

その後、この部分的に露出した81基板l上に、気相成
長法によりGaAs層4を選択成長させる(第1図(e
))。5は中空(空洞)部である。
Thereafter, a GaAs layer 4 is selectively grown on this partially exposed substrate 81 by vapor phase growth (Fig. 1(e)
)). 5 is a hollow (cavity) part.

選択成長したGaAs層4には圧縮の応力が働いていた
。次に、第1図(e)を用いて、圧縮応力が働く理由に
ついて説明する。第1図(e)に各層の横の長さを示し
た<Q、  Ω1、Q、)。ここで、Q、はエツチング
除去前のSiNx膜2、Q5は中空部分5、Q、は選択
成長したGaAs層4のそれぞれ横の長さを示す。選択
成長によりこれらは産着しているため、Q、=Q、x2
+Ω、となっている。成長温度は630℃である。その
後、通常動作させる室温30℃に取り出すと、各層の長
さはそれぞれの熱膨張係数αI、α2、α3に従って減
少する。ここで、α1はSl、α、はS10いα、はG
aAsの熱膨張係数を示し、α、=2.6X10−” 
(”C−’) 、α、 =0.6 X 10−“(℃−
“)、α、=sjxlo−” (”C−“)である、も
し仮に、上層のGaAs層、Sin、膜を下層のSi基
板を分離したとする。また、ΔTを成長温度と室温との
温度差とすると、 上層の長さは、Q、X(1−α2×Δ丁)×2+Q、X
 (1−α3×△T) 下層の長さは、Q、X(1−α1×ΔT)となり、上層
の長さ一下層の長さは、 Q、×(−α2×△T) X2+ff、X (−α3×
△T) −Q、X (−αl×Δ丁) =(α1xQ、−(α2X12.X2+α3xff、)
)×Δ丁 =<2Q、Cα1−α、)+Q、(α1−α、))×Δ
T となる、3i、SiO,、GaAsの熱膨張係数にはα
3〉α1〉α2の関係があるので、Q、とρ、を適当に
選ぶことにより、上層の長さ〉下層の長さの関係を得る
ことができる。この条件において、上層と下層が密着し
た本実施例においては、上層が圧縮応力を受け、すなわ
ち、圧縮応力を有するGaAs層が得られることが理解
できる1本実施例では、Q、=15μn、 Q、=10
μmである。
Compressive stress was acting on the selectively grown GaAs layer 4. Next, the reason why compressive stress acts will be explained using FIG. 1(e). Figure 1(e) shows the horizontal length of each layer (<Q, Ω1, Q,). Here, Q represents the horizontal length of the SiNx film 2 before etching removal, Q5 represents the hollow portion 5, and Q represents the horizontal length of the selectively grown GaAs layer 4. Since these are produced by selective growth, Q, = Q, x2
+Ω. The growth temperature is 630°C. Thereafter, when the layer is taken out to the normal operating room temperature of 30° C., the length of each layer decreases according to the respective thermal expansion coefficients αI, α2, and α3. Here, α1 is Sl, α, is S10, α, is G
Indicates the thermal expansion coefficient of aAs, α, = 2.6X10-”
("C-'), α, =0.6 X 10-"(℃-
), α,=sjxlo−” (“C−”). Suppose that the upper GaAs layer, the Si film, and the lower Si substrate are separated. Also, if ΔT is the temperature difference between the growth temperature and room temperature, the length of the upper layer is Q,
(1-α3×△T) The length of the lower layer is Q, (−α3×
△T) -Q,
) x Δ D = <2Q, Cα1-α, )+Q, (α1-α, )) x Δ
The coefficient of thermal expansion of 3i, SiO, GaAs is α
Since there is a relationship of 3>α1>α2, by appropriately selecting Q and ρ, the relationship of upper layer length>lower layer length can be obtained. Under these conditions, it can be understood that in this example where the upper layer and the lower layer are in close contact with each other, the upper layer receives compressive stress, that is, a GaAs layer having compressive stress is obtained.In this example, Q, = 15 μn, Q. ,=10
It is μm.

また、Q a A s膜4の転位密度を測定したところ
、lO’an−”と高品質膜が得られていた。これは、
従来のGaAs/Siでは、引張り応力により、成長温
度からの冷却過程において、10″CIII””の転位
が導入されていたのに対して、本実施例においては、圧
縮応力となって、その冷却過程の転位導入が無くなった
ことによるものである。
In addition, when the dislocation density of the Q a As film 4 was measured, it was found that a high quality film was obtained as 1O'an-''.
In conventional GaAs/Si, 10"CIII"" dislocations were introduced during the cooling process from the growth temperature due to tensile stress, whereas in this example, the dislocations were introduced due to compressive stress during the cooling process. This is due to the elimination of dislocation introduction in the process.

実施例 2 次に、本発明による実施例2として、InP基板上にI
nP膜を形成する例について述べる。第2図は、実施例
2の構造を示す断面図である。
Example 2 Next, as Example 2 according to the present invention, I was deposited on an InP substrate.
An example of forming an nP film will be described. FIG. 2 is a sectional view showing the structure of Example 2.

本実施例の構造は、実施例1において、Si基板の代わ
りにInP基板6を、またG a A s層の代わりに
InP層7を用いたものであり、その作製工程は実施例
1と同じである。
The structure of this example uses the InP substrate 6 instead of the Si substrate and the InP layer 7 instead of the GaAs layer in Example 1, and the manufacturing process is the same as Example 1. It is.

実施例1と同様に、上層のInP層7は圧縮応力を受け
ていた。また、この上層のInP層7をInP層で挾ま
れたI n G a A s活性層からなるLDのDH
(ダブルへテロ構造)としたところ、圧縮応力を受けた
ことによりキャリヤの寿命が長くなり、その発光強度は
増加していた。
As in Example 1, the upper InP layer 7 was under compressive stress. In addition, the upper InP layer 7 is the DH of an LD consisting of an InGaAs active layer sandwiched between InP layers.
(double heterostructure), the lifetime of the carriers became longer due to the compressive stress, and the emission intensity increased.

実施例 3 第3図は、実施例3の構造を示す断面図である。Example 3 FIG. 3 is a sectional view showing the structure of Example 3.

実施例1.2では、31基板lとSi○、膜3の間に中
空部5を設けていた。本実施例においては、この中空部
を軟化温度の低い(400℃)低融点ガラス8を用いた
。作製工程は、SiNx膜の代わりに低融点ガラス8を
用い、はぼ実施例1と同様であるが、実施例1における
S i NJi除去の工程は省略した。
In Example 1.2, a hollow portion 5 was provided between the 31 substrate 1 and the Si◯ film 3. In this example, a low melting point glass 8 having a low softening temperature (400° C.) was used for this hollow portion. The manufacturing process was the same as in Example 1, using low melting point glass 8 instead of the SiNx film, but the step of removing SiNJi in Example 1 was omitted.

本実施例の場合においても、冷却過程での熱膨張係数差
により生じる歪は、低融点ガラス8に吸収され、QaA
s層4には圧縮応力が働き、実施例1と同様の効果があ
った。本実施例の場合、低融点ガラスの選択エツチング
の工程を省略できる利点がある。さらには、最終形態に
おいて中空部の無い、従って、信頼性の高い基板が作製
できるという利点がある。
In the case of this embodiment as well, the strain caused by the difference in thermal expansion coefficient during the cooling process is absorbed by the low melting point glass 8, and the QaA
Compressive stress acted on the s-layer 4, and the same effect as in Example 1 was obtained. In the case of this embodiment, there is an advantage that the step of selectively etching the low melting point glass can be omitted. Furthermore, there is an advantage that a highly reliable substrate can be produced that has no hollow portion in its final form.

実施例 4 第4図(a)〜(d)は、実施例4の工程断面図である
Example 4 FIGS. 4(a) to 4(d) are process cross-sectional views of Example 4.

まず、InP基板6上の一部にS i O,膜3′をA
rスパッタ無しの条件でつける(第4図(a))。
First, a SiO film 3' is deposited on a part of the InP substrate 6.
It is attached under the condition of no r-spatter (Fig. 4(a)).

その上に、今度はArスパッタを行い、InP基板6の
表面処理をしながら5101膜3をっける(第4図(b
))。このようにして形成すると、後で示すように付着
力が強くなる。
On top of that, Ar sputtering is performed to form a 5101 film 3 while surface-treating the InP substrate 6 (see Fig. 4 (b).
)). When formed in this way, the adhesion becomes stronger as will be shown later.

次に、前の実施例と同様に、S10.膜3の一部をエツ
チングする(第4図(C))。できあがった5101M
は、全て同一の膜であるが、InP基板6との界面を考
えると、図中、細線で示した箇所と太線で示した箇所の
付着力が異なっている(太線の方が付着力が強い)。
Next, as in the previous embodiment, S10. A part of the film 3 is etched (FIG. 4(C)). The completed 5101M
are all the same film, but when considering the interface with the InP substrate 6, the adhesion force is different between the thin line and the thick line in the figure (the thick line has stronger adhesion). ).

次に、この部分的にn呂したInP基板6上にInP層
7を選択成長させる。
Next, an InP layer 7 is selectively grown on this partially wetted InP substrate 6.

このようにすると、InPの成長温度(650’C)に
おいては、Arスパッタ無しの箇所(細線)はSin、
膜3ヒInP基板6との間の結合が切れる。太線の箇所
は結合したままである。
In this way, at the InP growth temperature (650'C), the areas without Ar sputtering (thin lines) are
The bond between the film 3 and the InP substrate 6 is broken. The parts marked with thick lines remain connected.

応力などの結果は実施例2と同じである。また、でき上
がった構造は、普通の選択成長の場合と同じである。
Results such as stress are the same as in Example 2. Furthermore, the resulting structure is the same as in the case of ordinary selective growth.

以上、本発明を前記実施例に基づいて具体的に説明した
が、本発明は前記実施例に限定されるものではなく、そ
の要旨を逸脱しない範囲において種々変更可能であるこ
とは勿論である。例えば本発明は、上記実施例の他、Z
 n S S e / S i、G a P / S 
i、r n P / S i、AlGaAs/Si、I
nGaAsP/Si、GaAs/Geなどの、単結晶基
板上のm−v (El−v+)化合物半導体あるいはf
II−V (IT−VI)混晶半導体においても同様の
効果が得られる。また、ZnSSe/GaAsなどの族
の異なるヘテロエビ基板、A I G a A s /
 G a A s、I nGaAs P/InPなどの
同族へテロエビ基板においても同様の効果が得られる。
Although the present invention has been specifically explained based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various changes can be made without departing from the gist thereof. For example, in addition to the above embodiments, the present invention also provides Z
n S S e / S i, G a P / S
i, r n P/S i, AlGaAs/Si, I
m-v (El-v+) compound semiconductor or f on a single crystal substrate such as nGaAsP/Si, GaAs/Ge, etc.
Similar effects can be obtained with II-V (IT-VI) mixed crystal semiconductors. In addition, heterogeneous substrates of different families such as ZnSSe/GaAs, A I Ga As /
Similar effects can be obtained with homologous heterogeneous substrates such as GaAs and InGaAsP/InP.

GaAs/GaAs、InP層 I n Pなどのホモ
ニビにおいても、圧縮応力を有するQaAs膜、InP
Jljが得られることは勿論のこと、歪InP層デバイ
ス、歪GaAs層デバイスなどに応用できるなどの効果
を有する。
GaAs/GaAs, InP layer I n P, etc. homo-nibi, QaAs film with compressive stress, InP
Not only can Jlj be obtained, but it also has the advantage of being applicable to strained InP layer devices, strained GaAs layer devices, and the like.

[発明の効果] 上記のように、本発明の半導体基板によれば、基板上に
圧縮応力のかかったあるいは引張り応力の減少した所望
の膜が得られ、低転位密度の高品質膜が得られる。
[Effects of the Invention] As described above, according to the semiconductor substrate of the present invention, a desired film with compressive stress or reduced tensile stress can be obtained on the substrate, and a high-quality film with a low dislocation density can be obtained. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(e)は、本発明の実施例1の半導体基
板を示す工程断面図、第2図は、実施例2の半導体基板
を示す断面図、第3図は、実施例3の半導体基板を示す
断面図、第4図(a)〜(d)は、実施例4の半導体基
板を示す工程断面図である。 l・・・Si基板 2・・・SiNx膜 3・・・Sin、膜 4・・・GaAs膜 5・・・中空部 6・・・InP基板 7・・・InP膜 8・・・低融点ガラス 特許出願人 日本電信ii話株式会社
1(a) to (e) are process cross-sectional views showing a semiconductor substrate according to Example 1 of the present invention, FIG. 2 is a cross-sectional view showing a semiconductor substrate according to Example 2, and FIG. 3 is a process cross-sectional view showing a semiconductor substrate according to Example 2. FIGS. 4(a) to 4(d) are process sectional views showing the semiconductor substrate of Example 4. FIGS. l...Si substrate 2...SiNx film 3...Sin, film 4...GaAs film 5...hollow part 6...InP substrate 7...InP film 8...low melting point glass Patent applicant Nippon Telegraph II Inc.

Claims (1)

【特許請求の範囲】[Claims] 1、基板となる第1の物質と、上記第1の物質上に形成
された上記第1の物質とは異なる第2の物質からなる薄
膜と、上記薄膜の一部が上記第1の物質の表面まで除去
された部分に選択成長させた第3の物質で構成される半
導体基板において、上記第2の物質と上記第1の物質の
間で上記第3の物質の近傍が中空または第4の物質で構
成されていることを特徴とする半導体基板。
1. A first material serving as a substrate, a thin film formed on the first material and made of a second material different from the first material, and a part of the thin film made of the first material. In a semiconductor substrate composed of a third material selectively grown in a portion removed to the surface, the vicinity of the third material is hollow or a fourth material is formed between the second material and the first material. A semiconductor substrate characterized by being composed of a substance.
JP14864090A 1990-06-08 1990-06-08 Semiconductor substrate Expired - Fee Related JP2862018B2 (en)

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JPH0444219A true JPH0444219A (en) 1992-02-14
JP2862018B2 JP2862018B2 (en) 1999-02-24

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014212232A (en) * 2013-04-19 2014-11-13 富士通株式会社 Ge-BASED NANOWIRE OPTICAL ELEMENT AND METHOD OF MANUFACTURING THE SAME

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014212232A (en) * 2013-04-19 2014-11-13 富士通株式会社 Ge-BASED NANOWIRE OPTICAL ELEMENT AND METHOD OF MANUFACTURING THE SAME

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