JPH07321051A - Method of manufacturing compound semiconductor device, and semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device provided with a nitrogen based III-V group mixed crystal semiconductor having no antiphase boundary on an Si substrate. CONSTITUTION:A surface light emitting laser diode composed of an n type GaN 0.03, P 0.97 buffer layer 15, an n-type semiconductor multilayer film mirror 16, an undoped active layer 18, etc., is arranged on an n type Si substrate 10. This mixed crystal semiconductor shows no antiphase boundary. On the other hand, an Si electronic element comprising a drain electrode 12, a source electrode 13, etc., is arranged on the same substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor device having a structure in which a compound semiconductor is arranged on a Si substrate, a method for manufacturing the same, and a semiconductor device having such a structure.

[0002]

2. Description of the Related Art In the Si semiconductor technology, from transistor to I
It has been developed into C (integrated circuit) and VLSI (very large scale integrated circuit), and it is expected that the scale of integration will continue to increase. In recent years, as the scale of integration increases, it is becoming more feared that the operating speed is limited by the wiring delay of electric signals. As a countermeasure, signal connection by light is drawing attention. An important basic technology for achieving this is a technology for integrally forming Si and a compound semiconductor.

Conventionally, the following two means have been mainly studied as means for integrally forming a compound semiconductor on a Si substrate. One is, for example, Material Research Society Procedural Volume 116 (Material Research Society Pittsburgh 1988) (Mat.
er. Res. Soc. Pro. Vol. 11
6 (Mater. Res. Soc., Pitts
Burgh, 1988)).
This is a so-called superheteroepitaxy method in which a compound semiconductor such as As or InP is epitaxially grown. The other is Applied Physics Letters 62.
Volume, 1038-1040 (1993) (Appl. P.
hys. Lett. Vol. 62, pp. 1038-1
040 (1993)) is a direct bonding method in which a compound semiconductor such as GaAs or InP is bonded to a single crystal Si substrate by heat treatment.

Further, as a new material capable of lattice matching with a Si substrate, III-V containing at least nitrogen as a Group V element
Group mixed crystal semiconductors have been reported, and a method of epitaxially growing this nitrogen-based III-V group mixed crystal semiconductor on a Si substrate has been proposed (Japanese Patent Laid-Open No. 1-211912).

On the other hand, the compound semiconductor substrate is more expensive than the semiconductor substrate made of Si or the like. Therefore, it is also considered to form the compound semiconductor element on the inexpensive substrate made of Si or the like by the same method as described above. There is.

[0006]

The above-mentioned conventional superheteroepitaxy method and direct junction method are methods of integrally forming compound semiconductors having different lattice constants on a single-crystal Si substrate by epitaxial growth or bonding, so that the lattice mismatch is caused. Occurs, and misfit dislocations inevitably occur in the crystal near the interface between Si and the compound semiconductor, and thermal strain occurs due to the difference in thermal expansion coefficient between silicon and the compound semiconductor during the cooling process after the high temperature process of epitaxial growth or bonding. However, there was a problem that the generated misfit dislocation migrates and propagates. Further, there is a problem that the reliability of the device is low because the crystal defects move and propagate even during the operation of the compound semiconductor device manufactured on the Si substrate. Therefore, S
A compound semiconductor device having a structure in which a compound semiconductor element is provided on an i substrate and an optoelectronic integrated circuit (OEIC) in which a silicon element and a compound semiconductor element are monolithically integrated have not yet been put to practical use.

Further, the above-mentioned conventional nitrogen-based III-V group mixed crystal semiconductor can be lattice-matched with the Si substrate by selecting a mixed crystal composition, and misfit dislocations can be prevented so that a high quality crystal can be obtained. Although expected to be obtained, when a nitrogen-based III-V group mixed crystal semiconductor, which is a polar crystal, is epitaxially grown on Si, which is a non-polar crystal, another crystal defect called an antiphase boundary is generated. There was a problem.

That is, when a group III-V semiconductor is epitaxially grown on a Si substrate, a group III atom--group V atom--group III atom--group V atom and a group V atom--group III atom--group V atom-- A region (domain) is formed along with the group III atom, and a portion (group) along with the group III atom-group III atom or group V atom-group V atom is generated at the boundary (bandary) where these domains collide. III-V semiconductor is III
It becomes a semiconductor for the first time when group atoms and group V atoms are alternately arranged. Therefore, group III atom-group III atom or group V atom-V
The part aligned with the group atoms, that is, the part in which the arrangement of atoms (phase) is wrong, becomes a crystal defect and is called an antiphase boundary.

Since the thermal expansion coefficient difference between Si and the nitrogen-based III-V group mixed crystal semiconductor is as large as 2 × 10 ^-6 / ° C. or more, thermal strain occurs in the cooling process after the epitaxial growth and crystal defects occur. And it moves and propagates. Furthermore, Si
Since the crystal defects move and multiply even during the operation of the compound semiconductor device formed on the substrate, this antiphase boundary causes a problem in the life of the nitrogen-based III-V group mixed crystal semiconductor device formed on Si. Let

In general, in order to eliminate the anti-phase boundary, the plane orientation of the Si substrate should be (100), (11
A tilt substrate such as 0) or (111) deviated from the normal direction by several degrees or more is used. However, this method cannot completely eliminate the anti-phase boundary and requires a thick buffer layer to achieve single domain. Furthermore, the use of tilted substrates imposes restrictions on the design of Si electronic devices.

A first object of the present invention is to provide a compound semiconductor device having a structure in which a nitrogen-based III-V group mixed crystal semiconductor having no antiphase boundary is provided on a Si substrate. A second object of the present invention is to provide a method for manufacturing such a compound semiconductor device. A third object of the present invention is to provide a semiconductor device in which Si elements are integrated in such a compound semiconductor device.

[0012]

In order to achieve the first object, the compound semiconductor device of the present invention is a III-V compound containing nitrogen as a group V element, which has no anti-phase boundary on an Si substrate. Group III-V semiconductors are arranged and the III-V
A compound semiconductor element is provided on a group mixed crystal semiconductor.

III-V containing nitrogen as the group V element
A group mixed crystal semiconductor is one that is lattice-matched to Si by containing nitrogen, and a group V element is composed of nitrogen and another element. On the other hand, the group III element may be one element or two or more elements. For example, it is a compound semiconductor such as GaNP, GaNAs, or InNP. These mixed crystal semiconductors are not lattice-matched with Si over the entire composition range, but rather with GaN _x
In P _1-x , x is 0.03, and in GaN _y As _1-y , y is 0.
Lattice matching is performed at 19. Even if x and y are slightly deviated from this value, that is, if this value is substantially this value, lattice matching with Si is practically achieved. In this specification, such a III-V group mixed crystal semiconductor containing nitrogen as a V group element is referred to as a nitrogen-based III-V group mixed crystal semiconductor.

The crystal orientation of the Si substrate is (100), (1
It is preferably 10) or (111). Also, S
Amorphous S is formed between the i substrate and the III-V mixed crystal semiconductor.
It may be a structure in which i is arranged. Further, the crystal defect density of the III-V mixed crystal semiconductor is preferably 100,000 / square cm or less. It is best if the crystal defect density becomes zero. The Si substrate is not limited to a single crystal substrate, but may be a polycrystalline Si substrate or amorphous Si substrate depending on the application.
It may be a substrate.

In order to achieve the second object,
According to the method of manufacturing a compound semiconductor device of the present invention, an epitaxial layer made of a material that can be etched with a desired etching solution is formed on a polar crystal substrate, and III-V containing nitrogen as a group V element is formed on the epitaxial layer. The group III-V mixed crystal semiconductor layer is epitaxially grown, the III-V group mixed crystal semiconductor layer and the Si substrate are bonded together, and the epitaxial layer is etched with a desired etching solution to change the polar crystal substrate to the III-V group mixed crystal. It is separated from the crystalline semiconductor layer.

The III-V mixed crystal semiconductor layer and the Si substrate can be bonded together by a direct bonding method. The bonding is preferably performed by heating in the range of 400 ° C to 700 ° C, more preferably in the range of 400 ° C to 600 ° C. In addition, the III-V mixed crystal semiconductor layer and the Si substrate may be bonded to each other by providing amorphous Si on at least one of the surfaces, that is, the bonding surface, and bonding via the amorphous Si.

Furthermore, in order to achieve the third object, the semiconductor device of the present invention is such that a semiconductor element is further provided on the Si substrate of the compound semiconductor device described above. As the semiconductor element, for example, a MOS-
There are Si electronic devices such as FETs.

[0018]

[Function] When a polar crystal is epitaxially grown on a non-polar crystal, an antiphase boundary is inevitably generated. To essentially prevent this, a polar crystal may be epitaxially grown on the polar crystal. When a nitrogen-based III-V mixed crystal semiconductor is epitaxially grown on a polar crystal having a lattice constant extremely close to that of Si, for example, GaP, the occurrence of anti-phase boundary can be prevented. By bonding the obtained nitrogen-based III-V mixed crystal semiconductor to a Si substrate by a direct bonding method, a high-quality nitrogen-based nitrogen-free nitrogen-based semiconductor
A III-V mixed crystal semiconductor can be integrally formed on a Si substrate.

In the conventional direct bonding method using a material such as GaAs or InP, misfit dislocations are generated due to the difference in lattice constant from the Si substrate, which causes a problem in device characteristics. Misfit dislocations do not occur because a nitrogen-based III-V group mixed crystal semiconductor having a lattice constant substantially equal to that of the Si substrate is bonded to the Si substrate by the direct bonding method. Therefore, it is possible to integrally form a high-quality nitrogen-based III-V group mixed crystal semiconductor having neither misfit dislocations nor antiphase boundary on a Si substrate. Specifically, the crystal defect density of the compound semiconductor can be set to 100,000 defects / square cm or less, which is sufficient for the characteristics of the compound semiconductor device. The direct bonding method has a merit that the temperature of heat treatment is several hundred degrees lower than that of the epitaxial method, so that it has an advantage that the magnitude of thermal strain can be reduced.

The direct bonding method is not limited to the conventional method of directly bonding single crystals, but an amorphous Si layer which is an amorphous material may be inserted between the single crystal Si and the single crystal compound semiconductor. When affixing through amorphous Si, amorphous Si does not require crystal orientation because it is amorphous. Further, a compound semiconductor layer is selectively formed at a desired position on the Si substrate by forming a pattern in advance on the compound semiconductor to be bonded by the selective growth method or the etching method and aligning the pattern with the Si substrate. You can also

[0021]

【Example】

Example 1 In this example, a MOS-F of a Si electronic element is used.
ET (insulated gate type field effect transistor) and nitrogen type II
The same surface emitting laser diode of IV group mixed crystal semiconductor is used.
An example of an OEIC integrated on an i substrate will be described. This OEI
A structural cross-sectional view of C is shown in FIG. 1 and a method for making the same will be described. Ion implantation is performed on the Si substrate 10 having a (100) plane as a preparation for manufacturing an electronic element.
As shown in FIG. 1, B is implanted for isolation to form a p-type region 11 having a high specific resistance, P is ion-implanted, and a drain electrode 12 and a source electrode of an n-type MOS-FET are formed. 13 and a surface emitting laser diode contact layer 14 are formed.

Next, the surface emitting laser diode portion will be described. In FIG. 1, 15 is n-type GaN _0.03 P
_0.97 buffer layer (n = 1 × 10 ^-18 cm ^-3 , d = 0.1
μm), 16 is an n-type semiconductor multilayer mirror (n = 1 × 10
^-18 cm ^-3 ), 17 is an n-type GaN _0.03 P _0.97 cladding layer (n = 1 × 10 ^-18 cm ^-3 ), and 18 is a non-doped active layer, the structure of which will be described later. 19 is p-type GaN _0.03 P
_0.97 clad layer (p = 1 × 10 ^-18 cm ^-3 ), 20 is p
Type semiconductor multilayer film mirror (p = 1 × 10 ^-19 cm ^-3 ), 2
1 is a p-type GaN _0.03 P _0.97 cap layer (p = 1 × 10
^-19 cm ^-3 , d = 0.1 μm).

The active layer has a lattice mismatch of -1 with a thickness of 2 nm.
% GaN _0.07 P _0.93 layer and 1 nm thick lattice mismatch +
Using a stress-compensation superlattice layer in which 2% GaN _0.10 As _0.90 layers are alternately laminated, an effective 0.8 eV (wavelength: 1.5
It has a band gap of 5 μm). The total thickness of the active layer was 100 nm by stacking 33 periods so that the semiconductor layer had a wavelength of about 1/4. Further, in order to realize a one-wavelength resonator, the thickness of the clad layer is set to 3/8 wavelength in the semiconductor on both sides so that the mirror has one wavelength. The semiconductor multi-layer film mirror is a high-refractive-index GaN _0.03 layer with a quarter wavelength thickness in the semiconductor.
Low refractive index AlN with quarter wavelength thickness in P _0.97 layer and semiconductor
It is composed by alternately laminating _0.04 P _0.96 layers, and the number of lamination of mirror layers is 2 in order to make the reflectance 99% or more.
It was 0 times. The p-type mirror layer was heavily doped with p = 1 × 10 ⁻¹⁹ cm ^{−3 in} order to reduce the resistivity.

The surface emitting laser diode portion was separately manufactured by using a (100) GaP substrate and a gas source molecular beam epitaxy apparatus. First, a GaP buffer layer (d = 1 μm, not shown) and an AlN _0.04 P _0.96 etching layer (d = 1 μm, not shown) are grown on a GaP substrate (not shown), and then a surface emitting laser diode is manufactured. The parts are _{replaced with} p-type GaN _0.03 P _{0.97 in the} reverse order of the above description.
From the cap layer 21 to the n-type GaN _0.03 P _0.97 buffer layer 1
It was continuously grown up to 5. A metal was used as a group III raw material, phosphine and arsine were used as P and As raw materials, and a nitrogen radical in which nitrogen molecules were activated by rf plasma (high-frequency plasma) was used as a N raw material. Si and neopentane (C) were used as raw materials for the n-type dopant and the p-type dopant, respectively. The grown wafer is treated with a halogen-based reactive ion beam to leave a cylindrical surface-emitting laser diode portion having a diameter of 5 μm and AlN _0.04
The P _0.96 etching layer was etched vertically from the surface to the middle.

An n-type Si substrate and Ga processed as described above
The surface of the P substrate is treated with concentrated sulfuric acid to make it hydrophilic, and the contact layer 14 for the surface emitting laser diode and the n-type GaN _0.03 P
_{The 0.97} buffer layers 15 were put together, and heat-treated for 30 minutes in a hydrogen atmosphere at 450 ° C. to bond them together. After injecting a positive type resist between the two bonded substrates, the entire bonded substrate is exposed, and the resist remains around the cylindrical surface emitting laser diode, but there is no resist around the GaP substrate. did. An AlN _0.04 P _0.96 etching layer was selectively etched from the lateral direction of this substrate with a hydrofluoric acid-based solution to peel off the GaP substrate. Next, the resist was removed and the structure shown in FIG. 1 was produced.

Thereafter, a protective SiO ₂ oxide film is formed on a desired portion of the surface emitting laser diode surface by a CVD (chemical vapor deposition) method, and a transparent electrode is formed on the p-type GaN _0.03 P _0.97 cap layer 21. 22 was formed. Next, a SiO ₂ oxide film for element isolation and a gate insulating film were formed by a usual method, and finally, a gate electrode and an electric wiring were formed using Al to complete a MOS-FET and an OEIC. The produced OEIC is a MOS-FET for driving a laser diode.
When a voltage was applied to the gate electrode of, the current was injected into the surface emitting laser diode, laser oscillation occurred, and laser light was emitted in the vertical direction from the Si substrate.

The crystal defect density of another compound semiconductor layer portion prepared by performing epitaxial growth and substrate bonding by the same method was measured and found to be 100,000 / cm 2 or less, and the anti-phase boundary was used. Was not recognized. Therefore, the OEIC of this example had a long life. As the n-type Si substrate, a substrate having a crystal orientation of (100) plane was used.
Similar results were obtained using a Si substrate having a 1) plane.

<Embodiment 2> FIG. 2 shows the pin of the second embodiment.
The structural sectional drawing of a photodiode is shown. In FIG.
30 is an n-type GaN _0.03 P _0.97 buffer layer (n = 2 × 10
^-18 cm ^-3 , d = 1.0 μm), 31 is 2 nm thick GaN _0.14 P _0.86 with a lattice mismatch of -2% and 2 nm thick GaN _0.10 As _0.90 with a lattice mismatch of + 2%. Non-doped stress-compensated superlattice optical absorption layer (n = 1 × 10 ⁻¹⁵ cm) that has a band gap of 0.5 eV stacked.
^-3 , d = 0.5 μm), 32 is a p-type GaN _0.03 P _0.97 buffer layer (p = 2 × 10 ^-18 cm ^-3 , d = 1.0 μm)
m) and 33 are semi-metal GaNAs contact layers (d = 0.
01 μm).

This portion was formed by selective growth on a (111) GaP substrate using an actinic ray epitaxy apparatus. First, SiO ₂ is deposited on a GaP substrate (not shown) by a thermochemical deposition method, and a SiO ₂ mask with holes having a diameter of 5 μm is formed by photolithography. After growing a GaP buffer layer (d = 1 μm, not shown) and an AlN _0.04 P _0.96 etching layer (d = 1 μm, not shown) on the holes of the mask of this substrate, the above-mentioned light receiving portion is described above. P-type GaN _0.03 P in the reverse order of
_{The 0.97} buffer layer 32 to the n-type GaN _0.03 P _0.97 buffer layer 30 were continuously grown. Metallic Al is used as a raw material of Al, triethylgallium is used as a raw material of Ga, phosphine and arsine are used as raw materials of P and As, and N is
A nitrogen radical in which nitrogen molecules were activated by rf plasma was used as the raw material. Si and Be were used as raw materials for the n-type dopant and the p-type dopant, respectively.

On the other hand, silane and phosphine are used as raw materials on an n-type Si substrate (n = 2 × 10 ^-18 cm ^-3 ) 35 having a (100) plane to form a plasma chemical deposition method of 0.1 μm.
A thick n-type amorphous Si layer 34 was deposited. In addition,
The n-type amorphous Si layer 34 was deposited in high-power plasma to contain microcrystals in order to reduce the specific resistance. Next, by photolithography, the n-type amorphous Si layer 34 was selectively left only in the portion to which the light receiving portion was directly bonded, and the other portions were removed.

The GaP substrate and Si substrate 35 processed as described above are subjected to hydrophilic treatment on the surface with concentrated sulfuric acid, and then 40
Heat treatment was carried out for 30 minutes in a hydrogen atmosphere at 0 ° C. to bond them together. Then, the AlN _0.04 P _0.96 etching layer was etched with a hydrofluoric acid-based solution, the GaP substrate was removed, and the structure of the pin photodiode shown in FIG. 2 was produced. Finally, a polyimide film 36 was formed in a predetermined shape for surface protection, and an electrode 37 and an electrode 38 were formed to obtain a pin photodiode.

Since infrared light having a bandgap of 1.1 eV or less, that is, a wavelength of 1.1 μm or more is transparent to Si, the pin photodiode of this embodiment receives light from the Si substrate side. The pin photodiode of the present embodiment can receive far-infrared light up to 2.4 μm, which is difficult for the conventional photodiode because the band gap of the light absorption layer is 0.5 eV.

The crystal defect density of another compound semiconductor portion prepared by epitaxial growth and substrate bonding by the same method was measured to be 100,000 pieces / square cm.
Below, and no anti-phase bandary was recognized. Therefore, the pin photodiode of this example has a long life. Further, as the n-type Si substrate, a substrate having a crystal orientation of (100) plane was used.
Similar results were obtained using a Si substrate having a (111) plane.

[0034]

According to the present invention, a nitrogen-based compound II is formed on a Si substrate.
It was possible to obtain a compound semiconductor device in which the IV group mixed crystal semiconductor was integrally formed without generating an antiphase boundary. The crystal defect density of this mixed crystal semiconductor was 100,000 defects / square cm or less. Also, a semiconductor device monolithically integrated with the Si electronic device could be obtained. Further, such a compound semiconductor device could be easily manufactured.

[Brief description of drawings]

FIG. 1 is a structural cross-sectional view of an OEIC according to a first embodiment of the present invention.

FIG. 2 is a structural cross-sectional view of a pin photodiode of Example 2 of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... n-type Si substrate 11 ... high-resistivity p-type region 12 ... drain electrode 13 ... source electrode 14 ... contact layer 15, 30 ... n-type GaN _0.03 P _0.97 buffer layer 16 ... n-type semiconductor multilayer film mirror 17 ... n _-Type GaN _0.03 P _0.97 clad layer 18 ... Non-doped active layer 19 ... P-type GaN _0.03 P _0.97 clad layer 20 ... P-type semiconductor multilayer film mirror 21 ... P-type GaN _0.03 P _0.97 Cap layer 22 ... Transparent electrode 31 ... Stress compensation type super Lattice light absorption layer 32 ... p-type GaN _0.03 P _0.97 buffer layer 33 ... semi-metal GaNAs contact layer 34 ... n-type amorphous Si layer 35 ... n-type Si substrate 36 ... polyimide film 37, 38 ... electrode

Claims (12)

[Claims] 1. A group III-V mixed crystal semiconductor containing nitrogen as a group V element having no anti-phase boundary is arranged on a Si substrate, and a compound semiconductor element is provided on the group III-V mixed crystal semiconductor. A compound semiconductor device characterized by the above. 2. The compound semiconductor device according to claim 1, wherein the Si substrate has a crystal orientation of (100), (110).
Alternatively, the compound semiconductor device is (111). 3. A compound semiconductor device according to claim 1 or 2, wherein amorphous Si is arranged between the Si substrate and the III-V mixed crystal semiconductor. 4. The compound semiconductor device according to claim 1, 2 or 3, wherein the III-V mixed crystal semiconductor has a crystal defect density of 100,000 / square cm or less. . 5. The compound semiconductor device according to claim 1, wherein the compound semiconductor element is a light emitting diode. 6. The compound semiconductor device according to claim 5, wherein the light emitting diode is a laser diode. 7. The compound semiconductor device according to claim 1, wherein the compound semiconductor element is a photodiode. 8. A semiconductor device comprising the compound semiconductor device according to claim 1 and a semiconductor element provided on the Si substrate. 9. The semiconductor device according to claim 8, wherein the semiconductor element is an electronic element. 10. A step of forming, on a polar crystal substrate, an epitaxial layer made of a material which can be etched with a desired etching solution, and a III-V mixed crystal semiconductor layer containing nitrogen as a V group element on the epitaxial layer. Is epitaxially grown, the step of adhering the III-V mixed crystal semiconductor layer and the Si substrate, and the epitaxial layer is etched with a desired etching solution to form the polar crystal substrate with III-
A method of manufacturing a compound semiconductor device, comprising a step of separating from a group V mixed crystal semiconductor layer. 11. The method of manufacturing a compound semiconductor device according to claim 10, wherein the polar crystal substrate is GaP. 12. The method of manufacturing a compound semiconductor device according to claim 10, wherein the step of bonding the group III-V mixed crystal semiconductor layer and the Si substrate is an amorphous material provided on at least one surface thereof. A method for manufacturing a compound semiconductor device, which comprises laminating via Si.