JPH0444152U - - Google Patents
Info
- Publication number
- JPH0444152U JPH0444152U JP8659290U JP8659290U JPH0444152U JP H0444152 U JPH0444152 U JP H0444152U JP 8659290 U JP8659290 U JP 8659290U JP 8659290 U JP8659290 U JP 8659290U JP H0444152 U JPH0444152 U JP H0444152U
- Authority
- JP
- Japan
- Prior art keywords
- metallization
- ceramic body
- attached
- layer ceramic
- top surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001465 metallisation Methods 0.000 claims description 7
- 239000000919 ceramic Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000002356 single layer Substances 0.000 claims description 3
- 238000007789 sealing Methods 0.000 claims 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Description
第１図はこの考案による半導体用パツケージの
斜視図、第２図は、第１図のＡ−Ａ線による断面
図、第３図は従来の半導体用パツケージの斜視図
、第４図は、第３図のＢ−Ｂ線による断面図を示
す。
図において、６，７，８は外部リード、１１，
１２，１３は裏面のメタライズ、２１は一層のセ
ラミツク体、２２，２３，２４は裏面のメタライ
ズ、２５，２６，２７はスルーホールを示す。な
お、各図中の同一符号は同一または相当部分を示
す。
FIG. 1 is a perspective view of a semiconductor package according to this invention, FIG. 2 is a sectional view taken along line A-A in FIG. 1, FIG. 3 is a perspective view of a conventional semiconductor package, and FIG. 3 is a cross-sectional view taken along line BB in FIG. 3. In the figure, 6, 7, 8 are external leads, 11,
Reference numerals 12 and 13 indicate metallization on the back surface, 21 indicates a single-layer ceramic body, 22, 23, and 24 indicate metallization on the back surface, and 25, 26, and 27 indicate through holes. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
イズに外部リードが取り付けられ、前記一層のセ
ラミツク体の上面に封止用のキヤツプが取り付け
られるメタライズと、このメタライズと独立して
形成された配線用のメタライズとを備え、前記上
面の各メタライズと裏面の各メタライズとの接続
をスルーホールを介して導通させたことを特徴と
する半導体用パツケージ。 External leads are attached to the metallization formed on the back side of the single-layer ceramic body, and a sealing cap is attached to the top surface of the single-layer ceramic body, and metallization for wiring formed independently of this metallization. What is claimed is: 1. A package for a semiconductor, characterized in that each metallization on the top surface and each metallization on the back surface are electrically connected through through holes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8659290U JPH0444152U (en) | 1990-08-17 | 1990-08-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8659290U JPH0444152U (en) | 1990-08-17 | 1990-08-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0444152U true JPH0444152U (en) | 1992-04-15 |
Family
ID=31818338
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8659290U Pending JPH0444152U (en) | 1990-08-17 | 1990-08-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0444152U (en) |
-
1990
- 1990-08-17 JP JP8659290U patent/JPH0444152U/ja active Pending