JPH0442936Y2 - - Google Patents

Info

Publication number
JPH0442936Y2
JPH0442936Y2 JP1986110841U JP11084186U JPH0442936Y2 JP H0442936 Y2 JPH0442936 Y2 JP H0442936Y2 JP 1986110841 U JP1986110841 U JP 1986110841U JP 11084186 U JP11084186 U JP 11084186U JP H0442936 Y2 JPH0442936 Y2 JP H0442936Y2
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
external
external leads
circuit boards
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1986110841U
Other languages
English (en)
Japanese (ja)
Other versions
JPS6316449U (US07902200-20110308-C00004.png
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986110841U priority Critical patent/JPH0442936Y2/ja
Publication of JPS6316449U publication Critical patent/JPS6316449U/ja
Application granted granted Critical
Publication of JPH0442936Y2 publication Critical patent/JPH0442936Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Casings For Electric Apparatus (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Combinations Of Printed Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP1986110841U 1986-07-18 1986-07-18 Expired JPH0442936Y2 (US07902200-20110308-C00004.png)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986110841U JPH0442936Y2 (US07902200-20110308-C00004.png) 1986-07-18 1986-07-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986110841U JPH0442936Y2 (US07902200-20110308-C00004.png) 1986-07-18 1986-07-18

Publications (2)

Publication Number Publication Date
JPS6316449U JPS6316449U (US07902200-20110308-C00004.png) 1988-02-03
JPH0442936Y2 true JPH0442936Y2 (US07902200-20110308-C00004.png) 1992-10-12

Family

ID=30990216

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986110841U Expired JPH0442936Y2 (US07902200-20110308-C00004.png) 1986-07-18 1986-07-18

Country Status (1)

Country Link
JP (1) JPH0442936Y2 (US07902200-20110308-C00004.png)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5648627B2 (ja) * 2011-12-23 2015-01-07 株式会社デンソー 電力変換装置

Also Published As

Publication number Publication date
JPS6316449U (US07902200-20110308-C00004.png) 1988-02-03

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