JPH0439097B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In branch trace control mainly used for debugging and diagnostic purposes, it is possible to check whether a branch source address and a branch destination address are within a preset upper and lower limit address range. The check is performed using an existing arithmetic circuit, thereby reducing the amount of hardware required.

[Industrial application field]

The present invention relates to a control method for branch tracing in which instruction addresses of a branch source and a branch destination are stored in main memory when a branch condition is satisfied, mainly for use in debugging, diagnosis, and the like.

[Conventional technology]

In branch trace control, a specific address range is often set for the branch source and branch destination addresses, and when this is done, the branch source and branch destination addresses when branching by a branch instruction are set to the set address. Must be compared to the upper and lower addresses of the range.

FIG. 6 is a block diagram showing a conventional example of branch trace control.

FIG. 6 shows only the portions related to branch tracing. In the figure, 1 is the arithmetic and logic unit (ALU), 2 is the A register (AR), 3 is the B register (BR), 4 is the instruction address register (iAR), and 6 is the Z register (ZR ), each of which is one of the main components of the central processing unit.

51 and 52 indicate partial areas of the main memory (MS) 5, 51 is an area called local storage (LS), and 52 is a table (hereinafter referred to as BT table) in which branch destination and branch source addresses are written. ) is the area to write.

81, 82, 83 and 84 are registers and comparison circuits provided for branch tracing.

81 is a register (L) for setting the lower limit address.
-LMT-REG), and 82 is a register (U-LMT-REG) for setting the upper limit address.

A comparison circuit 1 83 compares the contents of the instruction address register (iAR) 4 and the contents of the L-LMT-REG 81 . 84 is a comparison circuit 2, which compares the contents of the instruction address register (iAR) 4 and U-LMT.
-Compare with the contents of REG82.

85 is an AND gate, and comparison circuits 1 and 83
AND conditions of the outputs of the comparison circuits 2 and 84 are taken.

86 is a delay AND circuit, and AND gate 85
Find the AND condition for the two outputs.

10 is a BT control unit that performs control for branch tracing.

In a normal operating state when a general instruction is executed in the central processing unit, an instruction is read from the main memory 5 (program area is not shown) at the address indicated by the instruction address register (iAR) 4 to an instruction register (not shown). The decoded data indicated by the instruction is read into the A register 2 and the B register 3, the ALU 1 performs the operation indicated by the instruction, and the result is read into the Z register 6. iAR4
The contents of + are determined by a count-up mechanism (not shown).
1 and the instructions are executed one after another.

When the branch condition calculation instruction is executed and the condition is satisfied, the branch instruction is read into the instruction register, and the address of the branch destination is set in iAR4. The instruction at the address indicated by this iAR4 is read and the branch destination instruction is executed.

When performing branch tracing for debugging or diagnosis, first, a pointer indicating the start address on the BT table 52 in which the branch destination address and branch source address are stored is stored in the LS area 51 of the main memory. Write the byte count indicating the remaining area of the BT table, and set the lower limit address of the branch source and branch destination address to L-LMT-
In REG81, set the upper limit address to U-LMT-REG8
Set to 2.

The BT enable (+BT-ENB) signal is a signal that can be set arbitrarily by the operator, and is set to "1" when branch tracing is desired.

When the branch instruction is read into the instruction register and the BT enable signal is “1”, the BT control unit 10
is activated, the control of the BT control unit 10 is prioritized, and fetching of the branch destination instruction is suspended.

The content of iAR4 (branch source instruction address) is checked by comparison circuits 1 and 83 to see if it is greater than or equal to the lower limit address, and by comparison circuits 2 and 84 to see if it is less than or equal to the upper limit address, and when both are true. , AND gate 85 is opened. then
The branch destination memory address is set in iAR4,
Similar comparisons are made in comparison circuits 1 and 83 and comparison circuits 2 and 84, and when both are established,
AND gate 85 is opened. The two outputs of the AND gate 85 are input to a delay AND circuit 86, and if both times are true, BT OK (+BT-
OK) becomes “1”.

BT enable is set to “1”,
If BT OK is “1”, AND gate 7
is opened, the branch source and branch destination addresses are written to the BT table address indicated by the pointer in LS51, the pointer is added by the number of bytes of write data, the byte count is subtracted by the number of bytes, and the next start address and Updated to indicate the number of bytes remaining. All these operations are BT
This is performed under the control of the control section 10.

In this way, in the conventional method, dedicated registers L-LMT-REG and U are used for branch tracing.
-LMT-REG and comparison circuits 1 and 2 are required.

[Problem that the invention seeks to solve]

As mentioned above, the conventional method requires a dedicated register and comparison circuit for branch tracing.

The present invention aims to provide a novel branch trace control method that does not require such dedicated registers and comparison circuits and reduces the amount of hardware.

[Means for solving problems]

FIG. 1 shows a principle block diagram of the branch trace control method of the present invention.

In Figure 1, ALU1, A register 2, B
The register 3, iAR 4, main memory 5, LS 51, BT table 52 and AND gate 7 represent the same objects as in FIG.

Reference numeral 9 is a carry and zero output check circuit, which outputs a carry output (which becomes "1" when the operation result is negative) and a zero output (which becomes "1" when the operation result is zero) which the arithmetic circuit (ALU) 1 originally has. 1'') is input, and the condition is checked by a predetermined calculation.

10 is a BT control means, which controls reading from the main memory LS area, A register 2, B register 3 and
Controls calculations using ALU1.

When performing a branch trace, first, in addition to a pointer and a byte count, upper and lower limit addresses of branch source and destination addresses are stored in the LS area 51 of the main memory. These operations are usually performed by an auxiliary processor, such as a so-called service processor.

When the program runs in the central processing unit and the branch condition is satisfied and a branch is executed, the BT control means 10 is activated, and the BT control means 10 issues a BT execution request, which is given priority. , fetching of the branch destination instruction is suspended, and branch trace control by the BT control means 10 is started.

The control of the BT control means 10 is started, and the branch address and then the branch destination address are set to one input of the arithmetic unit (ALU) 1, and the upper limit address and the upper limit address stored in the LS area 51 of the main memory are set to the other input. Fetch the lower limit address and set it, (lower limit address) - (branch source address), (upper limit address) - (branch source address), (lower limit address) - (branch destination address), (upper limit address) - (branch destination) address), and execute four operations.

The carry output and zero output of the four operation results in the ALU 1 are input to the carry and zero output test circuit 9, where the next test is performed.

That is, the carry output is "1" or the zero output is "1" in the operation results of and, and the carry output is "0" or the zero output is "1" in the operation results of and. When all the conditions are satisfied, the BT OK signal is set to "1".

BT enable is set to “1”,
If BT OK is “1”, AND gate 7
is opened, and the branch source address and branch destination address are written into the BT table address indicated by the pointer in the LS51. Also, the write pointer is read, the number of bytes of data is added and written, the byte count is subtracted by the number of bytes, and
As in the conventional example, the information is updated to indicate the next start address and the number of remaining bytes.

FIG. 2 is a diagram showing an instruction and branch trace execution sequence.

In the figure, the horizontal axis indicates time, and each vertical line indicates a machine cycle of the central processing unit. While an instruction is running in the central processing unit, an ALU use request is issued for each instruction, and when there is no request with a higher priority, that instruction uses the ALU to execute the instruction.
The priority order of ALU usage requests is as follows.

1st place: Branch trace request 2nd place: Instruction fetch request 3rd place: Instruction execution request An instruction execution request for one general instruction is issued in a cycle, the ALU usage right is obtained, and the instruction is executed in the cycle. At the end of the cycle, a request to execute the next instruction (branch instruction) is issued, the right to use the ALU is obtained, and the instruction is executed in the cycle. Since this is a branch instruction, the BT control means is activated,
Issue a trace request at the end of the cycle. A request to fetch the branch destination instruction is issued from execution of the branch instruction. Since the trace request has higher priority than the instruction fetch request, the trace request obtains the right to use the ALU and branch trace is executed.

The branch trace execution ends in a cycle,
Since the trace request disappears, the instruction fetch request becomes
The right to use the ALU is obtained and the branch destination instruction is fetched.
At the end of the cycle, an instruction execution request is issued, and the branch destination instruction is executed at the end of the cycle.

[Effect]

Next, it will be explained that with the above configuration, it is possible to check whether the branch source and branch destination addresses are within the set upper and lower limit addresses.

Branch source (same as branch destination) address (x
) are the lower and upper limit addresses (L-
LMT, U-LMT), there are the following five cases as shown in Figure 3a.

(a) x<L-LMT, (b) x=L-LMT, (c) L-LMT<x<U-LMT, (d) x=U-LMT, (e) U-LMT<x, above (L-LMT) for each of the five cases -
The carry output and zero output for the operation results of x and (U-LMT)-x are as shown in FIG. 3b.

Therefore, when the branch source or branch destination address x is within the upper and lower limit addresses, that is, (b),
The common OK conditions for carry output and zero output for the operation results of (L-LMT)-x and (U-LMT)-x in cases (c) and (d) are as shown in Figure 3b. As shown in the column below, if this is satisfied with the four operations, BT is OK.

By performing comparison operations using existing arithmetic circuits as described above, there is no need for the 4-byte dedicated registers and comparison circuits shown at 81 to 84 in the sixth conventional example, and Shown 1
It requires only an extremely small circuit of bits, and the amount of hardware can be greatly reduced.

〔Example〕

According to the embodiments shown in FIGS. 4 and 5 below,
The present invention will be explained in more detail.

FIG. 4 is a block diagram of an embodiment of the present invention.

FIG. 5 is a time chart of an embodiment of the present invention.

In FIG. 4, the same reference numerals as in FIG. 5 indicate the same objects.

Reference numerals 91 to 95 shown in FIG. 4 are embodiment circuits of the contents of the carry and zero output test circuit 9 shown in FIG.

91 is an exclusive OR circuit (EOR), which receives the carry output of the arithmetic unit (ALU) 1 and the output of the cycle count 92 as inputs.

The cycle counter 92 is a circuit that counts +1 by a clock and resets it to "0" by its own output. Therefore, as shown in the time chart of FIG. 5, "0" and "1" are repeated every cycle.

93 is an OR gate, which inputs the output of EOR 91 and the zero output of arithmetic unit (ALU) 1.

94 is an AND gate, which receives the output of the OR gate 93 and the output of the circuit 95 as inputs.

The circuit 95 is a circuit that is reset to "1" by the output of the OR gate 93 and becomes "0" in the next cycle.

In the first cycle, if the cycle count 92 is "0" and the carry output is "1", the output of the EOR 91 is "1".

When the output of EOR91 becomes "1", the output of OR gate 93 becomes "1" regardless of the value of zero output.
Since the circuit 95 is "1" in the initial state, the output of the AND gate 94 becomes "1" and the circuit 95 is reset to "1".

In the next cycle, the cycle count 92 becomes "1", and if the carry output is "0",
The output of EOR91 becomes "1". Therefore, AND
The output of gate 94 becomes "1" and circuit 95 is reset to "1".

In the next cycle, the cycle count 92 becomes "0" again and the same cycle occurs.

In the next cycle, the cycle count 92 becomes "1" again, the same thing as the cycle is performed, and the AND gate 94 outputs BT-OK "1".

In this way, in each of the above cycles, if the zero output becomes "1", the output of the AND gate 94 becomes "1" even if the output of the EOR 91 is "0".

If there is even one cycle in which the output of the OR gate 93 is "0" among the above four cycles, the output of the AND gate 94 is "0".
Therefore, the circuit 95 is not reset to "1",
The output of the AND gate 94 becomes "0".

When a branch condition is satisfied and a branch is taken in the circuit of FIG. 4, the situation in which branch tracing is executed is as follows, as shown in the time chart of FIG.

(1) L- from LS51 to A register (AR) 2
LMT is set, and the branch source address is set in B register (BR) 3. The cycle count at this time is "0".

(2) In the next cycle, AR−
The BR calculation is performed, and the carry and zero output of the calculation result is checked by circuits 91 to 95.

(3) U-LMT is set to AR2 from LS51. The cycle count 92 becomes "1".

(4) In the next cycle, AR−
The BR calculation is performed, and the carry and zero output of the calculation result is checked by circuits 91 to 95.

(5) BR3 has instruction address register (iAR) 4
The branch destination address is set from AR2.
L-LMT is set from LS51. The cycle count becomes "0".

(6) In the next cycle, AR−
The BR calculation is performed, and the carry and zero output of the calculation result is checked by circuits 91 to 95.

(7) U-LMT is set to AR2 from LS51. The cycle count becomes "1".

(8) In the next cycle, in ALU1, AR−
The BR calculation is performed, and the carry and zero output of the calculation result is checked by circuits 91 to 95.

(9) If the output of the AND gate 94, ie, BT-OK, is “1”, the branch source address in the Z register (ZR) and the branch destination address in BR3 are written to the BT table 52.

(10) The byte count is cassetted from LS51 to AR2, and "8" is set to BR3.
The value “8” is because the branch source and branch destination address data written in the BT table 52 is 8 bytes.

(11) In the next cycle, AR
−BR calculation is performed, and the result is LS5
Update the byte count value in 1.

(12) A pointer is set in AR2 from LS51.

(13) In the next cycle, AR
+BR calculation is performed, and depending on the result, LS5
Update the value of the pointer in 1.

This completes one branch trace and prepares for the next branch trace.
The BT control unit 10 stops the instruction execution request, the right to use the ALU 1 is transferred to the program instructions, the branch destination instructions are fetched, and the instructions are executed one after another.

〔Effect of the invention〕

As described above, according to the present invention, since address comparison is performed using existing arithmetic circuits, the amount of hardware can be reduced, and the practical effects thereof are extremely large.

[Brief explanation of drawings]

Figure 1 is a block diagram of the principle of the present invention, Figure 2 is a time chart during branch trace execution, Figure 3 is a diagram showing BT OK conditions, Figure 4 is a block diagram of an embodiment of the present invention, and Figure 5. 6 is a time chart of an embodiment of the present invention, and FIG. 6 is a block diagram of a conventional example. In the drawing, 1 is an arithmetic unit (ALU), 2 is A
Register (AR), 3 is B register (BR), 4 is instruction address register (iAR), 5 is main memory, 6
is a Z register (ZR), 7 is an AND gate, 9 is a carry and zero main check circuit, 10 is a BT control unit (means), 51 is an LS area, 52 is a BT table area,
81 and 82 are registers, 83 and 84 are comparison circuits,
85 is an AND gate, 86 is a delay AND circuit, 91
is an exclusive OR circuit (EOR), 92 is a cycle count, 93 is an OR gate, 94 is an AND gate,
Reference numeral 95 indicates a reset 1 circuit.

Claims (1)

[Scope of Claims] 1. In a data processing device that performs branch trace processing in which instruction addresses of a branch source and a branch destination are stored in a specific area of a main storage device when a branch condition is met, the method is activated when a branch condition is met. and setting a branch source address and then a branch destination address to one input of an arithmetic circuit included in the data processing device,
BT control means extracts and sets an upper limit address and a lower limit address stored in a specific area in advance to the other input for each of them, and executes four difference calculations; Input the carry output which becomes "1" when , and the zero output which becomes "1" when the result of the difference operation is zero,
a carry and zero output inspection circuit that inspects the carry output and zero output in the results of each operation, and outputs a signal allowing branch tracing when all of the operation results of each operation satisfy a predetermined condition; When performing branch tracing, store the upper and lower limits of the branch source and branch destination addresses in a specific area of the main memory before running the program, and when the program runs and the branch condition is met. The BT control means is activated and obtains the right to use the arithmetic circuit, and the arithmetic circuit of the data processing device is configured to perform a comparison operation of the branch source and branch destination addresses with upper and lower limit values. A branch trace control method featuring: