JPH04373234A - Digital signal receiver - Google Patents

Abstract

PURPOSE:To improve the sensitivity of the receiver by deciding the polarity of an output code of an A/D converter, integrating an output signal and feeding it back to a differential input terminal so as to cancel an offset in the output code. CONSTITUTION:An intermediate frequency signal is inputted to a mixer 2 and a base band signal via a low pass filter 3 is separated into I and Q channel signals by a 90 deg. power distributer 4 and they are inputted to operational amplifiers 5a, 5b. The signal converted by A/D converters 5a, 5b is given to a code deciding device 19, and a data resulting from applying sign decision to the I channel signal and a Q channel signal are multiplied by a multiplier 16, from which an error signal is outputted. Output codes extracted from code inverters 8a, 8b and signals from inverters 9a, 9b are integrated and a difference is extracted as an offset and fed back to the operational amplifiers 5a, 5b as a reference voltage via operational amplifiers 14a, 14b. A loop filter 17 and a numeral controlled oscillator 18 are connected to a post-stage of the multiplier 16 and the signal is inputted to the mixer 2.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing type phase-locked receiver using an analog-to-digital converter.

0002

2. Description of the Related Art In the prior art, a constant voltage was used as a reference voltage for an operational amplifier provided before an analog-to-digital converter.

0003

[Problems to be Solved by the Invention] In such a conventional digital signal processing type phase-locked receiving device, there is an error in the reference voltage of the operational amplifier installed in front of the analog-to-digital converter, and an error in the analog voltage up to the stage before the analog-to-digital converter. Due to the offset generated by the mixer, the input signal of the analog-to-digital converter contains an unnecessary offset, and
The analog-to-digital converter itself includes an offset that occurs during conversion, and the output code of the analog-to-digital converter includes an unnecessary offset.Furthermore, the offset drifts due to temperature changes and changes over time, but the output code of the analog-to-digital converter Including an offset is equivalent to inputting a signal different from the originally required input signal, which has the disadvantage of not operating optimally and reducing sensitivity.

SUMMARY OF THE INVENTION The present invention aims to eliminate such drawbacks and provides a digital signal receiving apparatus having means for suppressing a decrease in sensitivity and achieving optimum operation.

[0005]

[Means for Solving the Problems] The present invention provides a digital signal receiving apparatus that includes two analog-to-digital converters corresponding to an in-phase signal and a quadrature signal, and demodulates a carrier wave subjected to two-phase phase shift keying. It is provided before each analog-to-digital converter, has first and second differential input terminals, and feeds back the input signal that is converted from analog to digital by the analog-to-digital converter corresponding to the first differential input terminal. a first operational amplifier that determines the polarity of the output code of the analog-to-digital converter; a sign determiner that inverts the output signal of the sign determiner; and an inverter that integrates the output signal of the sign determiner. an analog integrator that integrates the output signal of the inverter, the output voltage of this analog integrator is used as a differential input, and the output voltage is used as a second differential input of the first operational amplifier. The second operational amplifier is fed back to the end.

[0006]

[Operation] An input signal to be converted from analog to digital by the analog-to-digital converter is supplied to the differential input terminal of the first operational amplifier provided before each of the analog-to-digital converters. It integrates the output signal of a sign determiner that determines the polarity of the output code of the analog-to-digital converter, and also integrates the output signal of an inverter that inverts the output signal of this sign determiner, and calculates the output voltage of these analog integrators. The output voltage of the second operational amplifier having differential input is fed back to the second input terminal of the first operational amplifier. Thereby, the voltage of the DC component in the input signal of the analog-to-digital converter can be controlled, and the average value of the output code of the analog-to-digital converter can be made zero.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of this embodiment. The embodiment shown in FIG. 1 is an example of a receiving apparatus that performs BPSK demodulation, and shows a case where a Costas loop is used for carrier wave recovery.

As shown in FIG. 1, this embodiment includes two analog-to-digital converters 6a and 6b corresponding to the in-phase signal and the quadrature signal. An input signal that is provided before each of the converters 6a and 6b, has first and second differential input terminals, and is converted from analog to digital by an analog-to-digital converter corresponding to the first differential input terminal. Operational amplifiers 5a and 5b to be fed back, sign determiners 8a and 8b that determine the polarity of the output code of the analog-to-digital converters 6a and 6b, and inverters 9a and 9a that invert the output signals of the sign determiners 8a and 8b. 9b, a combination circuit of resistors 10a, 10b and capacitors 12a, 12b, which are analog integrators that integrate the output signals of sign determiners 8a and 8b, and inverter 9a.
Resistors 11a, 11b and capacitors 13a, 13b are analog integrators that integrate the output signals of 9b and 9b.
and operational amplifiers 14a and 14b whose output voltages are fed back to second differential input terminals of operational amplifiers 5a and 5b.

Next, the operation of this embodiment will be explained. The intermediate frequency signal is input to mixer 2 from input terminal 1 . The baseband signal that has passed through the low-pass filter 3 is divided into I and Q channels by a 90° power divider 4 and input to operational amplifiers 5a and 5b for level conversion. Next, analog-to-digital conversion is performed by analog-to-digital converters 6a and 6b, and data obtained by determining the sign of the I channel signal by a sign determiner 19 is multiplied by the Q channel signal by a multiplier 16, and an error signal is output. . Also,
The sign of the output of the analog-to-digital converter taken out by sign inverters 8a and 8b and the signal whose sign was inverted by inverters 9a and 9b are connected to resistors 10a, 10b, 11a and 11b, capacitors 12a, 12b, 13a and 1.
Integrate with the time constant determined by 3b. At this point, an offset is extracted as the difference between the sign-integrated voltage and the inverted sign-integrated voltage. The extracted offset is sent to operational amplifiers 5a and 5 via operational amplifiers 14a and 14b.
It is fed back as the reference voltage of b. A loop filter 17 and a numerically controlled oscillator 18 are connected to the subsequent stage of the multiplier 16, and are inputted to the mixer 2 as a local oscillation signal.

It is now assumed that the output voltage of the sign determiner 8a is 0V when the output code of the analog-digital converter 6a is a code representing a positive value, and +5V when the output code is a code representing a negative value. To explain the case where the output code of has a positive offset, the modulus of the time percentage in which the output voltage of the sign determiner 19 is 0V is greater than the time percentage in which the output voltage is +5V. That is, capacitor 12
The voltage of the capacitor 13a is higher than the voltage of the capacitor 13a. Then, the first operational amplifier 14a becomes the second operational amplifier 5.
Since the reference voltage of a is increased, the input signal of the analog-to-digital converter 6a changes in a direction that cancels out the offset, that is, in a negative direction. In this way, 5
a, 5b, 6a, 6b, 8a, 8b, 9a, 9b-14
The circuit consisting of a and 14b operates such that the output code of the analog-to-digital converter represents a positive input signal and a negative input signal an equal proportion of the time. Although the offset included in the output code of the analog-to-digital converter fluctuates due to temperature changes and changes over time, the rate of change over time is sufficiently small compared to the frequency of the originally required signal component. In the digital signal processing type phase synchronized receiver of the present invention, by utilizing this property of offset, the resistors 10a, 10b, 11a and 11b, the capacitor 12
By designing the time constant determined by a, 12b, 13a, and 13b to be sufficiently smaller than the fluctuation of the offset and sufficiently larger than the signal component, the average value of the output code of the analog-to-digital converter is made zero. That is,
Offsets included in the output code of the analog-to-digital converter can be canceled out.

[0011]

As described above, the present invention has the effect of improving the sensitivity of a digital signal processing type phase-locked receiver by canceling the offset in the output code of an analog-to-digital converter.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing the configuration of an embodiment of the present invention.

[Explanation of symbols]

1 Input terminal 2 Mixer 3 Low pass filter 490° power divider 5a, 5b, 14a, 14b Operational amplifier 6a, 6b
Analog-digital converters 7a, 7b Accumulators 9a, 9b Inverters 10a, 10b, 11a, 11b Resistors 12a, 1
2b, 13a, 13b Capacitor 8a, 8b, 19
Sign determiner 16 Multiplier 17 Loop filter 18 Numerically controlled oscillator

Claims (1)

[Claims] Claim 1. A digital signal receiving device comprising two analog-to-digital converters corresponding to an in-phase signal and a quadrature signal, and demodulating a carrier wave subjected to two-phase phase shift keying, wherein a stage before each of the analog-to-digital converters is provided. a first operational amplifier, which is provided in , a sign determiner that determines the polarity of the output code of the analog-to-digital converter, an inverter that inverts the output signal of the sign determiner, an analog integrator that integrates the output signal of the sign determiner, and the inverter. an analog integrator that integrates the output signal of the amplifier, and a second operational amplifier whose output voltage is used as a differential input and whose output voltage is fed back to the second differential input terminal of the first operational amplifier. A digital signal receiving device comprising an operational amplifier.